| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2502839551 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3938103109 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3373121917 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2706760841 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3683000596 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3283233154 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3266983508 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2898211785 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1389808067 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.413363314 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.688629019 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3854201641 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2183339557 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1160271604 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2075963877 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.557198387 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2554981315 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2749140350 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.858768291 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3542892962 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1138917404 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1434883396 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1813753150 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1254511536 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.875066232 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2759739309 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1554007047 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.988167090 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2712355801 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1683244336 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3333810670 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2812647054 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1093099527 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.971937744 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2947122682 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3740717414 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1252102961 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1324258261 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3947633244 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1872153177 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.730676658 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2066786160 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3057880846 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2256622146 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.499516544 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3022895254 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.769863691 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3709366448 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1104537007 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1848394067 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.609099651 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.902233005 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.156189934 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.50857743 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.747478456 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3956952595 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3882789214 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.882938742 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1532686117 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4244203127 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4128687502 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2578698 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3944879236 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2986847187 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2963324114 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3291311205 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1214068661 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1431601450 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.335703563 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1264330730 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.110469651 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1112684978 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2816209036 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3083422666 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1402882526 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1087127480 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.208638463 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3630034950 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4232868875 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3092250994 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1547874286 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2735554823 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3398377636 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3189877553 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4175010336 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1378292781 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1637736118 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1448204711 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3655759397 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3638467201 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1405294331 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2164932261 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4023372574 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.173351865 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2214675666 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3681491350 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3899728506 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.500950212 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.858087807 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1276991433 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.151150089 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3477469937 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3808108855 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.707767236 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1629772811 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2210043354 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1995976264 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3512378206 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1249772270 |
| /workspace/coverage/default/0.sram_ctrl_bijection.4126021431 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.1107291212 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1024909768 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1107508728 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.4198459778 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.4201722691 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.589581196 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2355126112 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.2535767013 |
| /workspace/coverage/default/0.sram_ctrl_regwen.2095959699 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.2894688681 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2357433734 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1989038999 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.132414809 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.389549657 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.4026786472 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.4096130975 |
| /workspace/coverage/default/1.sram_ctrl_bijection.4145209616 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.2757415361 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3563515054 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2606438330 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.867710262 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.2433864741 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2087583729 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.649657931 |
| /workspace/coverage/default/1.sram_ctrl_regwen.502563183 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.2670340337 |
| /workspace/coverage/default/1.sram_ctrl_smoke.498695313 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.3349164088 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4135210334 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2095211555 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.426987414 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2688268373 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3257950253 |
| /workspace/coverage/default/10.sram_ctrl_bijection.1520105094 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3238010865 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2883286627 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.2649049744 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.231002100 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.3721963639 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.624539790 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.48993094 |
| /workspace/coverage/default/10.sram_ctrl_regwen.3372465545 |
| /workspace/coverage/default/10.sram_ctrl_smoke.1833768610 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.2072861077 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3439379410 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3418681981 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.845929753 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.96628690 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2500537861 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1599668056 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.3441590971 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3418913635 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.1163520050 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.784154731 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1110757823 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2944473120 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2478817216 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2963649156 |
| /workspace/coverage/default/11.sram_ctrl_smoke.223315321 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.681814239 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2500030887 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1887392561 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1052303152 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1012594208 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3601884502 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2702547331 |
| /workspace/coverage/default/12.sram_ctrl_executable.3608264857 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.2951978322 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.1727284726 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3646379991 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.3958384640 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.2771409725 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2313739838 |
| /workspace/coverage/default/12.sram_ctrl_regwen.2651598940 |
| /workspace/coverage/default/12.sram_ctrl_smoke.225380465 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3231723892 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.4243911940 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.899106938 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3316409272 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.2749002466 |
| /workspace/coverage/default/13.sram_ctrl_bijection.4273380945 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.419178972 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1492149935 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.903129357 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.1449559712 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1500038034 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.4144125253 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1044118157 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1088117973 |
| /workspace/coverage/default/13.sram_ctrl_regwen.155569583 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1366911487 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.4035865178 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.982698424 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3645771945 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1238612641 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.962045948 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.699959757 |
| /workspace/coverage/default/14.sram_ctrl_bijection.1254229662 |
| /workspace/coverage/default/14.sram_ctrl_executable.990301715 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1199240293 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2512135605 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3607149622 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.2101607253 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3102645705 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.1100509362 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1862598262 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.320920371 |
| /workspace/coverage/default/14.sram_ctrl_regwen.3346920521 |
| /workspace/coverage/default/14.sram_ctrl_smoke.1614617994 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1952238997 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3409177116 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.981300885 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.4261624543 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.1703188759 |
| /workspace/coverage/default/15.sram_ctrl_bijection.1430505540 |
| /workspace/coverage/default/15.sram_ctrl_executable.4151335431 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.2109694759 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.18590960 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1335605367 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.1818947329 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.3300238888 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.1785895067 |
| /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3709998032 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.2269273863 |
| /workspace/coverage/default/15.sram_ctrl_regwen.1739571289 |
| /workspace/coverage/default/15.sram_ctrl_smoke.4012455180 |
| /workspace/coverage/default/15.sram_ctrl_stress_all.2790134283 |
| /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1493361488 |
| /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1132805091 |
| /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4281535737 |
| /workspace/coverage/default/16.sram_ctrl_access_during_key_req.50703142 |
| /workspace/coverage/default/16.sram_ctrl_alert_test.595596685 |
| /workspace/coverage/default/16.sram_ctrl_bijection.2098177275 |
| /workspace/coverage/default/16.sram_ctrl_lc_escalation.4127559174 |
| /workspace/coverage/default/16.sram_ctrl_max_throughput.3842730837 |
| /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1866051424 |
| /workspace/coverage/default/16.sram_ctrl_mem_walk.178462828 |
| /workspace/coverage/default/16.sram_ctrl_multiple_keys.1040197215 |
| /workspace/coverage/default/16.sram_ctrl_partial_access.636866061 |
| /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3328426753 |
| /workspace/coverage/default/16.sram_ctrl_ram_cfg.3670359405 |
| /workspace/coverage/default/16.sram_ctrl_regwen.2471889344 |
| /workspace/coverage/default/16.sram_ctrl_smoke.3034452709 |
| /workspace/coverage/default/16.sram_ctrl_stress_all.2348597320 |
| /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1965234673 |
| /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3245713271 |
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| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.341580918 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2307891626 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.881335395 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1306592079 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.700059642 |
| /workspace/coverage/default/47.sram_ctrl_bijection.2147486755 |
| /workspace/coverage/default/47.sram_ctrl_executable.4131994546 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1651093237 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.404664994 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.709051291 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.1990041595 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.551346662 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.3700648440 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2462142296 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.4167593133 |
| /workspace/coverage/default/47.sram_ctrl_regwen.1710746824 |
| /workspace/coverage/default/47.sram_ctrl_smoke.1118840187 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.973616959 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1131825530 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3644487318 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3341047772 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2055332939 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.2616320171 |
| /workspace/coverage/default/48.sram_ctrl_bijection.2188265965 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.2798771673 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.2065220664 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1558811864 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.105301120 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.944749479 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.448368397 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4213894604 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2129211948 |
| /workspace/coverage/default/48.sram_ctrl_regwen.3597411328 |
| /workspace/coverage/default/48.sram_ctrl_smoke.1274834034 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3458846012 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2193961938 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3204251436 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2124686929 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.4086300400 |
| /workspace/coverage/default/49.sram_ctrl_bijection.390910643 |
| /workspace/coverage/default/49.sram_ctrl_executable.3387979246 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3838684342 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.3565748609 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4163412281 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.3295399180 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.3682994067 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3910988592 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.791062288 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1333187040 |
| /workspace/coverage/default/49.sram_ctrl_regwen.176220343 |
| /workspace/coverage/default/49.sram_ctrl_smoke.567897354 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3737687333 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.223225599 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1250377328 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2372953002 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.3049986707 |
| /workspace/coverage/default/5.sram_ctrl_bijection.247836782 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3467463693 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.731091439 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2268572161 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.2085836082 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.1181308675 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2244580980 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3224466496 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.2123067755 |
| /workspace/coverage/default/5.sram_ctrl_regwen.680810500 |
| /workspace/coverage/default/5.sram_ctrl_smoke.383087169 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.1332319465 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2893789733 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1989484628 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2506579362 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1788178515 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.1264741946 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1637066809 |
| /workspace/coverage/default/6.sram_ctrl_executable.4201693827 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.1665173589 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1667763567 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.3904334690 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.98004792 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.975036058 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1028683439 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.4011038592 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3048947036 |
| /workspace/coverage/default/6.sram_ctrl_smoke.2456016813 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3206671435 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3220632549 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2876159987 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3745287074 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.3806204058 |
| /workspace/coverage/default/7.sram_ctrl_bijection.4206356089 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.2315406292 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2557009038 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.57637764 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.616516270 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.2571084780 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.1036281338 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.246768146 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.3355568521 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3983563413 |
| /workspace/coverage/default/7.sram_ctrl_smoke.85321082 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2208636640 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3833437367 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3595797348 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2772763009 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1658768869 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3467428505 |
| /workspace/coverage/default/8.sram_ctrl_bijection.3927842348 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.1545698592 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.2331085205 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.928117266 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.717006171 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.3877924006 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.1432010288 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4184181035 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2079030451 |
| /workspace/coverage/default/8.sram_ctrl_regwen.3643487203 |
| /workspace/coverage/default/8.sram_ctrl_smoke.934933003 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1526296375 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2552904864 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1644343024 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3119021722 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.2163191409 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3299229715 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3844754505 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.4176035522 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4235669342 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3507062906 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.4071888574 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3224403190 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2972560513 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2546007779 |
| /workspace/coverage/default/9.sram_ctrl_regwen.613487509 |
| /workspace/coverage/default/9.sram_ctrl_smoke.18364564 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.509326016 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2404155596 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2615476367 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3751119008 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/49.sram_ctrl_smoke.567897354 |
|
|
Jan 21 12:50:21 PM PST 24 |
Jan 21 12:50:58 PM PST 24 |
3323923316 ps |
| T2 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3745287074 |
|
|
Jan 21 12:33:03 PM PST 24 |
Jan 21 12:39:39 PM PST 24 |
8935195413 ps |
| T3 |
/workspace/coverage/default/24.sram_ctrl_alert_test.438695744 |
|
|
Jan 21 12:39:00 PM PST 24 |
Jan 21 12:39:01 PM PST 24 |
38338657 ps |
| T4 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1157885457 |
|
|
Jan 21 12:44:46 PM PST 24 |
Jan 21 12:46:06 PM PST 24 |
9664265893 ps |
| T5 |
/workspace/coverage/default/47.sram_ctrl_executable.4131994546 |
|
|
Jan 21 12:49:47 PM PST 24 |
Jan 21 01:03:34 PM PST 24 |
30201071485 ps |
| T9 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.399277223 |
|
|
Jan 21 12:39:12 PM PST 24 |
Jan 21 12:49:04 PM PST 24 |
6094941056 ps |
| T10 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1040197215 |
|
|
Jan 21 12:35:23 PM PST 24 |
Jan 21 12:42:31 PM PST 24 |
17758712298 ps |
| T11 |
/workspace/coverage/default/18.sram_ctrl_smoke.3091277469 |
|
|
Jan 21 12:36:25 PM PST 24 |
Jan 21 12:36:49 PM PST 24 |
1190635943 ps |
| T12 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2953386073 |
|
|
Jan 21 01:03:27 PM PST 24 |
Jan 21 01:04:26 PM PST 24 |
1463159029 ps |
| T13 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.3375357723 |
|
|
Jan 21 01:16:34 PM PST 24 |
Jan 21 01:17:12 PM PST 24 |
4309907245 ps |
| T23 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2854406051 |
|
|
Jan 21 01:27:17 PM PST 24 |
Jan 21 01:27:18 PM PST 24 |
24858632 ps |
| T15 |
/workspace/coverage/default/12.sram_ctrl_bijection.2702547331 |
|
|
Jan 21 12:34:11 PM PST 24 |
Jan 21 01:02:45 PM PST 24 |
998372622965 ps |
| T16 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3645771945 |
|
|
Jan 21 01:13:03 PM PST 24 |
Jan 21 01:15:53 PM PST 24 |
2675722855 ps |
| T24 |
/workspace/coverage/default/26.sram_ctrl_alert_test.1778882881 |
|
|
Jan 21 12:39:48 PM PST 24 |
Jan 21 12:39:49 PM PST 24 |
22358772 ps |
| T103 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.18590960 |
|
|
Jan 21 12:35:18 PM PST 24 |
Jan 21 12:37:36 PM PST 24 |
3021238596 ps |
| T17 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.791062288 |
|
|
Jan 21 12:50:19 PM PST 24 |
Jan 21 12:59:40 PM PST 24 |
38922628772 ps |
| T14 |
/workspace/coverage/default/17.sram_ctrl_regwen.926118701 |
|
|
Jan 21 12:36:11 PM PST 24 |
Jan 21 12:37:25 PM PST 24 |
18336224907 ps |
| T104 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2887797609 |
|
|
Jan 21 01:49:59 PM PST 24 |
Jan 21 01:50:00 PM PST 24 |
12184691 ps |
| T64 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4029077139 |
|
|
Jan 21 01:37:29 PM PST 24 |
Jan 21 01:43:03 PM PST 24 |
20830842258 ps |
| T65 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1181308675 |
|
|
Jan 21 12:32:09 PM PST 24 |
Jan 21 12:45:26 PM PST 24 |
22495480118 ps |
| T18 |
/workspace/coverage/default/34.sram_ctrl_regwen.2355817821 |
|
|
Jan 21 12:43:00 PM PST 24 |
Jan 21 12:56:51 PM PST 24 |
3034917040 ps |
| T6 |
/workspace/coverage/default/41.sram_ctrl_stress_all.2738514586 |
|
|
Jan 21 12:47:03 PM PST 24 |
Jan 21 02:37:01 PM PST 24 |
202331653694 ps |
| T139 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2543016291 |
|
|
Jan 21 01:29:13 PM PST 24 |
Jan 21 01:30:35 PM PST 24 |
785426324 ps |
| T66 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3045822903 |
|
|
Jan 21 12:37:05 PM PST 24 |
Jan 21 12:39:24 PM PST 24 |
1569601905 ps |
| T8 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.820270718 |
|
|
Jan 21 12:32:04 PM PST 24 |
Jan 21 12:32:25 PM PST 24 |
577956328 ps |
| T35 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2568356253 |
|
|
Jan 21 12:39:58 PM PST 24 |
Jan 21 12:41:38 PM PST 24 |
828235000 ps |
| T22 |
/workspace/coverage/default/9.sram_ctrl_regwen.613487509 |
|
|
Jan 21 12:33:22 PM PST 24 |
Jan 21 12:56:08 PM PST 24 |
21293973275 ps |
| T7 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3838684342 |
|
|
Jan 21 12:50:35 PM PST 24 |
Jan 21 12:51:53 PM PST 24 |
32468476585 ps |
| T19 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.890591676 |
|
|
Jan 21 12:38:24 PM PST 24 |
Jan 21 12:49:38 PM PST 24 |
5148122876 ps |
| T36 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.2157205669 |
|
|
Jan 21 12:45:53 PM PST 24 |
Jan 21 12:46:50 PM PST 24 |
16898525324 ps |
| T27 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.392948670 |
|
|
Jan 21 12:41:05 PM PST 24 |
Jan 21 01:18:57 PM PST 24 |
541712137 ps |
| T37 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3176554984 |
|
|
Jan 21 12:45:15 PM PST 24 |
Jan 21 12:48:53 PM PST 24 |
2852291402 ps |
| T38 |
/workspace/coverage/default/16.sram_ctrl_bijection.2098177275 |
|
|
Jan 21 12:35:29 PM PST 24 |
Jan 21 12:56:00 PM PST 24 |
17390823454 ps |
| T39 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2207723951 |
|
|
Jan 21 01:11:13 PM PST 24 |
Jan 21 01:14:43 PM PST 24 |
3316491781 ps |
| T50 |
/workspace/coverage/default/40.sram_ctrl_regwen.3859541306 |
|
|
Jan 21 12:46:28 PM PST 24 |
Jan 21 01:02:56 PM PST 24 |
45749347485 ps |
| T51 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.169035782 |
|
|
Jan 21 12:42:49 PM PST 24 |
Jan 21 12:45:21 PM PST 24 |
3197344869 ps |
| T52 |
/workspace/coverage/default/42.sram_ctrl_regwen.3597088504 |
|
|
Jan 21 01:27:56 PM PST 24 |
Jan 21 01:44:49 PM PST 24 |
11291050956 ps |
| T53 |
/workspace/coverage/default/17.sram_ctrl_bijection.979663268 |
|
|
Jan 21 12:35:54 PM PST 24 |
Jan 21 01:09:13 PM PST 24 |
335229566805 ps |
| T54 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.355528221 |
|
|
Jan 21 12:32:03 PM PST 24 |
Jan 21 12:34:33 PM PST 24 |
49087707738 ps |
| T55 |
/workspace/coverage/default/19.sram_ctrl_partial_access.747269909 |
|
|
Jan 21 12:36:46 PM PST 24 |
Jan 21 12:37:07 PM PST 24 |
503102772 ps |
| T140 |
/workspace/coverage/default/35.sram_ctrl_smoke.3686563337 |
|
|
Jan 21 12:43:07 PM PST 24 |
Jan 21 12:43:31 PM PST 24 |
1350984086 ps |
| T109 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4253296691 |
|
|
Jan 21 12:38:46 PM PST 24 |
Jan 21 12:42:56 PM PST 24 |
105206518984 ps |
| T141 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1037791630 |
|
|
Jan 21 12:47:40 PM PST 24 |
Jan 21 12:50:15 PM PST 24 |
970480074 ps |
| T142 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.433195161 |
|
|
Jan 21 12:39:02 PM PST 24 |
Jan 21 12:40:26 PM PST 24 |
3111775290 ps |
| T143 |
/workspace/coverage/default/6.sram_ctrl_smoke.2456016813 |
|
|
Jan 21 12:32:23 PM PST 24 |
Jan 21 12:32:44 PM PST 24 |
781725468 ps |
| T78 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2644916955 |
|
|
Jan 21 12:44:11 PM PST 24 |
Jan 21 01:13:43 PM PST 24 |
50228285272 ps |
| T28 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3356889565 |
|
|
Jan 21 01:21:28 PM PST 24 |
Jan 21 03:22:02 PM PST 24 |
7533196231 ps |
| T144 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2989671867 |
|
|
Jan 21 12:44:34 PM PST 24 |
Jan 21 12:50:39 PM PST 24 |
5292175679 ps |
| T135 |
/workspace/coverage/default/20.sram_ctrl_executable.3774342440 |
|
|
Jan 21 12:49:24 PM PST 24 |
Jan 21 01:03:23 PM PST 24 |
48115283233 ps |
| T57 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3287907089 |
|
|
Jan 21 01:32:11 PM PST 24 |
Jan 21 01:32:13 PM PST 24 |
52171502 ps |
| T58 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1112684978 |
|
|
Jan 21 12:52:54 PM PST 24 |
Jan 21 12:52:56 PM PST 24 |
16030659 ps |
| T114 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2183339557 |
|
|
Jan 21 12:54:50 PM PST 24 |
Jan 21 12:54:52 PM PST 24 |
19975675 ps |
| T29 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1252102961 |
|
|
Jan 21 12:22:42 PM PST 24 |
Jan 21 12:22:49 PM PST 24 |
366432938 ps |
| T40 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2947122682 |
|
|
Jan 21 12:50:24 PM PST 24 |
Jan 21 12:50:26 PM PST 24 |
699781479 ps |
| T41 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.747478456 |
|
|
Jan 21 12:22:41 PM PST 24 |
Jan 21 12:22:47 PM PST 24 |
565129139 ps |
| T42 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3004743494 |
|
|
Jan 21 01:09:36 PM PST 24 |
Jan 21 01:09:39 PM PST 24 |
507877609 ps |
| T105 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.151150089 |
|
|
Jan 21 01:40:25 PM PST 24 |
Jan 21 01:40:27 PM PST 24 |
18125913 ps |
| T43 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.208638463 |
|
|
Jan 21 12:25:01 PM PST 24 |
Jan 21 12:25:04 PM PST 24 |
93253075 ps |
| T44 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4244203127 |
|
|
Jan 21 01:03:51 PM PST 24 |
Jan 21 01:03:56 PM PST 24 |
589451203 ps |
| T59 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1276991433 |
|
|
Jan 21 01:04:38 PM PST 24 |
Jan 21 01:04:39 PM PST 24 |
14557470 ps |
| T115 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2502839551 |
|
|
Jan 21 12:24:35 PM PST 24 |
Jan 21 12:24:37 PM PST 24 |
50193854 ps |
| T106 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3947633244 |
|
|
Jan 21 01:04:03 PM PST 24 |
Jan 21 01:04:05 PM PST 24 |
27043395 ps |
| T45 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.688629019 |
|
|
Jan 21 12:46:18 PM PST 24 |
Jan 21 12:46:22 PM PST 24 |
63348115 ps |
| T56 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.707767236 |
|
|
Jan 21 12:25:00 PM PST 24 |
Jan 21 12:25:06 PM PST 24 |
1404458224 ps |
| T107 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.156189934 |
|
|
Jan 21 12:20:28 PM PST 24 |
Jan 21 12:20:29 PM PST 24 |
13046093 ps |
| T46 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.902233005 |
|
|
Jan 21 12:34:06 PM PST 24 |
Jan 21 12:34:19 PM PST 24 |
966192445 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1214068661 |
|
|
Jan 21 12:56:14 PM PST 24 |
Jan 21 12:56:20 PM PST 24 |
42704396 ps |
| T60 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3057880846 |
|
|
Jan 21 01:08:51 PM PST 24 |
Jan 21 01:08:52 PM PST 24 |
13572547 ps |
| T47 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3512378206 |
|
|
Jan 21 12:22:09 PM PST 24 |
Jan 21 12:22:14 PM PST 24 |
238100337 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3709366448 |
|
|
Jan 21 12:44:59 PM PST 24 |
Jan 21 12:45:01 PM PST 24 |
15574575 ps |
| T48 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1087127480 |
|
|
Jan 21 01:11:42 PM PST 24 |
Jan 21 01:11:46 PM PST 24 |
74588356 ps |
| T62 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1093099527 |
|
|
Jan 21 01:15:54 PM PST 24 |
Jan 21 01:15:56 PM PST 24 |
41870643 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3638467201 |
|
|
Jan 21 12:21:25 PM PST 24 |
Jan 21 12:21:27 PM PST 24 |
19077907 ps |
| T49 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3283233154 |
|
|
Jan 21 01:02:18 PM PST 24 |
Jan 21 01:02:27 PM PST 24 |
294762579 ps |
| T117 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3189877553 |
|
|
Jan 21 12:25:01 PM PST 24 |
Jan 21 12:25:05 PM PST 24 |
114491519 ps |
| T138 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2816209036 |
|
|
Jan 21 12:24:40 PM PST 24 |
Jan 21 12:24:54 PM PST 24 |
725047657 ps |
| T118 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.875066232 |
|
|
Jan 21 12:37:18 PM PST 24 |
Jan 21 12:37:21 PM PST 24 |
70512136 ps |
| T127 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.500950212 |
|
|
Jan 21 12:20:01 PM PST 24 |
Jan 21 12:20:03 PM PST 24 |
154186905 ps |
| T145 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.413363314 |
|
|
Jan 21 12:24:10 PM PST 24 |
Jan 21 12:24:12 PM PST 24 |
15291654 ps |
| T146 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.769863691 |
|
|
Jan 21 12:22:09 PM PST 24 |
Jan 21 12:22:19 PM PST 24 |
2316918455 ps |
| T122 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3956952595 |
|
|
Jan 21 12:24:18 PM PST 24 |
Jan 21 12:24:21 PM PST 24 |
196058934 ps |
| T123 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3808108855 |
|
|
Jan 21 12:21:05 PM PST 24 |
Jan 21 12:21:10 PM PST 24 |
186143438 ps |
| T147 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1378292781 |
|
|
Jan 21 12:44:33 PM PST 24 |
Jan 21 12:44:34 PM PST 24 |
48956204 ps |
| T124 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1138917404 |
|
|
Jan 21 12:24:36 PM PST 24 |
Jan 21 12:24:39 PM PST 24 |
376483862 ps |
| T148 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2554981315 |
|
|
Jan 21 01:00:28 PM PST 24 |
Jan 21 01:00:35 PM PST 24 |
1441444086 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.615025683 |
|
|
Jan 21 12:24:35 PM PST 24 |
Jan 21 12:24:37 PM PST 24 |
13267976 ps |
| T149 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2898211785 |
|
|
Jan 21 12:58:06 PM PST 24 |
Jan 21 12:58:09 PM PST 24 |
135206991 ps |
| T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3681491350 |
|
|
Jan 21 12:22:25 PM PST 24 |
Jan 21 12:22:26 PM PST 24 |
15477239 ps |
| T150 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2075963877 |
|
|
Jan 21 12:25:00 PM PST 24 |
Jan 21 12:25:03 PM PST 24 |
38784256 ps |
| T119 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4023372574 |
|
|
Jan 21 12:24:49 PM PST 24 |
Jan 21 12:24:53 PM PST 24 |
2026685538 ps |
| T111 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1405294331 |
|
|
Jan 21 01:00:30 PM PST 24 |
Jan 21 01:00:32 PM PST 24 |
53604278 ps |
| T120 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4128687502 |
|
|
Jan 21 01:47:37 PM PST 24 |
Jan 21 01:47:40 PM PST 24 |
109859994 ps |
| T151 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1366223626 |
|
|
Jan 21 12:24:35 PM PST 24 |
Jan 21 12:24:49 PM PST 24 |
688707225 ps |
| T152 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3882789214 |
|
|
Jan 21 12:20:55 PM PST 24 |
Jan 21 12:21:09 PM PST 24 |
1815304224 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2759739309 |
|
|
Jan 21 12:29:38 PM PST 24 |
Jan 21 12:29:47 PM PST 24 |
288077022 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1160271604 |
|
|
Jan 21 12:24:49 PM PST 24 |
Jan 21 12:24:51 PM PST 24 |
21321986 ps |
| T112 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.971937744 |
|
|
Jan 21 12:47:09 PM PST 24 |
Jan 21 12:47:10 PM PST 24 |
24808360 ps |
| T153 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3854201641 |
|
|
Jan 21 12:24:20 PM PST 24 |
Jan 21 12:24:26 PM PST 24 |
351489148 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1547874286 |
|
|
Jan 21 12:41:15 PM PST 24 |
Jan 21 12:41:16 PM PST 24 |
13808942 ps |
| T70 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.882938742 |
|
|
Jan 21 12:58:03 PM PST 24 |
Jan 21 12:58:04 PM PST 24 |
19188829 ps |
| T154 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1448204711 |
|
|
Jan 21 12:56:24 PM PST 24 |
Jan 21 12:56:30 PM PST 24 |
128605609 ps |
| T155 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.173351865 |
|
|
Jan 21 12:24:45 PM PST 24 |
Jan 21 12:24:52 PM PST 24 |
1434827158 ps |
| T156 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1683244336 |
|
|
Jan 21 12:56:59 PM PST 24 |
Jan 21 12:57:06 PM PST 24 |
24166300 ps |
| T130 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1182100971 |
|
|
Jan 21 01:30:11 PM PST 24 |
Jan 21 01:30:15 PM PST 24 |
176515186 ps |
| T71 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1324258261 |
|
|
Jan 21 12:22:42 PM PST 24 |
Jan 21 12:22:44 PM PST 24 |
15023434 ps |
| T73 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3092250994 |
|
|
Jan 21 12:51:48 PM PST 24 |
Jan 21 12:51:58 PM PST 24 |
694469451 ps |
| T72 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3266983508 |
|
|
Jan 21 12:24:35 PM PST 24 |
Jan 21 12:24:37 PM PST 24 |
19343631 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2812647054 |
|
|
Jan 21 12:24:49 PM PST 24 |
Jan 21 12:24:56 PM PST 24 |
713694832 ps |
| T75 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.730676658 |
|
|
Jan 21 01:02:15 PM PST 24 |
Jan 21 01:02:19 PM PST 24 |
470329913 ps |
| T76 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2712355801 |
|
|
Jan 21 12:21:10 PM PST 24 |
Jan 21 12:21:18 PM PST 24 |
14460815 ps |
| T77 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.499516544 |
|
|
Jan 21 12:33:48 PM PST 24 |
Jan 21 12:33:51 PM PST 24 |
120772179 ps |
| T99 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1104537007 |
|
|
Jan 21 12:22:20 PM PST 24 |
Jan 21 12:22:22 PM PST 24 |
63883034 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1402882526 |
|
|
Jan 21 12:24:35 PM PST 24 |
Jan 21 12:24:37 PM PST 24 |
58927567 ps |
| T157 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3655759397 |
|
|
Jan 21 12:24:49 PM PST 24 |
Jan 21 12:25:01 PM PST 24 |
356160642 ps |
| T158 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1813753150 |
|
|
Jan 21 12:38:49 PM PST 24 |
Jan 21 12:38:50 PM PST 24 |
25681294 ps |
| T159 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3542892962 |
|
|
Jan 21 12:26:04 PM PST 24 |
Jan 21 12:26:09 PM PST 24 |
113629549 ps |
| T126 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3022895254 |
|
|
Jan 21 12:28:50 PM PST 24 |
Jan 21 12:28:52 PM PST 24 |
333144292 ps |
| T160 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4232868875 |
|
|
Jan 21 01:04:15 PM PST 24 |
Jan 21 01:04:16 PM PST 24 |
24005295 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1980806914 |
|
|
Jan 21 12:24:53 PM PST 24 |
Jan 21 12:24:58 PM PST 24 |
604471714 ps |
| T161 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2986847187 |
|
|
Jan 21 12:56:57 PM PST 24 |
Jan 21 12:57:00 PM PST 24 |
18768955 ps |
| T162 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3477469937 |
|
|
Jan 21 12:31:11 PM PST 24 |
Jan 21 12:31:14 PM PST 24 |
34966748 ps |
| T163 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4175010336 |
|
|
Jan 21 12:46:50 PM PST 24 |
Jan 21 12:46:56 PM PST 24 |
3424510516 ps |
| T164 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.858768291 |
|
|
Jan 21 12:46:43 PM PST 24 |
Jan 21 12:46:44 PM PST 24 |
13122881 ps |
| T165 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1532686117 |
|
|
Jan 21 12:21:00 PM PST 24 |
Jan 21 12:21:03 PM PST 24 |
26359048 ps |
| T91 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3938103109 |
|
|
Jan 21 12:24:35 PM PST 24 |
Jan 21 12:24:38 PM PST 24 |
102598952 ps |
| T92 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1434883396 |
|
|
Jan 21 12:22:04 PM PST 24 |
Jan 21 12:22:18 PM PST 24 |
1426570473 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1431601450 |
|
|
Jan 21 12:24:35 PM PST 24 |
Jan 21 12:24:41 PM PST 24 |
302723615 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.335703563 |
|
|
Jan 21 12:48:07 PM PST 24 |
Jan 21 12:48:14 PM PST 24 |
220543236 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2680105016 |
|
|
Jan 21 12:24:53 PM PST 24 |
Jan 21 12:24:56 PM PST 24 |
46866566 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1848394067 |
|
|
Jan 21 12:22:25 PM PST 24 |
Jan 21 12:22:30 PM PST 24 |
614414698 ps |
| T96 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1637736118 |
|
|
Jan 21 12:55:45 PM PST 24 |
Jan 21 12:55:47 PM PST 24 |
36912488 ps |
| T97 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2210043354 |
|
|
Jan 21 12:24:19 PM PST 24 |
Jan 21 12:24:21 PM PST 24 |
99738414 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2963324114 |
|
|
Jan 21 01:16:39 PM PST 24 |
Jan 21 01:16:44 PM PST 24 |
370946842 ps |
| T101 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3373121917 |
|
|
Jan 21 12:24:53 PM PST 24 |
Jan 21 12:25:02 PM PST 24 |
6862803189 ps |
| T102 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3333810670 |
|
|
Jan 21 12:40:52 PM PST 24 |
Jan 21 12:40:55 PM PST 24 |
487631313 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2578698 |
|
|
Jan 21 12:24:34 PM PST 24 |
Jan 21 12:24:36 PM PST 24 |
95777756 ps |
| T166 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3398377636 |
|
|
Jan 21 12:24:24 PM PST 24 |
Jan 21 12:24:31 PM PST 24 |
138778869 ps |
| T167 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2164932261 |
|
|
Jan 21 12:24:26 PM PST 24 |
Jan 21 12:24:30 PM PST 24 |
105365564 ps |
| T168 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2256622146 |
|
|
Jan 21 12:33:37 PM PST 24 |
Jan 21 12:33:38 PM PST 24 |
16313701 ps |
| T169 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3630034950 |
|
|
Jan 21 12:24:49 PM PST 24 |
Jan 21 12:24:51 PM PST 24 |
17121591 ps |
| T170 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1554007047 |
|
|
Jan 21 12:24:45 PM PST 24 |
Jan 21 12:24:52 PM PST 24 |
704373418 ps |
| T171 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3740717414 |
|
|
Jan 21 12:22:25 PM PST 24 |
Jan 21 12:22:27 PM PST 24 |
120843744 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1389808067 |
|
|
Jan 21 01:10:27 PM PST 24 |
Jan 21 01:10:34 PM PST 24 |
24601738 ps |
| T172 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2214675666 |
|
|
Jan 21 12:43:00 PM PST 24 |
Jan 21 12:43:02 PM PST 24 |
28893038 ps |
| T128 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.609099651 |
|
|
Jan 21 12:33:01 PM PST 24 |
Jan 21 12:33:03 PM PST 24 |
133040478 ps |
| T173 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2749140350 |
|
|
Jan 21 12:37:44 PM PST 24 |
Jan 21 12:37:45 PM PST 24 |
28724305 ps |
| T174 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3083422666 |
|
|
Jan 21 12:25:01 PM PST 24 |
Jan 21 12:25:04 PM PST 24 |
15121559 ps |
| T175 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2735554823 |
|
|
Jan 21 12:57:59 PM PST 24 |
Jan 21 12:58:01 PM PST 24 |
44834489 ps |
| T176 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1264330730 |
|
|
Jan 21 01:42:10 PM PST 24 |
Jan 21 01:42:12 PM PST 24 |
47194210 ps |
| T177 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1872153177 |
|
|
Jan 21 12:49:36 PM PST 24 |
Jan 21 12:49:41 PM PST 24 |
146880235 ps |
| T178 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1995976264 |
|
|
Jan 21 12:49:54 PM PST 24 |
Jan 21 12:49:58 PM PST 24 |
153231214 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.557198387 |
|
|
Jan 21 12:54:54 PM PST 24 |
Jan 21 12:54:58 PM PST 24 |
1068747306 ps |
| T179 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.110469651 |
|
|
Jan 21 12:24:40 PM PST 24 |
Jan 21 12:24:43 PM PST 24 |
48012692 ps |
| T180 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.988167090 |
|
|
Jan 21 01:25:18 PM PST 24 |
Jan 21 01:25:19 PM PST 24 |
36251336 ps |
| T181 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3944879236 |
|
|
Jan 21 12:24:10 PM PST 24 |
Jan 21 12:24:12 PM PST 24 |
90935193 ps |
| T82 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2706760841 |
|
|
Jan 21 12:24:51 PM PST 24 |
Jan 21 12:24:54 PM PST 24 |
21487493 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1629772811 |
|
|
Jan 21 12:23:01 PM PST 24 |
Jan 21 12:23:02 PM PST 24 |
11709037 ps |
| T182 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3899728506 |
|
|
Jan 21 12:24:49 PM PST 24 |
Jan 21 12:24:53 PM PST 24 |
136414350 ps |
| T183 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.858087807 |
|
|
Jan 21 01:20:38 PM PST 24 |
Jan 21 01:20:46 PM PST 24 |
1513601629 ps |
| T184 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3683000596 |
|
|
Jan 21 12:22:02 PM PST 24 |
Jan 21 12:22:04 PM PST 24 |
32154578 ps |
| T185 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.50857743 |
|
|
Jan 21 12:20:28 PM PST 24 |
Jan 21 12:20:29 PM PST 24 |
25239711 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3291311205 |
|
|
Jan 21 12:49:31 PM PST 24 |
Jan 21 12:49:33 PM PST 24 |
39848533 ps |
| T186 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2066786160 |
|
|
Jan 21 01:14:26 PM PST 24 |
Jan 21 01:14:39 PM PST 24 |
558287863 ps |
| T187 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1254511536 |
|
|
Jan 21 12:57:58 PM PST 24 |
Jan 21 12:58:00 PM PST 24 |
16892758 ps |
| T84 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.57637764 |
|
|
Jan 21 12:33:09 PM PST 24 |
Jan 21 12:34:18 PM PST 24 |
1013739118 ps |
| T188 |
/workspace/coverage/default/28.sram_ctrl_bijection.1370456097 |
|
|
Jan 21 12:40:16 PM PST 24 |
Jan 21 12:59:31 PM PST 24 |
17410506606 ps |
| T85 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2578139179 |
|
|
Jan 21 12:47:42 PM PST 24 |
Jan 21 12:53:58 PM PST 24 |
1945374748 ps |
| T113 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1534779812 |
|
|
Jan 21 12:36:10 PM PST 24 |
Jan 21 12:44:10 PM PST 24 |
89508637934 ps |
| T131 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1077282334 |
|
|
Jan 21 02:05:11 PM PST 24 |
Jan 21 03:15:30 PM PST 24 |
104595846512 ps |
| T137 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3844754505 |
|
|
Jan 21 12:33:23 PM PST 24 |
Jan 21 12:35:40 PM PST 24 |
5266975333 ps |
| T189 |
/workspace/coverage/default/24.sram_ctrl_partial_access.765997992 |
|
|
Jan 21 12:38:47 PM PST 24 |
Jan 21 12:40:39 PM PST 24 |
497431398 ps |
| T190 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2951344111 |
|
|
Jan 21 12:49:16 PM PST 24 |
Jan 21 01:00:21 PM PST 24 |
10965238044 ps |
| T191 |
/workspace/coverage/default/36.sram_ctrl_executable.2830936241 |
|
|
Jan 21 12:44:06 PM PST 24 |
Jan 21 01:09:53 PM PST 24 |
18220164398 ps |
| T192 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1712676455 |
|
|
Jan 21 12:33:44 PM PST 24 |
Jan 21 12:35:58 PM PST 24 |
23954629680 ps |
| T193 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1779158445 |
|
|
Jan 21 03:01:27 PM PST 24 |
Jan 21 03:02:12 PM PST 24 |
3821758916 ps |
| T194 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3948513447 |
|
|
Jan 21 12:43:34 PM PST 24 |
Jan 21 12:46:05 PM PST 24 |
62261898170 ps |
| T195 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3489779131 |
|
|
Jan 21 12:47:40 PM PST 24 |
Jan 21 12:49:15 PM PST 24 |
806813111 ps |
| T196 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2005810370 |
|
|
Jan 21 12:32:14 PM PST 24 |
Jan 21 12:43:39 PM PST 24 |
9763239905 ps |
| T197 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1026453565 |
|
|
Jan 21 01:13:11 PM PST 24 |
Jan 21 01:13:38 PM PST 24 |
2791909094 ps |
| T198 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1305826499 |
|
|
Jan 21 12:46:18 PM PST 24 |
Jan 21 12:48:47 PM PST 24 |
38204835399 ps |
| T132 |
/workspace/coverage/default/28.sram_ctrl_executable.1786703375 |
|
|
Jan 21 12:40:25 PM PST 24 |
Jan 21 12:58:20 PM PST 24 |
14538316152 ps |
| T30 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2589285695 |
|
|
Jan 21 12:34:20 PM PST 24 |
Jan 21 12:34:26 PM PST 24 |
344125672 ps |
| T199 |
/workspace/coverage/default/40.sram_ctrl_smoke.3475217416 |
|
|
Jan 21 12:46:18 PM PST 24 |
Jan 21 12:48:45 PM PST 24 |
1616675965 ps |
| T200 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.551346662 |
|
|
Jan 21 12:49:33 PM PST 24 |
Jan 21 01:10:51 PM PST 24 |
18249079037 ps |
| T201 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3049986707 |
|
|
Jan 21 12:32:25 PM PST 24 |
Jan 21 12:32:30 PM PST 24 |
14839194 ps |
| T86 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2526778671 |
|
|
Jan 21 12:37:34 PM PST 24 |
Jan 21 12:38:43 PM PST 24 |
980061903 ps |
| T202 |
/workspace/coverage/default/14.sram_ctrl_regwen.3346920521 |
|
|
Jan 21 01:03:49 PM PST 24 |
Jan 21 01:17:46 PM PST 24 |
19411890576 ps |
| T25 |
/workspace/coverage/default/47.sram_ctrl_stress_all.973616959 |
|
|
Jan 21 12:49:59 PM PST 24 |
Jan 21 01:41:18 PM PST 24 |
997650418337 ps |
| T203 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1055101785 |
|
|
Jan 21 12:35:48 PM PST 24 |
Jan 21 01:01:39 PM PST 24 |
100350566990 ps |
| T204 |
/workspace/coverage/default/25.sram_ctrl_regwen.2728146149 |
|
|
Jan 21 12:39:19 PM PST 24 |
Jan 21 12:54:48 PM PST 24 |
17482655083 ps |
| T136 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.305478131 |
|
|
Jan 21 12:40:40 PM PST 24 |
Jan 21 12:44:41 PM PST 24 |
39835462284 ps |
| T205 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1547946827 |
|
|
Jan 21 12:47:03 PM PST 24 |
Jan 21 12:51:05 PM PST 24 |
21877843671 ps |
| T206 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.944749479 |
|
|
Jan 21 12:49:55 PM PST 24 |
Jan 21 01:06:17 PM PST 24 |
15324386753 ps |
| T207 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.246768146 |
|
|
Jan 21 12:32:56 PM PST 24 |
Jan 21 12:39:27 PM PST 24 |
63505970704 ps |
| T208 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2616320171 |
|
|
Jan 21 02:06:36 PM PST 24 |
Jan 21 02:06:37 PM PST 24 |
14246090 ps |
| T116 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1256858875 |
|
|
Jan 21 12:47:55 PM PST 24 |
Jan 21 12:55:16 PM PST 24 |
607727398 ps |
| T209 |
/workspace/coverage/default/36.sram_ctrl_partial_access.911800110 |
|
|
Jan 21 12:43:50 PM PST 24 |
Jan 21 12:45:35 PM PST 24 |
1697934606 ps |
| T210 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1711806499 |
|
|
Jan 21 12:41:26 PM PST 24 |
Jan 21 12:42:02 PM PST 24 |
730350079 ps |
| T211 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3328426753 |
|
|
Jan 21 12:35:31 PM PST 24 |
Jan 21 12:42:06 PM PST 24 |
20014339639 ps |
| T212 |
/workspace/coverage/default/38.sram_ctrl_smoke.84851757 |
|
|
Jan 21 01:42:04 PM PST 24 |
Jan 21 01:42:26 PM PST 24 |
2970828144 ps |
| T213 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2460583496 |
|
|
Jan 21 02:35:38 PM PST 24 |
Jan 21 02:41:56 PM PST 24 |
11948835771 ps |
| T214 |
/workspace/coverage/default/4.sram_ctrl_bijection.635666650 |
|
|
Jan 21 12:32:06 PM PST 24 |
Jan 21 12:50:54 PM PST 24 |
50836841902 ps |
| T215 |
/workspace/coverage/default/8.sram_ctrl_regwen.3643487203 |
|
|
Jan 21 12:33:14 PM PST 24 |
Jan 21 12:53:58 PM PST 24 |
58131767414 ps |
| T87 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3726837946 |
|
|
Jan 21 12:48:39 PM PST 24 |
Jan 21 12:49:57 PM PST 24 |
2722776996 ps |
| T216 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1608033082 |
|
|
Jan 21 12:36:32 PM PST 24 |
Jan 21 12:37:05 PM PST 24 |
1459749250 ps |
| T217 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3418681981 |
|
|
Jan 21 12:33:28 PM PST 24 |
Jan 21 12:37:07 PM PST 24 |
3129894431 ps |
| T218 |
/workspace/coverage/default/44.sram_ctrl_regwen.3960534942 |
|
|
Jan 21 12:48:30 PM PST 24 |
Jan 21 01:02:53 PM PST 24 |
10620165682 ps |
| T31 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2546007779 |
|
|
Jan 21 12:33:26 PM PST 24 |
Jan 21 12:33:40 PM PST 24 |
697644721 ps |
| T219 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.4096579358 |
|
|
Jan 21 12:40:15 PM PST 24 |
Jan 21 12:43:41 PM PST 24 |
2585413474 ps |
| T220 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.551703075 |
|
|
Jan 21 12:43:33 PM PST 24 |
Jan 21 12:46:11 PM PST 24 |
801690140 ps |
| T221 |
/workspace/coverage/default/31.sram_ctrl_smoke.3853001231 |
|
|
Jan 21 12:41:19 PM PST 24 |
Jan 21 12:41:46 PM PST 24 |
3420524745 ps |
| T133 |
/workspace/coverage/default/21.sram_ctrl_regwen.4163990564 |
|
|
Jan 21 12:37:45 PM PST 24 |
Jan 21 12:56:12 PM PST 24 |
23344437601 ps |
| T222 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3833437367 |
|
|
Jan 21 12:33:08 PM PST 24 |
Jan 21 12:56:04 PM PST 24 |
1156541213 ps |
| T223 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1371265606 |
|
|
Jan 21 02:22:38 PM PST 24 |
Jan 21 03:44:00 PM PST 24 |
236930917680 ps |
| T224 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3682994067 |
|
|
Jan 21 01:44:21 PM PST 24 |
Jan 21 02:05:16 PM PST 24 |
50977648279 ps |
| T225 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3644487318 |
|
|
Jan 21 01:41:22 PM PST 24 |
Jan 21 01:46:42 PM PST 24 |
20864808789 ps |
| T226 |
/workspace/coverage/default/9.sram_ctrl_bijection.3299229715 |
|
|
Jan 21 12:33:28 PM PST 24 |
Jan 21 01:15:13 PM PST 24 |
116229595411 ps |
| T227 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3349164088 |
|
|
Jan 21 12:32:03 PM PST 24 |
Jan 21 01:21:13 PM PST 24 |
87241785896 ps |
| T228 |
/workspace/coverage/default/20.sram_ctrl_regwen.3771289606 |
|
|
Jan 21 12:37:29 PM PST 24 |
Jan 21 12:52:30 PM PST 24 |
3686156700 ps |
| T229 |
/workspace/coverage/default/17.sram_ctrl_executable.3755033789 |
|
|
Jan 21 12:36:10 PM PST 24 |
Jan 21 12:39:34 PM PST 24 |
3675782435 ps |
| T230 |
/workspace/coverage/default/1.sram_ctrl_regwen.502563183 |
|
|
Jan 21 12:32:05 PM PST 24 |
Jan 21 12:52:09 PM PST 24 |
6138856866 ps |
| T231 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1869291396 |
|
|
Jan 21 12:32:04 PM PST 24 |
Jan 21 12:32:24 PM PST 24 |
31751499 ps |
| T232 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1036281338 |
|
|
Jan 21 12:32:54 PM PST 24 |
Jan 21 12:33:20 PM PST 24 |
538674732 ps |
| T233 |
/workspace/coverage/default/26.sram_ctrl_smoke.32131357 |
|
|
Jan 21 01:25:30 PM PST 24 |
Jan 21 01:27:07 PM PST 24 |
451964240 ps |
| T234 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3656290421 |
|
|
Jan 21 12:46:20 PM PST 24 |
Jan 21 12:48:52 PM PST 24 |
1652604015 ps |
| T235 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2749002466 |
|
|
Jan 21 12:34:51 PM PST 24 |
Jan 21 12:34:54 PM PST 24 |
32655209 ps |
| T236 |
/workspace/coverage/default/39.sram_ctrl_smoke.2816050345 |
|
|
Jan 21 12:46:45 PM PST 24 |
Jan 21 12:47:09 PM PST 24 |
1264166628 ps |
| T237 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.260855096 |
|
|
Jan 21 12:39:36 PM PST 24 |
Jan 21 12:44:39 PM PST 24 |
32119490100 ps |
| T32 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4011038592 |
|
|
Jan 21 12:32:37 PM PST 24 |
Jan 21 12:32:52 PM PST 24 |
362895747 ps |
| T238 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3909414510 |
|
|
Jan 21 12:39:11 PM PST 24 |
Jan 21 12:40:01 PM PST 24 |
1515858132 ps |
| T239 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1983636470 |
|
|
Jan 21 12:38:07 PM PST 24 |
Jan 21 12:43:08 PM PST 24 |
57278168535 ps |
| T240 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.4287976351 |
|
|
Jan 21 12:47:42 PM PST 24 |
Jan 21 12:49:26 PM PST 24 |
123882432069 ps |
| T88 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3563515054 |
|
|
Jan 21 12:32:04 PM PST 24 |
Jan 21 12:34:55 PM PST 24 |
17490135754 ps |
| T241 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.505179192 |
|
|
Jan 21 01:41:24 PM PST 24 |
Jan 21 02:55:16 PM PST 24 |
246522236 ps |
| T242 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2606438330 |
|
|
Jan 21 12:32:05 PM PST 24 |
Jan 21 12:37:04 PM PST 24 |
13794139926 ps |
| T243 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2140553528 |
|
|
Jan 21 12:43:40 PM PST 24 |
Jan 21 01:40:40 PM PST 24 |
1442065606 ps |
| T244 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.379628411 |
|
|
Jan 21 12:46:14 PM PST 24 |
Jan 21 12:49:17 PM PST 24 |
8886542543 ps |
| T245 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3256201531 |
|
|
Jan 21 12:42:40 PM PST 24 |
Jan 21 12:46:46 PM PST 24 |
4023439519 ps |
| T246 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.98004792 |
|
|
Jan 21 12:32:25 PM PST 24 |
Jan 21 12:55:55 PM PST 24 |
69410963864 ps |
| T247 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4184181035 |
|
|
Jan 21 12:33:10 PM PST 24 |
Jan 21 12:37:53 PM PST 24 |
4356844987 ps |
| T248 |
/workspace/coverage/default/13.sram_ctrl_regwen.155569583 |
|
|
Jan 21 12:34:43 PM PST 24 |
Jan 21 12:45:04 PM PST 24 |
27113681696 ps |
| T26 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3719170401 |
|
|
Jan 21 12:53:48 PM PST 24 |
Jan 21 12:58:11 PM PST 24 |
41079423584 ps |
| T249 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2375565123 |
|
|
Jan 21 12:38:52 PM PST 24 |
Jan 21 12:56:17 PM PST 24 |
5246171943 ps |
| T250 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.3718009776 |
|
|
Jan 21 12:43:40 PM PST 24 |
Jan 21 12:46:14 PM PST 24 |
49188672414 ps |
| T134 |
/workspace/coverage/default/28.sram_ctrl_regwen.471905434 |
|
|
Jan 21 12:40:25 PM PST 24 |
Jan 21 12:59:45 PM PST 24 |
3755933703 ps |
| T251 |
/workspace/coverage/default/38.sram_ctrl_bijection.2361216478 |
|
|
Jan 21 12:45:07 PM PST 24 |
Jan 21 01:04:35 PM PST 24 |
274680689469 ps |
| T252 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1808695553 |
|
|
Jan 21 12:40:41 PM PST 24 |
Jan 21 12:43:14 PM PST 24 |
3078967679 ps |
| T253 |
/workspace/coverage/default/36.sram_ctrl_bijection.3404754759 |
|
|
Jan 21 12:43:49 PM PST 24 |
Jan 21 12:58:05 PM PST 24 |
49533506462 ps |
| T254 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2276963685 |
|
|
Jan 21 12:45:54 PM PST 24 |
Jan 21 12:46:09 PM PST 24 |
360897041 ps |
| T255 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.738415112 |
|
|
Jan 21 12:40:16 PM PST 24 |
Jan 21 12:52:58 PM PST 24 |
60506841207 ps |