Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	117090970	1			T1	2894		T2	72481		T4	134
triple_byte_access	2583017	1			T1	48		T2	1494		T5	1577
halfword_access	3969012	1			T1	80		T2	2176		T4	3
byte_access	5562414	1			T1	94		T2	2889		T4	2
zero_access	1696672	1			T1	23		T2	689		T4	3

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64813622

1

T1

1582

T2

39686

T4

74

auto[1]

66088463

1

T1

1557

T2

40043

T4

68

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	57804499	1			T1	1471		T2	36028		T4	70
auto[0]	triple_byte_access	1222517	1			T1	16		T2	728		T5	979
auto[0]	halfword_access	1927678	1			T1	33		T2	1131		T4	2
auto[0]	byte_access	2841828	1			T1	50		T2	1459		T4	1
auto[0]	zero_access	1017100	1			T1	12		T2	340		T4	1
auto[1]	word_access	59286471	1			T1	1423		T2	36453		T4	64
auto[1]	triple_byte_access	1360500	1			T1	32		T2	766		T5	598
auto[1]	halfword_access	2041334	1			T1	47		T2	1045		T4	1
auto[1]	byte_access	2720586	1			T1	44		T2	1430		T4	1
auto[1]	zero_access	679572	1			T1	11		T2	349		T4	2