4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | sram_ctrl_mem_walk | 0 | 50 | 0.00 | ||
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 0 | 50 | 0.00 | ||
| V1 | TOTAL | 0 | 205 | 0.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 0 | 50 | 0.00 | ||
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 0 | 50 | 0.00 | ||
| V2 | bijection | sram_ctrl_bijection | 0 | 50 | 0.00 | ||
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 0 | 50 | 0.00 | ||
| V2 | lc_escalation | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2 | executable | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2 | partial_access | sram_ctrl_partial_access | 0 | 50 | 0.00 | ||
| sram_ctrl_partial_access_b2b | 0 | 50 | 0.00 | ||||
| V2 | max_throughput | sram_ctrl_max_throughput | 0 | 50 | 0.00 | ||
| sram_ctrl_throughput_w_partial_write | 0 | 50 | 0.00 | ||||
| V2 | regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0 | 50 | 0.00 | ||
| V2 | stress_all | sram_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | sram_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| sram_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 45 | 0.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1040 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 3 | 3 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1042 failures:
0.sram_ctrl_smoke.83637796646575388491205654285832695898296443357179829190916841397556493000162
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest/run.log
1.sram_ctrl_smoke.14327614632125722006655542260555019524330300145499835836486444572563400759402
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest/run.log
... and 48 more failures.
0.sram_ctrl_multiple_keys.50008124126219573859486035701147771213622104615139907750235987945682590571746
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest/run.log
1.sram_ctrl_multiple_keys.14384637160213044432441307569891699994129092625035247463363292724546017519795
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest/run.log
... and 48 more failures.
0.sram_ctrl_bijection.21129893685102185307086780973339649780164238051659409294768792062379228325655
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest/run.log
1.sram_ctrl_bijection.89337749524939359342946945639413143095176304087756690960303010080166263277969
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest/run.log
... and 48 more failures.
0.sram_ctrl_stress_pipeline.113222277857865213167692402853075934029777002652358023850622266705085848659147
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log
1.sram_ctrl_stress_pipeline.92457455785223535980302135018797432445716691165272471009934723813374418556866
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest/run.log
... and 48 more failures.
0.sram_ctrl_partial_access.13071176026212869114942031754100336970729675660417144468242912024155219288600
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest/run.log
1.sram_ctrl_partial_access.8129085320557553911512155574467583979477854498386181750163259729035061927568
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.