Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	255084371	1			T1	125322		T2	71582		T3	672974
instr_valid_dis	234481870	1			T1	125322		T3	672974		T10	17562
instr_en	11326670	1			T2	71582		T13	191726		T23	19692

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	6983038	1			T13	79108		T24	43516		T32	25596
sram_ifetch_valid_disable	235013265	1			T1	125322		T3	672974		T10	17562
sram_ifetch_enable	13088068	1			T2	71582		T13	270344		T23	19692

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	255084371	1			T1	125322		T2	71582		T3	672974
hw_debug_en_valid_off	235220595	1			T1	125322		T2	71582		T3	672974
hw_debug_en_on	14512035	1			T13	126080		T23	19692		T24	81170

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	235013265	1			T1	125322		T3	672974		T10	17562
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	224322884	1			T1	125322		T3	672974		T10	17562
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5060036	1			T13	24472		T111	101356		T36	62
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2080926	1			T13	42918		T24	15764		T32	10626
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	947120	1			T13	23468		T124	43982		T125	117888
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	949726	1			T13	19450		T132	4980		T127	24300
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3837272	1			T24	27752		T32	14970		T124	40160
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2565180	1			T124	40160		T125	112222		T129	123252
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	880080	1			T32	14970		T125	30976		T135	15304
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5132949	1			T13	28128		T24	37348		T126	78
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1548141	1			T13	13348		T126	78		T32	16018
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1458678	1			T13	14780		T111	47890		T32	22812

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	4110824	1			T2	71582		T13	147804		T23	19692
lc_exec_en	5541814	1			T13	97952		T23	19692		T24	16070
valid_exec_dis	233954503	1			T1	125322		T3	672974		T10	17562
invalid_exec_dis	20071106	1			T2	71582		T13	349452		T23	19692