Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	105438018	1			T1	3129		T2	19651		T3	305824
triple_byte_access	2596792	1			T1	7047		T2	415		T3	6150
halfword_access	3992438	1			T1	13141		T2	566		T3	9361
byte_access	5591142	1			T1	24841		T2	762		T3	12123
zero_access	1706033	1			T1	14503		T2	215		T3	3029

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58956858

1

T1

31185

T2

14505

T3

168528

auto[1]

60367565

1

T1

31476

T2

7104

T3

167959

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	51922550	1			T1	274		T2	13173		T3	153213
auto[0]	triple_byte_access	1226550	1			T1	1370		T2	287		T3	3087
auto[0]	halfword_access	1937812	1			T1	4558		T2	384		T3	4727
auto[0]	byte_access	2849104	1			T1	13305		T2	520		T3	6003
auto[0]	zero_access	1020842	1			T1	11678		T2	141		T3	1498
auto[1]	word_access	53515468	1			T1	2855		T2	6478		T3	152611
auto[1]	triple_byte_access	1370242	1			T1	5677		T2	128		T3	3063
auto[1]	halfword_access	2054626	1			T1	8583		T2	182		T3	4634
auto[1]	byte_access	2742038	1			T1	11536		T2	242		T3	6120
auto[1]	zero_access	685191	1			T1	2825		T2	74		T3	1531