Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	286967900	1			T1	329846		T2	124010		T4	6976
instr_valid_dis	260790998	1			T1	329846		T2	124010		T4	6976
instr_en	16052012	1			T10	176032		T13	87040		T14	33124

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	8825156	1			T10	45944		T13	41038		T14	27080
sram_ifetch_valid_disable	264612730	1			T1	329846		T2	124010		T4	6976
sram_ifetch_enable	13530014	1			T10	176386		T13	89434		T14	15930

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	286967900	1			T1	329846		T2	124010		T4	6976
hw_debug_en_valid_off	260789316	1			T1	329846		T2	124010		T4	6976
hw_debug_en_on	19292908	1			T10	190316		T13	69250		T14	20058

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	264612730	1			T1	329846		T2	124010		T4	6976
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	252816722	1			T1	329846		T2	124010		T4	6976
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8859594	1			T10	69284		T13	20000		T14	13790
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2617872	1			T10	1244		T13	27222		T14	7746
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1351382	1			T13	27222		T21	78		T128	42666
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	679242	1			T10	1244		T26	20000		T27	14456
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4965830	1			T10	14658		T13	13816		T14	58
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	842898	1			T13	13816		T26	47874		T121	13688
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	720088	1			T10	14658		T14	58		T27	25364
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9636558	1			T10	71920		T13	42		T14	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2188168	1			T13	42		T14	20000		T26	19816
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6422396	1			T10	69284		T26	46412		T120	64036

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5319832	1			T10	90846		T13	67040		T26	90238
lc_exec_en	4690520	1			T10	103738		T13	55392		T26	187108
valid_exec_dis	257603212	1			T1	329846		T2	124010		T4	6976
invalid_exec_dis	22355170	1			T10	222330		T13	130472		T14	43010