Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	120261539	1			T1	29855		T2	3026		T4	997
triple_byte_access	2687793	1			T1	27130		T2	6894		T4	25
halfword_access	4134442	1			T1	40636		T2	12956		T4	25
byte_access	5809469	1			T1	53793		T2	24618		T4	43
zero_access	1792613	1			T1	13509		T2	14511		T4	7

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66770772

1

T1

82573

T2

30974

T4

530

auto[1]

67915084

1

T1

82350

T2

31031

T4

567

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	59455187	1			T1	14898		T2	252		T4	478
auto[0]	triple_byte_access	1266002	1			T1	13688		T2	1290		T4	15
auto[0]	halfword_access	2002909	1			T1	20294		T2	4442		T4	12
auto[0]	byte_access	2966808	1			T1	26942		T2	13347		T4	19
auto[0]	zero_access	1079866	1			T1	6751		T2	11643		T4	6
auto[1]	word_access	60806352	1			T1	14957		T2	2774		T4	519
auto[1]	triple_byte_access	1421791	1			T1	13442		T2	5604		T4	10
auto[1]	halfword_access	2131533	1			T1	20342		T2	8514		T4	13
auto[1]	byte_access	2842661	1			T1	26851		T2	11271		T4	24
auto[1]	zero_access	712747	1			T1	6758		T2	2868		T4	1