Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	282068512	1			T1	15988		T2	4676		T3	3480
instr_valid_dis	257967361	1			T1	15988		T2	4676		T3	3480
instr_en	18105096	1			T17	2476		T19	37380		T7	162084

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10934880	1			T18	44218		T19	43930		T7	43114
sram_ifetch_valid_disable	256694196	1			T1	15988		T2	4676		T3	3480
sram_ifetch_enable	14439436	1			T17	58		T18	159380		T19	26

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	282068512	1			T1	15988		T2	4676		T3	3480
hw_debug_en_valid_off	256536570	1			T1	15988		T2	4676		T3	3480
hw_debug_en_on	18100276	1			T18	116252		T19	42956		T7	115294

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	256694196	1			T1	15988		T2	4676		T3	3480
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	247839209	1			T1	15988		T2	4676		T3	3480
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	6569850	1			T17	2476		T19	20056		T7	145384
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2091840	1			T19	14934		T7	3238		T30	35964
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	702000	1			T7	3238		T117	20000		T122	82374
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1036396	1			T19	14934		T30	35964		T103	3148
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7491654	1			T18	44218		T19	22874		T7	39876
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3209648	1			T18	44218		T26	237838		T118	33652
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3909488	1			T19	2364		T30	19570		T103	37410
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5235946	1			T19	20056		T7	4806		T30	43192
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1694708	1			T30	28260		T117	17634		T122	15950
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2409916	1			T19	20056		T7	4806		T30	14932

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5935820	1			T19	26		T7	16700		T30	134358
lc_exec_en	5372676	1			T18	72034		T19	26		T7	70612
valid_exec_dis	254064994	1			T1	15988		T2	4676		T3	3480
invalid_exec_dis	25374316	1			T17	58		T18	203598		T19	43956