Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	117765556	1			T1	7269		T2	428		T3	121
triple_byte_access	2668942	1			T1	148		T2	402		T3	3
halfword_access	4102083	1			T1	211		T2	591		T3	3
byte_access	5746777	1			T1	298		T2	730		T3	4
zero_access	1759828	1			T1	68		T2	187		T3	1

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65509242

1

T1

3980

T2

1131

T3

67

auto[1]

66533944

1

T1

4014

T2

1207

T3

65

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	58264295	1			T1	3620		T2	208		T3	61
auto[0]	triple_byte_access	1261619	1			T1	67		T2	193		T3	2
auto[0]	halfword_access	1990821	1			T1	103		T2	276		T3	1
auto[0]	byte_access	2936916	1			T1	157		T2	368		T3	2
auto[0]	zero_access	1055591	1			T1	33		T2	86		T3	1
auto[1]	word_access	59501261	1			T1	3649		T2	220		T3	60
auto[1]	triple_byte_access	1407323	1			T1	81		T2	209		T3	1
auto[1]	halfword_access	2111262	1			T1	108		T2	315		T3	2
auto[1]	byte_access	2809861	1			T1	141		T2	362		T3	2
auto[1]	zero_access	704237	1			T1	35		T2	101		T6	376