| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.28 | 100.00 | 97.62 | 100.00 | 100.00 | 99.15 | 99.70 | 98.52 |
| T800 | /workspace/coverage/default/2.sram_ctrl_mem_walk.2017288544 | Feb 21 12:56:31 PM PST 24 | Feb 21 12:58:33 PM PST 24 | 2002964869 ps | ||
| T801 | /workspace/coverage/default/40.sram_ctrl_partial_access.583085895 | Feb 21 01:00:31 PM PST 24 | Feb 21 01:02:17 PM PST 24 | 3432151993 ps | ||
| T802 | /workspace/coverage/default/2.sram_ctrl_smoke.3905965106 | Feb 21 12:56:27 PM PST 24 | Feb 21 12:57:00 PM PST 24 | 929406155 ps | ||
| T803 | /workspace/coverage/default/42.sram_ctrl_mem_walk.2586870986 | Feb 21 01:00:57 PM PST 24 | Feb 21 01:03:26 PM PST 24 | 21515400104 ps | ||
| T804 | /workspace/coverage/default/38.sram_ctrl_smoke.1109781097 | Feb 21 01:00:17 PM PST 24 | Feb 21 01:01:32 PM PST 24 | 3218934945 ps | ||
| T805 | /workspace/coverage/default/33.sram_ctrl_smoke.1331756273 | Feb 21 12:59:22 PM PST 24 | Feb 21 01:00:10 PM PST 24 | 1112138361 ps | ||
| T806 | /workspace/coverage/default/27.sram_ctrl_executable.655637288 | Feb 21 12:58:39 PM PST 24 | Feb 21 01:10:50 PM PST 24 | 73803193022 ps | ||
| T807 | /workspace/coverage/default/9.sram_ctrl_lc_escalation.1609291133 | Feb 21 12:57:01 PM PST 24 | Feb 21 01:00:15 PM PST 24 | 35294098862 ps | ||
| T808 | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2808193741 | Feb 21 12:57:11 PM PST 24 | Feb 21 01:00:45 PM PST 24 | 9766965915 ps | ||
| T809 | /workspace/coverage/default/37.sram_ctrl_max_throughput.3392487596 | Feb 21 01:00:06 PM PST 24 | Feb 21 01:00:43 PM PST 24 | 734091156 ps | ||
| T810 | /workspace/coverage/default/22.sram_ctrl_partial_access.923938700 | Feb 21 12:57:54 PM PST 24 | Feb 21 12:58:09 PM PST 24 | 751672592 ps | ||
| T811 | /workspace/coverage/default/4.sram_ctrl_bijection.1960880017 | Feb 21 12:56:45 PM PST 24 | Feb 21 01:10:13 PM PST 24 | 95140845371 ps | ||
| T812 | /workspace/coverage/default/34.sram_ctrl_stress_all.4013550598 | Feb 21 12:59:57 PM PST 24 | Feb 21 01:54:00 PM PST 24 | 79532426164 ps | ||
| T813 | /workspace/coverage/default/48.sram_ctrl_smoke.73243618 | Feb 21 01:01:43 PM PST 24 | Feb 21 01:01:59 PM PST 24 | 1363178041 ps | ||
| T814 | /workspace/coverage/default/25.sram_ctrl_smoke.2258267304 | Feb 21 12:58:19 PM PST 24 | Feb 21 12:58:39 PM PST 24 | 2132802105 ps | ||
| T815 | /workspace/coverage/default/35.sram_ctrl_mem_walk.4080273994 | Feb 21 12:59:59 PM PST 24 | Feb 21 01:02:03 PM PST 24 | 7055309007 ps | ||
| T816 | /workspace/coverage/default/10.sram_ctrl_mem_walk.1067730940 | Feb 21 12:57:02 PM PST 24 | Feb 21 12:59:00 PM PST 24 | 4116218834 ps | ||
| T817 | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.224355795 | Feb 21 01:00:26 PM PST 24 | Feb 21 01:06:52 PM PST 24 | 5740094986 ps | ||
| T818 | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.648569929 | Feb 21 12:56:42 PM PST 24 | Feb 21 01:01:48 PM PST 24 | 16523653085 ps | ||
| T819 | /workspace/coverage/default/37.sram_ctrl_bijection.3365389304 | Feb 21 01:00:08 PM PST 24 | Feb 21 01:26:05 PM PST 24 | 23570119881 ps | ||
| T820 | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.294380208 | Feb 21 12:57:54 PM PST 24 | Feb 21 01:09:40 PM PST 24 | 23230159306 ps | ||
| T821 | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2270183393 | Feb 21 12:57:46 PM PST 24 | Feb 21 12:59:09 PM PST 24 | 6268050051 ps | ||
| T822 | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1356560618 | Feb 21 12:57:43 PM PST 24 | Feb 21 01:06:23 PM PST 24 | 24413307915 ps | ||
| T823 | /workspace/coverage/default/21.sram_ctrl_partial_access.1518173170 | Feb 21 12:57:55 PM PST 24 | Feb 21 12:59:28 PM PST 24 | 890108434 ps | ||
| T824 | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2424784747 | Feb 21 12:58:39 PM PST 24 | Feb 21 12:59:53 PM PST 24 | 992715954 ps | ||
| T825 | /workspace/coverage/default/25.sram_ctrl_lc_escalation.1901341086 | Feb 21 12:58:28 PM PST 24 | Feb 21 01:00:01 PM PST 24 | 9910836512 ps | ||
| T826 | /workspace/coverage/default/9.sram_ctrl_partial_access.2379795622 | Feb 21 12:56:48 PM PST 24 | Feb 21 12:57:37 PM PST 24 | 2867181958 ps | ||
| T827 | /workspace/coverage/default/23.sram_ctrl_partial_access.4267648516 | Feb 21 12:58:08 PM PST 24 | Feb 21 12:58:22 PM PST 24 | 874014586 ps | ||
| T828 | /workspace/coverage/default/47.sram_ctrl_bijection.1523054726 | Feb 21 01:01:28 PM PST 24 | Feb 21 01:37:38 PM PST 24 | 267553343893 ps | ||
| T829 | /workspace/coverage/default/37.sram_ctrl_multiple_keys.3405368502 | Feb 21 01:00:07 PM PST 24 | Feb 21 01:11:49 PM PST 24 | 121820870355 ps | ||
| T830 | /workspace/coverage/default/33.sram_ctrl_max_throughput.2338037874 | Feb 21 12:59:39 PM PST 24 | Feb 21 01:00:06 PM PST 24 | 1447468869 ps | ||
| T831 | /workspace/coverage/default/2.sram_ctrl_ram_cfg.3636672971 | Feb 21 12:56:30 PM PST 24 | Feb 21 12:56:36 PM PST 24 | 1165259637 ps | ||
| T832 | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1754440828 | Feb 21 12:58:28 PM PST 24 | Feb 21 12:59:39 PM PST 24 | 949455294 ps | ||
| T833 | /workspace/coverage/default/21.sram_ctrl_smoke.3035850807 | Feb 21 12:57:53 PM PST 24 | Feb 21 12:59:26 PM PST 24 | 1441072480 ps | ||
| T834 | /workspace/coverage/default/49.sram_ctrl_mem_walk.1892862886 | Feb 21 01:01:58 PM PST 24 | Feb 21 01:07:07 PM PST 24 | 33282697276 ps | ||
| T835 | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3531993731 | Feb 21 12:59:41 PM PST 24 | Feb 21 01:00:36 PM PST 24 | 1464661479 ps | ||
| T836 | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.247159688 | Feb 21 12:58:21 PM PST 24 | Feb 21 01:28:18 PM PST 24 | 12814572828 ps | ||
| T837 | /workspace/coverage/default/21.sram_ctrl_mem_walk.810204423 | Feb 21 12:57:56 PM PST 24 | Feb 21 01:02:06 PM PST 24 | 16422848644 ps | ||
| T838 | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1284471857 | Feb 21 12:56:42 PM PST 24 | Feb 21 01:02:03 PM PST 24 | 19625061986 ps | ||
| T839 | /workspace/coverage/default/36.sram_ctrl_partial_access.2844849422 | Feb 21 01:00:00 PM PST 24 | Feb 21 01:00:23 PM PST 24 | 1812307992 ps | ||
| T840 | /workspace/coverage/default/41.sram_ctrl_ram_cfg.439985149 | Feb 21 01:00:56 PM PST 24 | Feb 21 01:01:02 PM PST 24 | 633637753 ps | ||
| T841 | /workspace/coverage/default/24.sram_ctrl_alert_test.2195964832 | Feb 21 12:58:20 PM PST 24 | Feb 21 12:58:21 PM PST 24 | 27164850 ps | ||
| T842 | /workspace/coverage/default/14.sram_ctrl_alert_test.297364318 | Feb 21 12:57:27 PM PST 24 | Feb 21 12:57:28 PM PST 24 | 20417102 ps | ||
| T843 | /workspace/coverage/default/16.sram_ctrl_smoke.2533904273 | Feb 21 12:57:18 PM PST 24 | Feb 21 12:57:58 PM PST 24 | 2003896764 ps | ||
| T844 | /workspace/coverage/default/35.sram_ctrl_multiple_keys.922485706 | Feb 21 12:59:58 PM PST 24 | Feb 21 01:28:39 PM PST 24 | 13342464377 ps | ||
| T845 | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.710542591 | Feb 21 01:01:44 PM PST 24 | Feb 21 01:04:02 PM PST 24 | 1184867019 ps | ||
| T846 | /workspace/coverage/default/1.sram_ctrl_max_throughput.1338885122 | Feb 21 12:56:19 PM PST 24 | Feb 21 12:56:50 PM PST 24 | 686050996 ps | ||
| T847 | /workspace/coverage/default/12.sram_ctrl_ram_cfg.1467498049 | Feb 21 12:57:11 PM PST 24 | Feb 21 12:57:26 PM PST 24 | 1342779837 ps | ||
| T848 | /workspace/coverage/default/35.sram_ctrl_bijection.754543757 | Feb 21 01:00:01 PM PST 24 | Feb 21 01:33:25 PM PST 24 | 188063682081 ps | ||
| T849 | /workspace/coverage/default/39.sram_ctrl_partial_access.2060773030 | Feb 21 01:00:30 PM PST 24 | Feb 21 01:01:42 PM PST 24 | 5032392357 ps | ||
| T850 | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2387511856 | Feb 21 12:58:19 PM PST 24 | Feb 21 01:04:38 PM PST 24 | 93892567699 ps | ||
| T851 | /workspace/coverage/default/46.sram_ctrl_max_throughput.1960521814 | Feb 21 01:01:27 PM PST 24 | Feb 21 01:02:13 PM PST 24 | 2968555572 ps | ||
| T852 | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3814960333 | Feb 21 12:58:28 PM PST 24 | Feb 21 01:00:51 PM PST 24 | 19779565504 ps | ||
| T853 | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3152328808 | Feb 21 12:59:02 PM PST 24 | Feb 21 01:05:57 PM PST 24 | 70385443319 ps | ||
| T854 | /workspace/coverage/default/40.sram_ctrl_ram_cfg.3602697811 | Feb 21 01:00:44 PM PST 24 | Feb 21 01:00:52 PM PST 24 | 1532936936 ps | ||
| T37 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2065390740 | Feb 21 12:31:14 PM PST 24 | Feb 21 12:31:18 PM PST 24 | 39954313 ps | ||
| T62 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1991596214 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:31:38 PM PST 24 | 29729558 ps | ||
| T34 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1001677310 | Feb 21 12:31:21 PM PST 24 | Feb 21 12:31:24 PM PST 24 | 198683659 ps | ||
| T63 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.205365805 | Feb 21 12:32:08 PM PST 24 | Feb 21 12:32:09 PM PST 24 | 30422839 ps | ||
| T101 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1414917772 | Feb 21 12:31:42 PM PST 24 | Feb 21 12:31:43 PM PST 24 | 25786883 ps | ||
| T35 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.66146987 | Feb 21 12:31:40 PM PST 24 | Feb 21 12:31:43 PM PST 24 | 208954655 ps | ||
| T36 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2334206032 | Feb 21 12:31:17 PM PST 24 | Feb 21 12:31:19 PM PST 24 | 148129632 ps | ||
| T64 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.190628478 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:33:55 PM PST 24 | 16818157011 ps | ||
| T96 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2629132567 | Feb 21 12:31:24 PM PST 24 | Feb 21 12:31:26 PM PST 24 | 50280883 ps | ||
| T102 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.742332380 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:31:21 PM PST 24 | 20181616 ps | ||
| T65 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2784161550 | Feb 21 12:31:09 PM PST 24 | Feb 21 12:31:11 PM PST 24 | 15817447 ps | ||
| T51 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2943266681 | Feb 21 12:31:21 PM PST 24 | Feb 21 12:31:23 PM PST 24 | 23086279 ps | ||
| T58 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1901220116 | Feb 21 12:31:36 PM PST 24 | Feb 21 12:31:38 PM PST 24 | 269000065 ps | ||
| T97 | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1805707376 | Feb 21 12:31:35 PM PST 24 | Feb 21 12:31:36 PM PST 24 | 20651517 ps | ||
| T66 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2277031927 | Feb 21 12:31:08 PM PST 24 | Feb 21 12:31:09 PM PST 24 | 15314067 ps | ||
| T67 | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.292622769 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:33:13 PM PST 24 | 7323161527 ps | ||
| T104 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.410887068 | Feb 21 12:31:05 PM PST 24 | Feb 21 12:31:09 PM PST 24 | 163979640 ps | ||
| T68 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.86470448 | Feb 21 12:31:40 PM PST 24 | Feb 21 12:33:34 PM PST 24 | 7279240759 ps | ||
| T69 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3686270056 | Feb 21 12:31:24 PM PST 24 | Feb 21 12:31:28 PM PST 24 | 666264264 ps | ||
| T52 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1413648503 | Feb 21 12:31:16 PM PST 24 | Feb 21 12:31:19 PM PST 24 | 84742738 ps | ||
| T855 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4096834043 | Feb 21 12:31:39 PM PST 24 | Feb 21 12:31:40 PM PST 24 | 26883213 ps | ||
| T98 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1035899455 | Feb 21 12:31:35 PM PST 24 | Feb 21 12:31:36 PM PST 24 | 189052279 ps | ||
| T53 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1983302731 | Feb 21 12:31:39 PM PST 24 | Feb 21 12:31:42 PM PST 24 | 189886607 ps | ||
| T54 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1734560393 | Feb 21 12:31:19 PM PST 24 | Feb 21 12:31:23 PM PST 24 | 194679688 ps | ||
| T55 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.939149824 | Feb 21 12:31:32 PM PST 24 | Feb 21 12:31:34 PM PST 24 | 90055721 ps | ||
| T56 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2986115418 | Feb 21 12:31:11 PM PST 24 | Feb 21 12:31:13 PM PST 24 | 118723011 ps | ||
| T57 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3745132111 | Feb 21 12:31:16 PM PST 24 | Feb 21 12:31:19 PM PST 24 | 45352237 ps | ||
| T59 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4185035016 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:31:40 PM PST 24 | 43739488 ps | ||
| T60 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1546125541 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:31:44 PM PST 24 | 221220602 ps | ||
| T70 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3182556861 | Feb 21 12:31:19 PM PST 24 | Feb 21 12:31:20 PM PST 24 | 37952632 ps | ||
| T71 | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.681512285 | Feb 21 12:32:33 PM PST 24 | Feb 21 12:34:10 PM PST 24 | 7364575745 ps | ||
| T856 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1491684494 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:31:21 PM PST 24 | 11397395 ps | ||
| T857 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1947188281 | Feb 21 12:31:33 PM PST 24 | Feb 21 12:31:34 PM PST 24 | 37446173 ps | ||
| T858 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3045392899 | Feb 21 12:31:13 PM PST 24 | Feb 21 12:31:15 PM PST 24 | 35089104 ps | ||
| T82 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1801727095 | Feb 21 12:31:34 PM PST 24 | Feb 21 12:32:31 PM PST 24 | 3777356363 ps | ||
| T83 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2022576662 | Feb 21 12:31:13 PM PST 24 | Feb 21 12:33:29 PM PST 24 | 3817069656 ps | ||
| T61 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3381468192 | Feb 21 12:32:01 PM PST 24 | Feb 21 12:32:04 PM PST 24 | 224695023 ps | ||
| T84 | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3046585509 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:32:17 PM PST 24 | 3930550870 ps | ||
| T106 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2029825506 | Feb 21 12:31:23 PM PST 24 | Feb 21 12:31:26 PM PST 24 | 95597722 ps | ||
| T91 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4161786659 | Feb 21 12:31:21 PM PST 24 | Feb 21 12:31:22 PM PST 24 | 71043632 ps | ||
| T92 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2751613493 | Feb 21 12:31:11 PM PST 24 | Feb 21 12:31:12 PM PST 24 | 29487317 ps | ||
| T859 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1981582596 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:31:39 PM PST 24 | 174741809 ps | ||
| T112 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1397475929 | Feb 21 12:31:41 PM PST 24 | Feb 21 12:31:42 PM PST 24 | 179585585 ps | ||
| T95 | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2792341984 | Feb 21 12:31:41 PM PST 24 | Feb 21 12:33:59 PM PST 24 | 3709020282 ps | ||
| T111 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3838035501 | Feb 21 12:32:17 PM PST 24 | Feb 21 12:32:22 PM PST 24 | 533120180 ps | ||
| T860 | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3746616950 | Feb 21 12:31:22 PM PST 24 | Feb 21 12:31:24 PM PST 24 | 31745980 ps | ||
| T861 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.721484833 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:31:38 PM PST 24 | 17377522 ps | ||
| T862 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3636821211 | Feb 21 12:31:35 PM PST 24 | Feb 21 12:33:35 PM PST 24 | 7280167520 ps | ||
| T863 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2552366816 | Feb 21 12:31:18 PM PST 24 | Feb 21 12:31:19 PM PST 24 | 20913275 ps | ||
| T864 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.327904590 | Feb 21 12:31:34 PM PST 24 | Feb 21 12:31:36 PM PST 24 | 30304248 ps | ||
| T865 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.401919645 | Feb 21 12:31:25 PM PST 24 | Feb 21 12:31:26 PM PST 24 | 105576419 ps | ||
| T866 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4255837096 | Feb 21 12:31:35 PM PST 24 | Feb 21 12:31:37 PM PST 24 | 119770236 ps | ||
| T93 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2228447780 | Feb 21 12:31:13 PM PST 24 | Feb 21 12:32:02 PM PST 24 | 15089830876 ps | ||
| T867 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1381982750 | Feb 21 12:31:18 PM PST 24 | Feb 21 12:31:18 PM PST 24 | 125386923 ps | ||
| T94 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.786057599 | Feb 21 12:32:37 PM PST 24 | Feb 21 12:32:38 PM PST 24 | 57720758 ps | ||
| T868 | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3500544653 | Feb 21 12:31:19 PM PST 24 | Feb 21 12:33:18 PM PST 24 | 14119684425 ps | ||
| T869 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1502757707 | Feb 21 12:31:21 PM PST 24 | Feb 21 12:31:22 PM PST 24 | 26659471 ps | ||
| T870 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2452934405 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:32:31 PM PST 24 | 15412693193 ps | ||
| T871 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1365468127 | Feb 21 12:31:29 PM PST 24 | Feb 21 12:31:30 PM PST 24 | 17361417 ps | ||
| T872 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2405463561 | Feb 21 12:31:34 PM PST 24 | Feb 21 12:31:35 PM PST 24 | 51003801 ps | ||
| T873 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3165715929 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:31:22 PM PST 24 | 220810901 ps | ||
| T108 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3873498421 | Feb 21 12:31:10 PM PST 24 | Feb 21 12:31:13 PM PST 24 | 279061866 ps | ||
| T874 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.70428249 | Feb 21 12:31:34 PM PST 24 | Feb 21 12:31:35 PM PST 24 | 26735225 ps | ||
| T875 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1895741733 | Feb 21 12:31:12 PM PST 24 | Feb 21 12:31:13 PM PST 24 | 22722598 ps | ||
| T876 | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1916971579 | Feb 21 12:31:27 PM PST 24 | Feb 21 12:31:28 PM PST 24 | 149484802 ps | ||
| T877 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.137604996 | Feb 21 12:31:39 PM PST 24 | Feb 21 12:31:44 PM PST 24 | 309202485 ps | ||
| T115 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3532263175 | Feb 21 12:31:22 PM PST 24 | Feb 21 12:31:24 PM PST 24 | 184550979 ps | ||
| T107 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3788230625 | Feb 21 12:31:18 PM PST 24 | Feb 21 12:31:20 PM PST 24 | 181898353 ps | ||
| T878 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2506129722 | Feb 21 12:31:13 PM PST 24 | Feb 21 12:31:14 PM PST 24 | 22799309 ps | ||
| T879 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2767605381 | Feb 21 12:31:18 PM PST 24 | Feb 21 12:33:21 PM PST 24 | 7367112950 ps | ||
| T880 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3233603901 | Feb 21 12:31:16 PM PST 24 | Feb 21 12:31:19 PM PST 24 | 226516719 ps | ||
| T881 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3627452216 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:31:39 PM PST 24 | 14023068 ps | ||
| T882 | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4255641366 | Feb 21 12:32:37 PM PST 24 | Feb 21 12:32:38 PM PST 24 | 20922559 ps | ||
| T883 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.701992743 | Feb 21 12:31:54 PM PST 24 | Feb 21 12:31:55 PM PST 24 | 12809118 ps | ||
| T884 | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.927282460 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:31:21 PM PST 24 | 58444639 ps | ||
| T885 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1059257418 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:31:39 PM PST 24 | 14682732 ps | ||
| T886 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.675249169 | Feb 21 12:31:22 PM PST 24 | Feb 21 12:31:26 PM PST 24 | 73151602 ps | ||
| T887 | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1030484849 | Feb 21 12:31:22 PM PST 24 | Feb 21 12:33:47 PM PST 24 | 7841890135 ps | ||
| T888 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3784839159 | Feb 21 12:31:09 PM PST 24 | Feb 21 12:31:10 PM PST 24 | 23350802 ps | ||
| T889 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1881744361 | Feb 21 12:32:37 PM PST 24 | Feb 21 12:37:02 PM PST 24 | 7665980765 ps | ||
| T890 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1888267675 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:31:42 PM PST 24 | 110377611 ps | ||
| T109 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.774262809 | Feb 21 12:31:39 PM PST 24 | Feb 21 12:31:42 PM PST 24 | 350310279 ps | ||
| T891 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2451355787 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:31:23 PM PST 24 | 526904266 ps | ||
| T892 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3508224260 | Feb 21 12:31:42 PM PST 24 | Feb 21 12:31:45 PM PST 24 | 58399343 ps | ||
| T893 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1943131797 | Feb 21 12:31:13 PM PST 24 | Feb 21 12:31:16 PM PST 24 | 806079151 ps | ||
| T894 | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3422234645 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:33:14 PM PST 24 | 10533151109 ps | ||
| T895 | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3773230463 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:31:39 PM PST 24 | 29342640 ps | ||
| T896 | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2660861428 | Feb 21 12:31:13 PM PST 24 | Feb 21 12:31:15 PM PST 24 | 19250368 ps | ||
| T897 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1383671753 | Feb 21 12:31:39 PM PST 24 | Feb 21 12:31:40 PM PST 24 | 37470158 ps | ||
| T898 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2967036564 | Feb 21 12:31:20 PM PST 24 | Feb 21 12:31:21 PM PST 24 | 34613740 ps | ||
| T899 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.541548604 | Feb 21 12:31:15 PM PST 24 | Feb 21 12:31:17 PM PST 24 | 62284406 ps | ||
| T900 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2005309321 | Feb 21 12:31:23 PM PST 24 | Feb 21 12:31:29 PM PST 24 | 141086481 ps | ||
| T113 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2121467193 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:31:39 PM PST 24 | 205127001 ps | ||
| T901 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.673818967 | Feb 21 12:31:22 PM PST 24 | Feb 21 12:31:23 PM PST 24 | 25583871 ps | ||
| T902 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4062885394 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:31:41 PM PST 24 | 403090134 ps | ||
| T903 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3043352531 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:31:39 PM PST 24 | 72415546 ps | ||
| T904 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.910810069 | Feb 21 12:31:09 PM PST 24 | Feb 21 12:31:11 PM PST 24 | 28896429 ps | ||
| T905 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3097325525 | Feb 21 12:31:21 PM PST 24 | Feb 21 12:31:22 PM PST 24 | 44331856 ps | ||
| T906 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.790827427 | Feb 21 12:31:21 PM PST 24 | Feb 21 12:31:22 PM PST 24 | 80180142 ps | ||
| T110 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.985120139 | Feb 21 12:31:18 PM PST 24 | Feb 21 12:31:21 PM PST 24 | 210457943 ps | ||
| T907 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2565589289 | Feb 21 12:31:38 PM PST 24 | Feb 21 12:31:41 PM PST 24 | 38843281 ps | ||
| T908 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3053108829 | Feb 21 12:31:42 PM PST 24 | Feb 21 12:31:44 PM PST 24 | 218116977 ps | ||
| T909 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.488159917 | Feb 21 12:31:23 PM PST 24 | Feb 21 12:33:46 PM PST 24 | 13643724087 ps | ||
| T910 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.468018672 | Feb 21 12:31:22 PM PST 24 | Feb 21 12:31:23 PM PST 24 | 35296477 ps | ||
| T911 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4194553641 | Feb 21 12:31:35 PM PST 24 | Feb 21 12:31:36 PM PST 24 | 46962231 ps | ||
| T912 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3650288442 | Feb 21 12:31:23 PM PST 24 | Feb 21 12:31:26 PM PST 24 | 302853066 ps | ||
| T913 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.518321280 | Feb 21 12:31:27 PM PST 24 | Feb 21 12:33:48 PM PST 24 | 15355145958 ps | ||
| T914 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1045106814 | Feb 21 12:31:36 PM PST 24 | Feb 21 12:33:46 PM PST 24 | 3872191550 ps | ||
| T915 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.229883400 | Feb 21 12:31:23 PM PST 24 | Feb 21 12:31:25 PM PST 24 | 21104351 ps | ||
| T916 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1405439077 | Feb 21 12:31:28 PM PST 24 | Feb 21 12:31:31 PM PST 24 | 108141982 ps | ||
| T114 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2655187845 | Feb 21 12:31:27 PM PST 24 | Feb 21 12:31:30 PM PST 24 | 1298779762 ps | ||
| T917 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1833481459 | Feb 21 12:31:37 PM PST 24 | Feb 21 12:31:38 PM PST 24 | 34183222 ps | ||
| T918 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.849977817 | Feb 21 12:31:10 PM PST 24 | Feb 21 12:31:12 PM PST 24 | 18758427 ps | ||
| T919 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.325098490 | Feb 21 12:31:33 PM PST 24 | Feb 21 12:31:34 PM PST 24 | 50177796 ps | ||
| T920 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3901709950 | Feb 21 12:31:34 PM PST 24 | Feb 21 12:36:01 PM PST 24 | 29358177882 ps |
| Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.3574629118 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5281182429 ps |
| CPU time | 72.2 seconds |
| Started | Feb 21 12:56:21 PM PST 24 |
| Finished | Feb 21 12:57:35 PM PST 24 |
| Peak memory | 214008 kb |
| Host | smart-9f684d74-f3dc-40a7-bb0d-d571519c2402 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574629118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.3574629118 |
| Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_regwen.1404792360 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3012823559 ps |
| CPU time | 42.21 seconds |
| Started | Feb 21 01:01:04 PM PST 24 |
| Finished | Feb 21 01:01:47 PM PST 24 |
| Peak memory | 252192 kb |
| Host | smart-d689dd69-6ddb-498e-9b46-961975bc1c87 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404792360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1404792360 |
| Directory | /workspace/43.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1001677310 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 198683659 ps |
| CPU time | 2.61 seconds |
| Started | Feb 21 12:31:21 PM PST 24 |
| Finished | Feb 21 12:31:24 PM PST 24 |
| Peak memory | 202828 kb |
| Host | smart-e75f10e9-972b-4eb3-b02e-4d23d77f16d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001677310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1001677310 |
| Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2065390740 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 39954313 ps |
| CPU time | 3.13 seconds |
| Started | Feb 21 12:31:14 PM PST 24 |
| Finished | Feb 21 12:31:18 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-68896701-c885-401b-9d09-96a7d6e087a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065390740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.2065390740 |
| Directory | /workspace/0.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3484610920 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 96744977434 ps |
| CPU time | 512.13 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:08:12 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-7e03df3b-5d8a-462d-a578-3e48428fad31 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484610920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.3484610920 |
| Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.2469056897 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 271032263505 ps |
| CPU time | 3413.85 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 01:54:14 PM PST 24 |
| Peak memory | 372192 kb |
| Host | smart-9ab2e488-828c-4575-97de-dd955b27ad49 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469056897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.2469056897 |
| Directory | /workspace/16.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.1491284855 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1140461091 ps |
| CPU time | 2.71 seconds |
| Started | Feb 21 12:56:13 PM PST 24 |
| Finished | Feb 21 12:56:17 PM PST 24 |
| Peak memory | 220904 kb |
| Host | smart-4ff5821e-ee4a-4126-9be4-3a783746223d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491284855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1491284855 |
| Directory | /workspace/0.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.3962745414 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 153779059664 ps |
| CPU time | 4879.24 seconds |
| Started | Feb 21 01:00:45 PM PST 24 |
| Finished | Feb 21 02:22:06 PM PST 24 |
| Peak memory | 379336 kb |
| Host | smart-5f95b8b9-3dc2-4c39-a9ad-e4f7ceb08ce3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962745414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.3962745414 |
| Directory | /workspace/40.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.3974090809 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 115451932 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 12:57:18 PM PST 24 |
| Finished | Feb 21 12:57:19 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-e560e07b-8614-440d-ac73-0638bb39b627 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974090809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3974090809 |
| Directory | /workspace/13.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3411149781 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14020737975 ps |
| CPU time | 744.29 seconds |
| Started | Feb 21 12:57:13 PM PST 24 |
| Finished | Feb 21 01:09:38 PM PST 24 |
| Peak memory | 373168 kb |
| Host | smart-add31a5e-edb3-46fd-a2d3-f66d42d4acf0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411149781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.3411149781 |
| Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.292622769 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 7323161527 ps |
| CPU time | 95.15 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:33:13 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-930cb57d-5845-4abf-8f5d-134a0aa8aaf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292622769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.292622769 |
| Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3873498421 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 279061866 ps |
| CPU time | 1.98 seconds |
| Started | Feb 21 12:31:10 PM PST 24 |
| Finished | Feb 21 12:31:13 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-70d08360-6ab5-494f-89ba-f0fb21a155c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873498421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.3873498421 |
| Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.1339359809 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 361472310 ps |
| CPU time | 13.53 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 12:57:16 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-fc387cab-ba08-418e-8a9f-cfed3720f983 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339359809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1339359809 |
| Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.2706966013 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 814306839465 ps |
| CPU time | 4412.6 seconds |
| Started | Feb 21 12:57:06 PM PST 24 |
| Finished | Feb 21 02:10:40 PM PST 24 |
| Peak memory | 372952 kb |
| Host | smart-af68edea-ccfa-4c14-abd6-0c532677e921 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706966013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.2706966013 |
| Directory | /workspace/10.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.774262809 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 350310279 ps |
| CPU time | 2.48 seconds |
| Started | Feb 21 12:31:39 PM PST 24 |
| Finished | Feb 21 12:31:42 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-d993bafd-6e37-400f-84f7-500bc72cd60d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774262809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sram_ctrl_tl_intg_err.774262809 |
| Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3381468192 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 224695023 ps |
| CPU time | 2.18 seconds |
| Started | Feb 21 12:32:01 PM PST 24 |
| Finished | Feb 21 12:32:04 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-7bf66098-1cdb-4ca7-a489-c39d41d3720b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381468192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.3381468192 |
| Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.3038664123 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 115403002726 ps |
| CPU time | 2508.69 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 01:39:09 PM PST 24 |
| Peak memory | 379280 kb |
| Host | smart-af2c1604-af67-4be2-80b4-3cdeacbeb634 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038664123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.3038664123 |
| Directory | /workspace/15.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2121467193 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 205127001 ps |
| CPU time | 1.49 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:31:39 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-4c66bfe5-6d31-4e4a-a3ca-1b0bd1b31fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121467193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.2121467193 |
| Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.3481862567 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 201513970802 ps |
| CPU time | 4273.88 seconds |
| Started | Feb 21 12:56:15 PM PST 24 |
| Finished | Feb 21 02:07:30 PM PST 24 |
| Peak memory | 386232 kb |
| Host | smart-e2c4f7d1-3459-4384-bbbb-20bd9058b474 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481862567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.3481862567 |
| Directory | /workspace/1.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2506129722 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 22799309 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:31:13 PM PST 24 |
| Finished | Feb 21 12:31:14 PM PST 24 |
| Peak memory | 202132 kb |
| Host | smart-6c6b6838-d08b-4239-9c2e-cde9fcdd1dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506129722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.2506129722 |
| Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.410887068 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 163979640 ps |
| CPU time | 1.52 seconds |
| Started | Feb 21 12:31:05 PM PST 24 |
| Finished | Feb 21 12:31:09 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-d903ee7e-a76e-4b1e-9e86-9aa9ad7721ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410887068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.410887068 |
| Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1381982750 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 125386923 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:31:18 PM PST 24 |
| Finished | Feb 21 12:31:18 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-845c20e0-1fad-4440-bbb8-4e3ee563b334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381982750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.1381982750 |
| Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2751613493 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 29487317 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:31:11 PM PST 24 |
| Finished | Feb 21 12:31:12 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-6e998d95-c270-4606-87e2-210fe88485a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751613493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2751613493 |
| Directory | /workspace/0.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2022576662 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3817069656 ps |
| CPU time | 135.7 seconds |
| Started | Feb 21 12:31:13 PM PST 24 |
| Finished | Feb 21 12:33:29 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-210fbf3c-18f8-4e6f-8a23-48f975854aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022576662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2022576662 |
| Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2660861428 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 19250368 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:31:13 PM PST 24 |
| Finished | Feb 21 12:31:15 PM PST 24 |
| Peak memory | 202064 kb |
| Host | smart-684234fc-363a-4c7e-a630-9a8267b190d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660861428 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2660861428 |
| Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3532263175 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 184550979 ps |
| CPU time | 1.51 seconds |
| Started | Feb 21 12:31:22 PM PST 24 |
| Finished | Feb 21 12:31:24 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-c2dd7209-bb54-49a7-b49d-53652a2592a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532263175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3532263175 |
| Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2277031927 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 15314067 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:31:08 PM PST 24 |
| Finished | Feb 21 12:31:09 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-12f2bca4-0e22-4458-b9e6-598c5b00639e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277031927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2277031927 |
| Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3233603901 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 226516719 ps |
| CPU time | 2.17 seconds |
| Started | Feb 21 12:31:16 PM PST 24 |
| Finished | Feb 21 12:31:19 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-860f87a4-dc38-4c7b-a78d-3b7a15c0bc3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233603901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.3233603901 |
| Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3045392899 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 35089104 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:31:13 PM PST 24 |
| Finished | Feb 21 12:31:15 PM PST 24 |
| Peak memory | 202096 kb |
| Host | smart-a8fdd1f6-905a-4f6f-9830-d27bf4e1d4fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045392899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.3045392899 |
| Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3784839159 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 23350802 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:31:09 PM PST 24 |
| Finished | Feb 21 12:31:10 PM PST 24 |
| Peak memory | 202068 kb |
| Host | smart-c47ddc6e-ba75-4200-81be-dfae267b2558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784839159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3784839159 |
| Directory | /workspace/1.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.518321280 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 15355145958 ps |
| CPU time | 140.2 seconds |
| Started | Feb 21 12:31:27 PM PST 24 |
| Finished | Feb 21 12:33:48 PM PST 24 |
| Peak memory | 210916 kb |
| Host | smart-0eb4b349-8f6e-43d3-a397-1d1b4ac4845e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518321280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.518321280 |
| Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.541548604 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 62284406 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:31:15 PM PST 24 |
| Finished | Feb 21 12:31:17 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-9259ac1c-160e-4726-a368-28c27c28f735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541548604 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.541548604 |
| Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2451355787 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 526904266 ps |
| CPU time | 2.72 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:31:23 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-ce17f5ac-73b8-456c-899f-fe0fe9d11044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451355787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2451355787 |
| Directory | /workspace/1.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.790827427 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 80180142 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:31:21 PM PST 24 |
| Finished | Feb 21 12:31:22 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-b20971d9-c1ec-48c1-af90-f2cc5e0e2fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790827427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_csr_rw.790827427 |
| Directory | /workspace/10.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1030484849 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 7841890135 ps |
| CPU time | 144.1 seconds |
| Started | Feb 21 12:31:22 PM PST 24 |
| Finished | Feb 21 12:33:47 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-154f06cf-27c0-4332-9d31-dbc6a7005c69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030484849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.1030484849 |
| Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4255641366 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 20922559 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:32:37 PM PST 24 |
| Finished | Feb 21 12:32:38 PM PST 24 |
| Peak memory | 202156 kb |
| Host | smart-169154d0-b3f4-4ae7-aaec-dc0ea1385629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255641366 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.4255641366 |
| Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1734560393 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 194679688 ps |
| CPU time | 2.93 seconds |
| Started | Feb 21 12:31:19 PM PST 24 |
| Finished | Feb 21 12:31:23 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-1940aca9-7681-454d-af47-f1bca7238f02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734560393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.1734560393 |
| Directory | /workspace/10.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3650288442 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 302853066 ps |
| CPU time | 1.43 seconds |
| Started | Feb 21 12:31:23 PM PST 24 |
| Finished | Feb 21 12:31:26 PM PST 24 |
| Peak memory | 210652 kb |
| Host | smart-0c402209-0277-40c7-8660-75f10f8e39a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650288442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.3650288442 |
| Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1383671753 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 37470158 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:31:39 PM PST 24 |
| Finished | Feb 21 12:31:40 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-508c4980-feae-407f-95eb-bd226e1aca2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383671753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.1383671753 |
| Directory | /workspace/11.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1801727095 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3777356363 ps |
| CPU time | 56.91 seconds |
| Started | Feb 21 12:31:34 PM PST 24 |
| Finished | Feb 21 12:32:31 PM PST 24 |
| Peak memory | 210832 kb |
| Host | smart-81621722-adbe-4b4e-abd9-ee2fadf5c24a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801727095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1801727095 |
| Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1991596214 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 29729558 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:31:38 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-77131fdc-67a4-434d-b419-aa20e8f1b123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991596214 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1991596214 |
| Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.137604996 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 309202485 ps |
| CPU time | 5.39 seconds |
| Started | Feb 21 12:31:39 PM PST 24 |
| Finished | Feb 21 12:31:44 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-5c79f9de-a66d-4375-b72a-6759f4e91a5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137604996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.137604996 |
| Directory | /workspace/11.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4255837096 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 119770236 ps |
| CPU time | 1.51 seconds |
| Started | Feb 21 12:31:35 PM PST 24 |
| Finished | Feb 21 12:31:37 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-e6e09493-d79e-4c29-9ecc-243e85c905d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255837096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.4255837096 |
| Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1414917772 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 25786883 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:31:42 PM PST 24 |
| Finished | Feb 21 12:31:43 PM PST 24 |
| Peak memory | 202104 kb |
| Host | smart-37e15358-5d8c-4fdc-9c9f-813251475578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414917772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.1414917772 |
| Directory | /workspace/12.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2792341984 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3709020282 ps |
| CPU time | 138.2 seconds |
| Started | Feb 21 12:31:41 PM PST 24 |
| Finished | Feb 21 12:33:59 PM PST 24 |
| Peak memory | 210224 kb |
| Host | smart-81f9e009-0957-4a39-9368-5ff233723208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792341984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2792341984 |
| Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1035899455 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 189052279 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:31:35 PM PST 24 |
| Finished | Feb 21 12:31:36 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-47fef778-13e0-4b67-ada1-056c4f32ca64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035899455 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1035899455 |
| Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1546125541 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 221220602 ps |
| CPU time | 5.18 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:31:44 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-30ef7446-abef-4aa1-adb7-9e926afbcc58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546125541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.1546125541 |
| Directory | /workspace/12.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1981582596 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 174741809 ps |
| CPU time | 1.37 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:31:39 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-b502b34b-c7d3-4c9e-99da-c56ee70c3ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981582596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.1981582596 |
| Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4194553641 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 46962231 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:31:35 PM PST 24 |
| Finished | Feb 21 12:31:36 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-33897cdf-6ead-4e50-ad46-ab282229efef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194553641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.4194553641 |
| Directory | /workspace/13.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3627452216 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 14023068 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:31:39 PM PST 24 |
| Peak memory | 201652 kb |
| Host | smart-e994180e-0e3d-4566-b543-e8127a8c4811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627452216 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3627452216 |
| Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2565589289 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 38843281 ps |
| CPU time | 2.94 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:31:41 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-21881b9f-a563-49f7-a3f1-8b3e15c24138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565589289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.2565589289 |
| Directory | /workspace/13.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.66146987 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 208954655 ps |
| CPU time | 2.55 seconds |
| Started | Feb 21 12:31:40 PM PST 24 |
| Finished | Feb 21 12:31:43 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-a238b3a1-6e14-4832-b7fc-34c667882acd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66146987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 13.sram_ctrl_tl_intg_err.66146987 |
| Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1833481459 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 34183222 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:31:38 PM PST 24 |
| Peak memory | 200728 kb |
| Host | smart-5bd7252f-11ad-47eb-96f7-898022fa19b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833481459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.1833481459 |
| Directory | /workspace/14.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3636821211 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 7280167520 ps |
| CPU time | 119.36 seconds |
| Started | Feb 21 12:31:35 PM PST 24 |
| Finished | Feb 21 12:33:35 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-c446eae9-f88a-465f-becb-7b1651469999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636821211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3636821211 |
| Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1805707376 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 20651517 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:31:35 PM PST 24 |
| Finished | Feb 21 12:31:36 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-1c1a0794-cfef-45b5-a0b9-5d02216d351a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805707376 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1805707376 |
| Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3053108829 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 218116977 ps |
| CPU time | 2.22 seconds |
| Started | Feb 21 12:31:42 PM PST 24 |
| Finished | Feb 21 12:31:44 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-56a9ff24-9bd2-48d8-b3c4-389708947e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053108829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3053108829 |
| Directory | /workspace/14.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1397475929 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 179585585 ps |
| CPU time | 1.36 seconds |
| Started | Feb 21 12:31:41 PM PST 24 |
| Finished | Feb 21 12:31:42 PM PST 24 |
| Peak memory | 201732 kb |
| Host | smart-684d3318-9d1e-4762-80a5-ba0330641cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397475929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1397475929 |
| Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2405463561 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 51003801 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:31:34 PM PST 24 |
| Finished | Feb 21 12:31:35 PM PST 24 |
| Peak memory | 202128 kb |
| Host | smart-67c9822d-40ef-49c9-bf10-cc11fe22c6ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405463561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.2405463561 |
| Directory | /workspace/15.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.86470448 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7279240759 ps |
| CPU time | 113.61 seconds |
| Started | Feb 21 12:31:40 PM PST 24 |
| Finished | Feb 21 12:33:34 PM PST 24 |
| Peak memory | 219040 kb |
| Host | smart-3424da0c-8877-46a3-ab9d-42b96090b5dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86470448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.86470448 |
| Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3043352531 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 72415546 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:31:39 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-bc00e493-84df-41c4-8567-a5849146ef4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043352531 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3043352531 |
| Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3508224260 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 58399343 ps |
| CPU time | 2.62 seconds |
| Started | Feb 21 12:31:42 PM PST 24 |
| Finished | Feb 21 12:31:45 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-10a9cda7-c286-4b44-957e-3f5a7c0fa239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508224260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3508224260 |
| Directory | /workspace/15.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4096834043 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 26883213 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:31:39 PM PST 24 |
| Finished | Feb 21 12:31:40 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-52dddf3b-042b-4f2b-9b7d-8db7e5667967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096834043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.4096834043 |
| Directory | /workspace/16.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2452934405 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 15412693193 ps |
| CPU time | 52.63 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:32:31 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-0e94a5e7-07f6-4805-aadb-6b86a0ef3811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452934405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2452934405 |
| Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.721484833 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 17377522 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:31:38 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-b2765e2f-be24-49fb-aaa3-e66b4ab0ca79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721484833 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.721484833 |
| Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.327904590 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 30304248 ps |
| CPU time | 1.94 seconds |
| Started | Feb 21 12:31:34 PM PST 24 |
| Finished | Feb 21 12:31:36 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-7a443004-298a-4dd6-afd5-625a99948e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327904590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.327904590 |
| Directory | /workspace/16.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1901220116 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 269000065 ps |
| CPU time | 1.32 seconds |
| Started | Feb 21 12:31:36 PM PST 24 |
| Finished | Feb 21 12:31:38 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-60430441-9af1-4ca1-b28f-8c116bfdc66f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901220116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.1901220116 |
| Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.325098490 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 50177796 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:31:33 PM PST 24 |
| Finished | Feb 21 12:31:34 PM PST 24 |
| Peak memory | 201808 kb |
| Host | smart-76fb9314-cc12-419f-878d-9fae2806d337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325098490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.325098490 |
| Directory | /workspace/17.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.190628478 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 16818157011 ps |
| CPU time | 136.11 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:33:55 PM PST 24 |
| Peak memory | 202824 kb |
| Host | smart-bc033fb3-70de-4757-b210-7ac76df0fbb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190628478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.190628478 |
| Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.70428249 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 26735225 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:31:34 PM PST 24 |
| Finished | Feb 21 12:31:35 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-fe9b10d6-4a81-4636-ad44-84c880b30bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70428249 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.70428249 |
| Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1888267675 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 110377611 ps |
| CPU time | 3.37 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:31:42 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-8da98de2-dd9a-42be-b154-350b9afebcf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888267675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.1888267675 |
| Directory | /workspace/17.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4062885394 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 403090134 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:31:41 PM PST 24 |
| Peak memory | 202140 kb |
| Host | smart-2eb685f2-1904-44b9-8efe-053217a3fb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062885394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.4062885394 |
| Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1059257418 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 14682732 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:31:39 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-30e87c66-6d13-4087-bf7d-6b11a0149205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059257418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.1059257418 |
| Directory | /workspace/18.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1045106814 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 3872191550 ps |
| CPU time | 129.53 seconds |
| Started | Feb 21 12:31:36 PM PST 24 |
| Finished | Feb 21 12:33:46 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-71a99ace-dd2e-41ac-8d87-be1e05050f96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045106814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1045106814 |
| Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3773230463 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 29342640 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 12:31:37 PM PST 24 |
| Finished | Feb 21 12:31:39 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-82bb8a9a-c81c-4ae7-89d0-e6fd250217b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773230463 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3773230463 |
| Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4185035016 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 43739488 ps |
| CPU time | 2.24 seconds |
| Started | Feb 21 12:31:38 PM PST 24 |
| Finished | Feb 21 12:31:40 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-19a827c4-67cd-4f39-8ba7-5271336e23f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185035016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.4185035016 |
| Directory | /workspace/18.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.205365805 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 30422839 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:32:08 PM PST 24 |
| Finished | Feb 21 12:32:09 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-ab669e8d-8cde-400a-beb8-88a9207ba12d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205365805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.205365805 |
| Directory | /workspace/19.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3901709950 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 29358177882 ps |
| CPU time | 265.92 seconds |
| Started | Feb 21 12:31:34 PM PST 24 |
| Finished | Feb 21 12:36:01 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-24913aee-4748-484c-bb7d-0b3e46d72b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901709950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3901709950 |
| Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.701992743 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 12809118 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:31:54 PM PST 24 |
| Finished | Feb 21 12:31:55 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-18170ea3-4e2b-4043-bae1-004f5a3f57f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701992743 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.701992743 |
| Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1983302731 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 189886607 ps |
| CPU time | 2.29 seconds |
| Started | Feb 21 12:31:39 PM PST 24 |
| Finished | Feb 21 12:31:42 PM PST 24 |
| Peak memory | 202856 kb |
| Host | smart-db7fba34-b5ef-4d5d-b5b8-12cec9ecc279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983302731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1983302731 |
| Directory | /workspace/19.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2784161550 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 15817447 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:31:09 PM PST 24 |
| Finished | Feb 21 12:31:11 PM PST 24 |
| Peak memory | 202084 kb |
| Host | smart-f5676fb0-a566-4a54-a755-52fdab452494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784161550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.2784161550 |
| Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1943131797 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 806079151 ps |
| CPU time | 2.3 seconds |
| Started | Feb 21 12:31:13 PM PST 24 |
| Finished | Feb 21 12:31:16 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-639d3801-f559-461e-abfe-a8214efa1b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943131797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.1943131797 |
| Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.468018672 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 35296477 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:31:22 PM PST 24 |
| Finished | Feb 21 12:31:23 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-6875fd19-4de2-48b7-9d01-8f19e3368bca |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468018672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.468018672 |
| Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.910810069 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 28896429 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:31:09 PM PST 24 |
| Finished | Feb 21 12:31:11 PM PST 24 |
| Peak memory | 202096 kb |
| Host | smart-022da3c9-9564-488e-bcd6-7f10da055c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910810069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_csr_rw.910810069 |
| Directory | /workspace/2.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3422234645 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 10533151109 ps |
| CPU time | 114.01 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:33:14 PM PST 24 |
| Peak memory | 201936 kb |
| Host | smart-2693908a-3290-441d-8ff2-17e42ae978c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422234645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3422234645 |
| Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1916971579 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 149484802 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:31:27 PM PST 24 |
| Finished | Feb 21 12:31:28 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-28061eef-f1cc-410f-a875-225750e9c283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916971579 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1916971579 |
| Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2986115418 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 118723011 ps |
| CPU time | 1.8 seconds |
| Started | Feb 21 12:31:11 PM PST 24 |
| Finished | Feb 21 12:31:13 PM PST 24 |
| Peak memory | 202040 kb |
| Host | smart-21925190-5b8c-4fb1-b49a-6f1d9f06b8df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986115418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2986115418 |
| Directory | /workspace/2.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3788230625 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 181898353 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 12:31:18 PM PST 24 |
| Finished | Feb 21 12:31:20 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-2eb0729e-d8f2-41af-8cd3-2b9cac36332f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788230625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.3788230625 |
| Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1895741733 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 22722598 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:31:12 PM PST 24 |
| Finished | Feb 21 12:31:13 PM PST 24 |
| Peak memory | 202108 kb |
| Host | smart-6ddc2ea0-5d63-495f-8f33-68990f285feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895741733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.1895741733 |
| Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2967036564 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 34613740 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:31:21 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-5f290e1e-4591-42d2-a7a7-81ce8a4de0a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967036564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.2967036564 |
| Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.742332380 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 20181616 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:31:21 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-dcf3e559-b317-4e63-8a9f-ed9c059a4cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742332380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.742332380 |
| Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.849977817 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 18758427 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:31:10 PM PST 24 |
| Finished | Feb 21 12:31:12 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-8610fdb6-63dc-417d-a758-424ec03e1c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849977817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_csr_rw.849977817 |
| Directory | /workspace/3.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2228447780 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 15089830876 ps |
| CPU time | 48.6 seconds |
| Started | Feb 21 12:31:13 PM PST 24 |
| Finished | Feb 21 12:32:02 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-f2521043-370a-47f8-9758-de670ebcba35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228447780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2228447780 |
| Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2552366816 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 20913275 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:31:18 PM PST 24 |
| Finished | Feb 21 12:31:19 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-976ce66e-5854-4138-bfb7-371578aea37c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552366816 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2552366816 |
| Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1413648503 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 84742738 ps |
| CPU time | 2.62 seconds |
| Started | Feb 21 12:31:16 PM PST 24 |
| Finished | Feb 21 12:31:19 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-1405e87a-1e07-4549-9146-1f7a1ad9898d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413648503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.1413648503 |
| Directory | /workspace/3.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3838035501 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 533120180 ps |
| CPU time | 3.06 seconds |
| Started | Feb 21 12:32:17 PM PST 24 |
| Finished | Feb 21 12:32:22 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-669388e6-a8e3-49a4-9c36-d2b1bf723d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838035501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.3838035501 |
| Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4161786659 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 71043632 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:31:21 PM PST 24 |
| Finished | Feb 21 12:31:22 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-2dbe3a3d-7ad9-454d-878f-afa4ad2718c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161786659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.4161786659 |
| Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3686270056 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 666264264 ps |
| CPU time | 2.24 seconds |
| Started | Feb 21 12:31:24 PM PST 24 |
| Finished | Feb 21 12:31:28 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-9895466d-25f7-4fa2-8db7-78b275d4a720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686270056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.3686270056 |
| Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1502757707 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 26659471 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:31:21 PM PST 24 |
| Finished | Feb 21 12:31:22 PM PST 24 |
| Peak memory | 202132 kb |
| Host | smart-d7243059-e3eb-4629-8039-78ea433ef924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502757707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1502757707 |
| Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.673818967 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 25583871 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:31:22 PM PST 24 |
| Finished | Feb 21 12:31:23 PM PST 24 |
| Peak memory | 201604 kb |
| Host | smart-0d47cda8-8d17-44f0-b791-25044cb8c736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673818967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_csr_rw.673818967 |
| Directory | /workspace/4.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2767605381 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 7367112950 ps |
| CPU time | 122.29 seconds |
| Started | Feb 21 12:31:18 PM PST 24 |
| Finished | Feb 21 12:33:21 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-2229fb36-28fd-4da3-b526-9903d0ca9c19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767605381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2767605381 |
| Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2629132567 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 50280883 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:31:24 PM PST 24 |
| Finished | Feb 21 12:31:26 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-bb211e8b-3fc3-4d1b-857b-abf59ac2c45c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629132567 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2629132567 |
| Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2005309321 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 141086481 ps |
| CPU time | 4.22 seconds |
| Started | Feb 21 12:31:23 PM PST 24 |
| Finished | Feb 21 12:31:29 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-8caa830d-4e5e-4d0c-8e89-0fc48e3a3109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005309321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.2005309321 |
| Directory | /workspace/4.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2655187845 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1298779762 ps |
| CPU time | 2.72 seconds |
| Started | Feb 21 12:31:27 PM PST 24 |
| Finished | Feb 21 12:31:30 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-876e2ca9-8921-4feb-aa81-66088dc20ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655187845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2655187845 |
| Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3097325525 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 44331856 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:31:21 PM PST 24 |
| Finished | Feb 21 12:31:22 PM PST 24 |
| Peak memory | 201988 kb |
| Host | smart-4613cd43-857d-445c-980a-021efd3f1a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097325525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3097325525 |
| Directory | /workspace/5.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.681512285 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 7364575745 ps |
| CPU time | 94.61 seconds |
| Started | Feb 21 12:32:33 PM PST 24 |
| Finished | Feb 21 12:34:10 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-ad5f3ecb-b0ca-4874-891d-c0ff9a901898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681512285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.681512285 |
| Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.229883400 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 21104351 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:31:23 PM PST 24 |
| Finished | Feb 21 12:31:25 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-a413f301-ac5c-4d43-8afc-91ddacb53088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229883400 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.229883400 |
| Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3745132111 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 45352237 ps |
| CPU time | 2.45 seconds |
| Started | Feb 21 12:31:16 PM PST 24 |
| Finished | Feb 21 12:31:19 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-4b71b7f7-0e59-46e9-8790-72fa91c54315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745132111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.3745132111 |
| Directory | /workspace/5.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.939149824 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 90055721 ps |
| CPU time | 1.53 seconds |
| Started | Feb 21 12:31:32 PM PST 24 |
| Finished | Feb 21 12:31:34 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-663a0ec9-6b47-4885-8124-5d7316e89864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939149824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.939149824 |
| Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1491684494 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 11397395 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:31:21 PM PST 24 |
| Peak memory | 202080 kb |
| Host | smart-f0825b7e-2186-445b-a0a4-6c098cfda2f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491684494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.1491684494 |
| Directory | /workspace/6.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.488159917 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 13643724087 ps |
| CPU time | 141.7 seconds |
| Started | Feb 21 12:31:23 PM PST 24 |
| Finished | Feb 21 12:33:46 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-759c59b4-bfd4-4a5c-886a-8d83582a96f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488159917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.488159917 |
| Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1365468127 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 17361417 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:31:29 PM PST 24 |
| Finished | Feb 21 12:31:30 PM PST 24 |
| Peak memory | 201928 kb |
| Host | smart-8a510021-4e4e-4a5e-a0b5-36be47380ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365468127 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1365468127 |
| Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.675249169 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 73151602 ps |
| CPU time | 3.25 seconds |
| Started | Feb 21 12:31:22 PM PST 24 |
| Finished | Feb 21 12:31:26 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-a7347d8d-8b12-4eca-909b-ff79d10bc1fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675249169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.675249169 |
| Directory | /workspace/6.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.786057599 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 57720758 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:32:37 PM PST 24 |
| Finished | Feb 21 12:32:38 PM PST 24 |
| Peak memory | 202112 kb |
| Host | smart-4222a715-bff7-4f5c-9933-4afb246f3252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786057599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.786057599 |
| Directory | /workspace/7.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3500544653 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 14119684425 ps |
| CPU time | 118.82 seconds |
| Started | Feb 21 12:31:19 PM PST 24 |
| Finished | Feb 21 12:33:18 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-56fed6d0-5a3f-4b9d-9301-87ccebfae99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500544653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3500544653 |
| Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.927282460 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 58444639 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:31:21 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-6d297331-d587-4f62-a7c2-8d866267bc16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927282460 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.927282460 |
| Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1405439077 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 108141982 ps |
| CPU time | 2.4 seconds |
| Started | Feb 21 12:31:28 PM PST 24 |
| Finished | Feb 21 12:31:31 PM PST 24 |
| Peak memory | 202020 kb |
| Host | smart-c71a033a-34a2-4962-a0c9-251335699323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405439077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.1405439077 |
| Directory | /workspace/7.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2334206032 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 148129632 ps |
| CPU time | 1.5 seconds |
| Started | Feb 21 12:31:17 PM PST 24 |
| Finished | Feb 21 12:31:19 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-bbe0da8b-cefa-4573-959d-9085f686edde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334206032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2334206032 |
| Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.401919645 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 105576419 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:31:25 PM PST 24 |
| Finished | Feb 21 12:31:26 PM PST 24 |
| Peak memory | 202120 kb |
| Host | smart-6cdd7846-bdcc-41a5-a5c9-fea73e61b725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401919645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_csr_rw.401919645 |
| Directory | /workspace/8.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3046585509 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3930550870 ps |
| CPU time | 57.6 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:32:17 PM PST 24 |
| Peak memory | 210916 kb |
| Host | smart-69b88b44-356f-4b18-9a77-373d603bb014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046585509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3046585509 |
| Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3182556861 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 37952632 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:31:19 PM PST 24 |
| Finished | Feb 21 12:31:20 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-5a7a0f94-b1cf-4349-b07c-1abd7ef9010a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182556861 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3182556861 |
| Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3165715929 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 220810901 ps |
| CPU time | 2.08 seconds |
| Started | Feb 21 12:31:20 PM PST 24 |
| Finished | Feb 21 12:31:22 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-9f19754b-d0ec-4c4d-811b-eb22e96b5719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165715929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.3165715929 |
| Directory | /workspace/8.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2029825506 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 95597722 ps |
| CPU time | 1.53 seconds |
| Started | Feb 21 12:31:23 PM PST 24 |
| Finished | Feb 21 12:31:26 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-249942f0-5c7a-4932-ae6a-156579503c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029825506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2029825506 |
| Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1947188281 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 37446173 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:31:33 PM PST 24 |
| Finished | Feb 21 12:31:34 PM PST 24 |
| Peak memory | 202140 kb |
| Host | smart-a9bdcbde-313f-42bf-9285-8710ab82774c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947188281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1947188281 |
| Directory | /workspace/9.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1881744361 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 7665980765 ps |
| CPU time | 263.82 seconds |
| Started | Feb 21 12:32:37 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-c1d1be33-d853-42f1-8dd1-0e0484b7fd14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881744361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1881744361 |
| Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3746616950 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 31745980 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:31:22 PM PST 24 |
| Finished | Feb 21 12:31:24 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-0b82687b-bfd1-4998-bf9d-e7d8fe0c1cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746616950 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3746616950 |
| Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2943266681 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 23086279 ps |
| CPU time | 1.81 seconds |
| Started | Feb 21 12:31:21 PM PST 24 |
| Finished | Feb 21 12:31:23 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-eb425b3e-7b25-4b17-9db5-bf1bf4b8c61f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943266681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.2943266681 |
| Directory | /workspace/9.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.985120139 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 210457943 ps |
| CPU time | 2.31 seconds |
| Started | Feb 21 12:31:18 PM PST 24 |
| Finished | Feb 21 12:31:21 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-a243dec5-c10a-4d11-b82d-90f6f9874d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985120139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.sram_ctrl_tl_intg_err.985120139 |
| Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3137185574 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2464956828 ps |
| CPU time | 299.97 seconds |
| Started | Feb 21 12:56:11 PM PST 24 |
| Finished | Feb 21 01:01:12 PM PST 24 |
| Peak memory | 378120 kb |
| Host | smart-9bbe97b0-3732-415c-a48c-e3b65a6f6cbf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137185574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3137185574 |
| Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.2342954613 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 25212116 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:56:27 PM PST 24 |
| Finished | Feb 21 12:56:28 PM PST 24 |
| Peak memory | 201948 kb |
| Host | smart-2fcd2736-6b0c-4057-bc1d-2c2305813d6c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342954613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.2342954613 |
| Directory | /workspace/0.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_bijection.3858416760 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 30539611470 ps |
| CPU time | 2137.98 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 01:31:59 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-d8cc71a9-b976-40a3-b1f0-65246eab87b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858416760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 3858416760 |
| Directory | /workspace/0.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_executable.2396866311 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 10751606659 ps |
| CPU time | 537.46 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 01:05:19 PM PST 24 |
| Peak memory | 356800 kb |
| Host | smart-4148f73d-0460-4080-8f42-15b3ccfd0cb1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396866311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.2396866311 |
| Directory | /workspace/0.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.4260799248 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 12773999962 ps |
| CPU time | 76.37 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 12:57:37 PM PST 24 |
| Peak memory | 210656 kb |
| Host | smart-43d28aa0-4b55-440a-b774-14625340b381 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260799248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.4260799248 |
| Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.4083913255 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 15138567067 ps |
| CPU time | 154.49 seconds |
| Started | Feb 21 12:56:11 PM PST 24 |
| Finished | Feb 21 12:58:46 PM PST 24 |
| Peak memory | 358860 kb |
| Host | smart-172803f2-b328-4da4-96d6-ad138f65a2d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083913255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.4083913255 |
| Directory | /workspace/0.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2860555533 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1970143774 ps |
| CPU time | 71.09 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 12:57:30 PM PST 24 |
| Peak memory | 211360 kb |
| Host | smart-d73f709d-9715-440e-b3ed-cc50137e007e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860555533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.2860555533 |
| Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.1249497728 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 41344245148 ps |
| CPU time | 311.53 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 01:01:32 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-25a69a49-72d3-4320-811f-144be3a0c369 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249497728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.1249497728 |
| Directory | /workspace/0.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.1219103028 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 63288150591 ps |
| CPU time | 1160.56 seconds |
| Started | Feb 21 12:56:20 PM PST 24 |
| Finished | Feb 21 01:15:44 PM PST 24 |
| Peak memory | 377300 kb |
| Host | smart-7b5b86ba-f15a-4dff-9c65-5f7689fb55b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219103028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.1219103028 |
| Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.625964763 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 962207553 ps |
| CPU time | 40.03 seconds |
| Started | Feb 21 12:56:20 PM PST 24 |
| Finished | Feb 21 12:57:03 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-77f16a7d-ba47-4f5a-84bc-fa5b978c5543 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625964763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr am_ctrl_partial_access.625964763 |
| Directory | /workspace/0.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3856370474 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 6930206251 ps |
| CPU time | 442.83 seconds |
| Started | Feb 21 12:56:20 PM PST 24 |
| Finished | Feb 21 01:03:46 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-d37ebed8-df10-49a1-8779-0ead3da13635 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856370474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.3856370474 |
| Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.3973669978 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1355985288 ps |
| CPU time | 6.67 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 12:56:29 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-4135dd6d-1d57-4104-9bb7-67729754c20b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973669978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3973669978 |
| Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_regwen.3765812677 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 57076875849 ps |
| CPU time | 661.09 seconds |
| Started | Feb 21 12:56:18 PM PST 24 |
| Finished | Feb 21 01:07:19 PM PST 24 |
| Peak memory | 379300 kb |
| Host | smart-e8e727bc-651e-42df-a035-043888373ca7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765812677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3765812677 |
| Directory | /workspace/0.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_smoke.1747332600 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 12002702490 ps |
| CPU time | 34.31 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 12:56:55 PM PST 24 |
| Peak memory | 289560 kb |
| Host | smart-db7b9206-04c2-4c6d-b572-0dda08d32d46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747332600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1747332600 |
| Directory | /workspace/0.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2343584168 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 7016862481 ps |
| CPU time | 288.37 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 01:01:10 PM PST 24 |
| Peak memory | 210624 kb |
| Host | smart-3c477f4d-2dcb-4919-babe-177ab170049f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343584168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.2343584168 |
| Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4038132432 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3016747218 ps |
| CPU time | 51.79 seconds |
| Started | Feb 21 12:56:12 PM PST 24 |
| Finished | Feb 21 12:57:05 PM PST 24 |
| Peak memory | 284092 kb |
| Host | smart-5f9174e0-0486-4323-ad3f-d2a8b96105f8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038132432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.4038132432 |
| Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3780792033 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 23995842068 ps |
| CPU time | 739.66 seconds |
| Started | Feb 21 12:56:16 PM PST 24 |
| Finished | Feb 21 01:08:36 PM PST 24 |
| Peak memory | 377224 kb |
| Host | smart-b7d18f25-b21b-4305-9a26-df61b8589f9d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780792033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.3780792033 |
| Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.447209540 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 15802762 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:56:28 PM PST 24 |
| Finished | Feb 21 12:56:29 PM PST 24 |
| Peak memory | 201948 kb |
| Host | smart-f5b19575-ac7e-45be-b376-f0bf8ce93166 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447209540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.447209540 |
| Directory | /workspace/1.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_bijection.104256379 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 424298824070 ps |
| CPU time | 2043.06 seconds |
| Started | Feb 21 12:56:14 PM PST 24 |
| Finished | Feb 21 01:30:17 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-0736dbc6-02f7-4093-91e5-b5cb27a02449 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104256379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.104256379 |
| Directory | /workspace/1.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_executable.306701549 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4673653426 ps |
| CPU time | 117.08 seconds |
| Started | Feb 21 12:56:27 PM PST 24 |
| Finished | Feb 21 12:58:25 PM PST 24 |
| Peak memory | 324832 kb |
| Host | smart-695245c5-b09a-4666-8d8d-ede334deabc5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306701549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable .306701549 |
| Directory | /workspace/1.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1338885122 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 686050996 ps |
| CPU time | 30.31 seconds |
| Started | Feb 21 12:56:19 PM PST 24 |
| Finished | Feb 21 12:56:50 PM PST 24 |
| Peak memory | 224620 kb |
| Host | smart-df893fb8-911e-4a0a-860c-496965e529f4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338885122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1338885122 |
| Directory | /workspace/1.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1933833769 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1639462771 ps |
| CPU time | 128.84 seconds |
| Started | Feb 21 12:56:15 PM PST 24 |
| Finished | Feb 21 12:58:24 PM PST 24 |
| Peak memory | 218696 kb |
| Host | smart-231ac333-6706-4dad-82a9-63a4d3d032f9 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933833769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.1933833769 |
| Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.180704099 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 44743441448 ps |
| CPU time | 155.74 seconds |
| Started | Feb 21 12:56:26 PM PST 24 |
| Finished | Feb 21 12:59:03 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-c95200bd-7830-48f1-bdb1-55284a1195f6 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180704099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.180704099 |
| Directory | /workspace/1.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.991391323 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 44572606878 ps |
| CPU time | 885.58 seconds |
| Started | Feb 21 12:56:28 PM PST 24 |
| Finished | Feb 21 01:11:14 PM PST 24 |
| Peak memory | 378516 kb |
| Host | smart-58678a58-cdaa-4f44-80e5-771f6a9295d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991391323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multipl e_keys.991391323 |
| Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.66456459 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5126923593 ps |
| CPU time | 24.55 seconds |
| Started | Feb 21 12:56:16 PM PST 24 |
| Finished | Feb 21 12:56:41 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-bd5b8f15-422e-4a5a-b1d5-f8651c303a72 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66456459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sra m_ctrl_partial_access.66456459 |
| Directory | /workspace/1.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2868904653 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 10668881072 ps |
| CPU time | 242.43 seconds |
| Started | Feb 21 12:56:16 PM PST 24 |
| Finished | Feb 21 01:00:19 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-8c6b5583-aba4-478c-a0dc-79091b2fbb6d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868904653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.2868904653 |
| Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.3390584897 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 378801222 ps |
| CPU time | 5.8 seconds |
| Started | Feb 21 12:56:14 PM PST 24 |
| Finished | Feb 21 12:56:21 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-0234106e-50f0-4a10-811c-384300450ce3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390584897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3390584897 |
| Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_regwen.2582797377 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 51702269973 ps |
| CPU time | 652.58 seconds |
| Started | Feb 21 12:56:16 PM PST 24 |
| Finished | Feb 21 01:07:09 PM PST 24 |
| Peak memory | 378352 kb |
| Host | smart-99640c39-bb43-477a-a23b-d46b69ec908a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582797377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2582797377 |
| Directory | /workspace/1.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.2003984484 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 537541237 ps |
| CPU time | 3.1 seconds |
| Started | Feb 21 12:56:27 PM PST 24 |
| Finished | Feb 21 12:56:30 PM PST 24 |
| Peak memory | 220988 kb |
| Host | smart-f9eb3389-4b3f-4793-84ac-46dab662bd20 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003984484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2003984484 |
| Directory | /workspace/1.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_smoke.937151156 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1630591753 ps |
| CPU time | 34.24 seconds |
| Started | Feb 21 12:56:16 PM PST 24 |
| Finished | Feb 21 12:56:51 PM PST 24 |
| Peak memory | 202308 kb |
| Host | smart-b70d69a9-7f2f-4771-8de2-83c92cf0efdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937151156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.937151156 |
| Directory | /workspace/1.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.973668262 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 17701605702 ps |
| CPU time | 327.49 seconds |
| Started | Feb 21 12:56:14 PM PST 24 |
| Finished | Feb 21 01:01:42 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-67e83d80-80d0-47c2-82d1-9875474fe71f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973668262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_stress_pipeline.973668262 |
| Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.263384907 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 779060955 ps |
| CPU time | 64.31 seconds |
| Started | Feb 21 12:56:16 PM PST 24 |
| Finished | Feb 21 12:57:21 PM PST 24 |
| Peak memory | 313748 kb |
| Host | smart-3d1abbf9-51b9-4d03-91f5-da81f9991f72 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263384907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.263384907 |
| Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.415184184 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 15401861670 ps |
| CPU time | 1146.23 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 01:16:05 PM PST 24 |
| Peak memory | 377244 kb |
| Host | smart-f1859138-f4ea-4888-9a33-17fc89d6f6c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415184184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_access_during_key_req.415184184 |
| Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.3498184181 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 12615926 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:57:05 PM PST 24 |
| Peak memory | 201948 kb |
| Host | smart-07b9d4d8-40d6-4153-afca-38feff6cc34f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498184181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3498184181 |
| Directory | /workspace/10.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_bijection.558372797 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 16935112602 ps |
| CPU time | 1080.17 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 01:15:06 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-bff636e8-247a-4587-b4b5-f19138cb576a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558372797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 558372797 |
| Directory | /workspace/10.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_executable.927601262 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 28388055901 ps |
| CPU time | 1095.47 seconds |
| Started | Feb 21 12:57:13 PM PST 24 |
| Finished | Feb 21 01:15:29 PM PST 24 |
| Peak memory | 377004 kb |
| Host | smart-a0b13c6e-f24a-452d-97ed-dc71eab25b4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927601262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl e.927601262 |
| Directory | /workspace/10.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.1143365178 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 9166752053 ps |
| CPU time | 88.08 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:58:33 PM PST 24 |
| Peak memory | 210628 kb |
| Host | smart-8644844e-fc9d-49db-9579-4ffe5ca330b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143365178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1143365178 |
| Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.608583522 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1534326947 ps |
| CPU time | 142.46 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 12:59:28 PM PST 24 |
| Peak memory | 365040 kb |
| Host | smart-1347ea2b-2627-4beb-a09b-9b9e9ca353ab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608583522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.sram_ctrl_max_throughput.608583522 |
| Directory | /workspace/10.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3797343067 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 11751141839 ps |
| CPU time | 76.3 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:58:21 PM PST 24 |
| Peak memory | 218820 kb |
| Host | smart-ff88bfa0-6634-41d5-a86e-b1071896291c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797343067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.3797343067 |
| Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.1067730940 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4116218834 ps |
| CPU time | 117.78 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 12:59:00 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-7eacabd7-4813-4397-b5d6-eae6d09bd2c5 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067730940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.1067730940 |
| Directory | /workspace/10.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.2903109980 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 11691259627 ps |
| CPU time | 1094.3 seconds |
| Started | Feb 21 12:57:03 PM PST 24 |
| Finished | Feb 21 01:15:18 PM PST 24 |
| Peak memory | 357860 kb |
| Host | smart-a8fb079e-0fbe-4a1c-9a30-731177c408e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903109980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2903109980 |
| Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.513023445 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 6945433132 ps |
| CPU time | 36.06 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:57:41 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-90003066-fe26-4338-8204-8f730c39ef3b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513023445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.s ram_ctrl_partial_access.513023445 |
| Directory | /workspace/10.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.401563434 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 26185376067 ps |
| CPU time | 308.74 seconds |
| Started | Feb 21 12:57:01 PM PST 24 |
| Finished | Feb 21 01:02:10 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-0829774e-54eb-45b4-a09d-e878ae6e5c51 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401563434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.sram_ctrl_partial_access_b2b.401563434 |
| Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_regwen.2003640779 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8548675165 ps |
| CPU time | 420.8 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 01:04:06 PM PST 24 |
| Peak memory | 368300 kb |
| Host | smart-df7ebf8e-6284-4b1d-bf06-0a6d6c7c424c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003640779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2003640779 |
| Directory | /workspace/10.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_smoke.3225504344 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 1316576336 ps |
| CPU time | 86.42 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 12:58:28 PM PST 24 |
| Peak memory | 351460 kb |
| Host | smart-ad5c15ea-01a7-4ce6-b498-6cae25cc3228 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225504344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3225504344 |
| Directory | /workspace/10.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2147645231 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 10108818292 ps |
| CPU time | 205.69 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 01:00:30 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-92c6ec87-c575-4706-934c-58d4341f8dc4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147645231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.2147645231 |
| Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3461702260 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 784287250 ps |
| CPU time | 54.29 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 12:57:57 PM PST 24 |
| Peak memory | 293112 kb |
| Host | smart-e2894dad-bed2-4330-9b11-626514e7a71d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461702260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3461702260 |
| Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.169671943 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 15599267604 ps |
| CPU time | 1008.41 seconds |
| Started | Feb 21 12:57:13 PM PST 24 |
| Finished | Feb 21 01:14:02 PM PST 24 |
| Peak memory | 375052 kb |
| Host | smart-3de862ce-5d9b-42b8-8d5d-a5dc55744307 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169671943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_access_during_key_req.169671943 |
| Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.2181454416 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 19347287 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:57:19 PM PST 24 |
| Finished | Feb 21 12:57:20 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-cd8a1f57-e606-430e-8a72-3ec24c23694f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181454416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2181454416 |
| Directory | /workspace/11.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_bijection.1313616792 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 979442488753 ps |
| CPU time | 1775.7 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 01:26:38 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-c3faed32-50df-44a1-a646-ed815ab424aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313616792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .1313616792 |
| Directory | /workspace/11.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_executable.55340231 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 63327475993 ps |
| CPU time | 527.7 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 01:05:52 PM PST 24 |
| Peak memory | 376228 kb |
| Host | smart-be351e02-0734-4857-8135-b5c4a9567ddc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55340231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable .55340231 |
| Directory | /workspace/11.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.1928770419 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 12443380821 ps |
| CPU time | 119.63 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:59:04 PM PST 24 |
| Peak memory | 212000 kb |
| Host | smart-14e84164-0b2d-4c6a-9186-c39fb59e395a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928770419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1928770419 |
| Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.2928462639 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1361994949 ps |
| CPU time | 38.74 seconds |
| Started | Feb 21 12:57:13 PM PST 24 |
| Finished | Feb 21 12:57:52 PM PST 24 |
| Peak memory | 267780 kb |
| Host | smart-189901c2-a59d-4cad-bcad-94198affd1c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928462639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.2928462639 |
| Directory | /workspace/11.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.450016002 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 48257220834 ps |
| CPU time | 142.29 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 12:59:33 PM PST 24 |
| Peak memory | 218704 kb |
| Host | smart-0960f0f6-8ca1-449e-82d2-fec371cd9dac |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450016002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_mem_partial_access.450016002 |
| Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.3335883939 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 13794980792 ps |
| CPU time | 266.81 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 01:01:34 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-c4864e74-2f63-4d2d-a58f-fb3c5e95d4cd |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335883939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.3335883939 |
| Directory | /workspace/11.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.3456637421 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 30574187647 ps |
| CPU time | 761.16 seconds |
| Started | Feb 21 12:56:59 PM PST 24 |
| Finished | Feb 21 01:09:41 PM PST 24 |
| Peak memory | 360968 kb |
| Host | smart-c7178553-d9ef-4532-ad5f-6a0818768ac3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456637421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3456637421 |
| Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.2257441999 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1994268364 ps |
| CPU time | 22.59 seconds |
| Started | Feb 21 12:57:00 PM PST 24 |
| Finished | Feb 21 12:57:24 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-edc26a09-4bf9-4f10-a32e-8cad2da89657 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257441999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.2257441999 |
| Directory | /workspace/11.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3798856759 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 31642835057 ps |
| CPU time | 396.04 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 01:03:38 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-83a910c0-d863-4e8b-bb48-2c8475b78206 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798856759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3798856759 |
| Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.812456997 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 345933682 ps |
| CPU time | 6.29 seconds |
| Started | Feb 21 12:57:00 PM PST 24 |
| Finished | Feb 21 12:57:08 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-c221b188-429d-41cc-993f-c299447ec3da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812456997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.812456997 |
| Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_regwen.1815013020 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4184657925 ps |
| CPU time | 243.78 seconds |
| Started | Feb 21 12:57:00 PM PST 24 |
| Finished | Feb 21 01:01:05 PM PST 24 |
| Peak memory | 352692 kb |
| Host | smart-ee64ea21-c631-4e29-ae41-0d74af394a98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815013020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1815013020 |
| Directory | /workspace/11.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_smoke.4077735197 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 4511146371 ps |
| CPU time | 12.16 seconds |
| Started | Feb 21 12:57:06 PM PST 24 |
| Finished | Feb 21 12:57:19 PM PST 24 |
| Peak memory | 210612 kb |
| Host | smart-6db6fdbd-27dd-4e59-9d0b-d8818fff4b09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077735197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.4077735197 |
| Directory | /workspace/11.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.3490771886 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 146702911392 ps |
| CPU time | 5857.82 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 02:34:50 PM PST 24 |
| Peak memory | 380380 kb |
| Host | smart-6f171c7e-fbda-4332-b386-e63bace58006 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490771886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.3490771886 |
| Directory | /workspace/11.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2895517453 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 110379779554 ps |
| CPU time | 512.33 seconds |
| Started | Feb 21 12:57:01 PM PST 24 |
| Finished | Feb 21 01:05:34 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-0ce41639-2225-4106-88f8-7735edde796c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895517453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.2895517453 |
| Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2035910098 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 730724408 ps |
| CPU time | 47.77 seconds |
| Started | Feb 21 12:57:01 PM PST 24 |
| Finished | Feb 21 12:57:49 PM PST 24 |
| Peak memory | 275036 kb |
| Host | smart-776692ff-10c4-467b-b97b-66641babf3dc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035910098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2035910098 |
| Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2851930483 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4277429666 ps |
| CPU time | 184.24 seconds |
| Started | Feb 21 12:57:18 PM PST 24 |
| Finished | Feb 21 01:00:22 PM PST 24 |
| Peak memory | 313944 kb |
| Host | smart-4d336de5-9ff1-4921-aebd-6625066e2cbe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851930483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.2851930483 |
| Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.725136856 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 101012007 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 12:57:12 PM PST 24 |
| Peak memory | 201976 kb |
| Host | smart-39fc0130-3a91-4920-97ac-a863bcde6ce4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725136856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.725136856 |
| Directory | /workspace/12.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_bijection.3658012949 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 96663739145 ps |
| CPU time | 1555.23 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 01:23:06 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-1284886e-0ecb-4049-af4e-c41f48803391 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658012949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .3658012949 |
| Directory | /workspace/12.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_executable.263089364 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 83094368572 ps |
| CPU time | 841.71 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 01:11:13 PM PST 24 |
| Peak memory | 370992 kb |
| Host | smart-30c36a64-684b-4fbe-8fc3-f21bcf6c51af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263089364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executabl e.263089364 |
| Directory | /workspace/12.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.3827231338 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10380038063 ps |
| CPU time | 37.04 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 12:57:45 PM PST 24 |
| Peak memory | 210588 kb |
| Host | smart-80322ada-cfdd-4b6a-9080-1216d27ba706 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827231338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.3827231338 |
| Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.3256484117 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 760602904 ps |
| CPU time | 27.33 seconds |
| Started | Feb 21 12:57:18 PM PST 24 |
| Finished | Feb 21 12:57:45 PM PST 24 |
| Peak memory | 214536 kb |
| Host | smart-f6fd3dac-8594-4490-a864-0681f786fc69 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256484117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3256484117 |
| Directory | /workspace/12.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3242395150 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 8673511247 ps |
| CPU time | 76.82 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 12:58:28 PM PST 24 |
| Peak memory | 211488 kb |
| Host | smart-a54e9c4b-b325-4c05-90cc-8a252335bf26 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242395150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.3242395150 |
| Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.1817594855 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2084080486 ps |
| CPU time | 126.79 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 12:59:17 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-29fb1ce3-2957-4170-bb76-15e36bea5606 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817594855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1817594855 |
| Directory | /workspace/12.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.307027006 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 28554226977 ps |
| CPU time | 2506.64 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 01:38:59 PM PST 24 |
| Peak memory | 377088 kb |
| Host | smart-5a5032cf-4c9e-44e4-a0c2-3abc9a5ac74b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307027006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multip le_keys.307027006 |
| Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.3534007341 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1419712335 ps |
| CPU time | 13.07 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 12:57:24 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-1b33f7df-5336-4497-b1f5-09db96b4c3a9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534007341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.3534007341 |
| Directory | /workspace/12.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2808193741 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 9766965915 ps |
| CPU time | 213.1 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 01:00:45 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-92c073f4-b514-4ccc-9ed0-a722ff8f57c6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808193741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.2808193741 |
| Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.1467498049 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1342779837 ps |
| CPU time | 14.56 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 12:57:26 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-2ef3c98b-7c65-424a-9e85-80d702c6ad88 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467498049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1467498049 |
| Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_regwen.3597604522 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 19594272501 ps |
| CPU time | 1270.82 seconds |
| Started | Feb 21 12:57:13 PM PST 24 |
| Finished | Feb 21 01:18:24 PM PST 24 |
| Peak memory | 377292 kb |
| Host | smart-e530e798-7b36-453c-9a81-952ee2d4112b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597604522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3597604522 |
| Directory | /workspace/12.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_smoke.3787968046 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 969985648 ps |
| CPU time | 16.58 seconds |
| Started | Feb 21 12:57:09 PM PST 24 |
| Finished | Feb 21 12:57:26 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-ec2534ac-f9b3-4706-bfcd-26952ca04295 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787968046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3787968046 |
| Directory | /workspace/12.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2081231933 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3519154127 ps |
| CPU time | 251.04 seconds |
| Started | Feb 21 12:57:19 PM PST 24 |
| Finished | Feb 21 01:01:30 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-3ac93360-eaf2-4501-ae3a-94a5231a9fc2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081231933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.2081231933 |
| Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1975679496 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2824180908 ps |
| CPU time | 27.39 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 12:57:38 PM PST 24 |
| Peak memory | 218768 kb |
| Host | smart-93178411-9709-4490-9415-694a27d55129 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975679496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1975679496 |
| Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2221495021 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 27456595849 ps |
| CPU time | 832.02 seconds |
| Started | Feb 21 12:57:08 PM PST 24 |
| Finished | Feb 21 01:11:01 PM PST 24 |
| Peak memory | 377324 kb |
| Host | smart-e059c42c-7e4d-4e0e-bc74-9d4ac81f3df1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221495021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.2221495021 |
| Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_bijection.4085418905 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 32800066181 ps |
| CPU time | 581.53 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 01:06:53 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-0ccaf342-f0f9-413c-b9df-4e4c5b674f24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085418905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .4085418905 |
| Directory | /workspace/13.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_executable.2622678305 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3567665558 ps |
| CPU time | 188.82 seconds |
| Started | Feb 21 12:57:19 PM PST 24 |
| Finished | Feb 21 01:00:28 PM PST 24 |
| Peak memory | 342340 kb |
| Host | smart-46e7a10d-a189-4646-a336-161fc66709b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622678305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.2622678305 |
| Directory | /workspace/13.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.2218361027 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 7005015690 ps |
| CPU time | 172.9 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 01:00:04 PM PST 24 |
| Peak memory | 210692 kb |
| Host | smart-71979ec1-654d-4879-96f5-c4ac0f75e4be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218361027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.2218361027 |
| Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.3163280440 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3029327822 ps |
| CPU time | 26.55 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 12:57:37 PM PST 24 |
| Peak memory | 210684 kb |
| Host | smart-9bb65d4b-7fae-49d5-a56f-02839cb82181 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163280440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.3163280440 |
| Directory | /workspace/13.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1447150416 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 17476593165 ps |
| CPU time | 154.75 seconds |
| Started | Feb 21 12:57:08 PM PST 24 |
| Finished | Feb 21 12:59:44 PM PST 24 |
| Peak memory | 211448 kb |
| Host | smart-b10ad2ec-a1c9-4819-a206-869b452d4f31 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447150416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.1447150416 |
| Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.497409932 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 57426123566 ps |
| CPU time | 294.63 seconds |
| Started | Feb 21 12:57:16 PM PST 24 |
| Finished | Feb 21 01:02:11 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-3c0a50ac-4fd4-4e8e-9ece-1b5c66e6da25 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497409932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _mem_walk.497409932 |
| Directory | /workspace/13.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.4219543900 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 15834049451 ps |
| CPU time | 519.07 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 01:05:50 PM PST 24 |
| Peak memory | 375200 kb |
| Host | smart-bee9f010-72d3-449c-a552-befdf9a16a81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219543900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.4219543900 |
| Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.2654874162 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3387594004 ps |
| CPU time | 36.72 seconds |
| Started | Feb 21 12:57:12 PM PST 24 |
| Finished | Feb 21 12:57:49 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-0377ed2b-792b-4c61-aaeb-9d8292cc02e4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654874162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2654874162 |
| Directory | /workspace/13.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3616972988 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 14195862190 ps |
| CPU time | 477.4 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 01:05:05 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-8c26e9bb-640d-482c-b5f5-fdf53778fcb4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616972988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.3616972988 |
| Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.3428311648 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 403996397 ps |
| CPU time | 13.39 seconds |
| Started | Feb 21 12:57:16 PM PST 24 |
| Finished | Feb 21 12:57:30 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-a3b8e568-052b-4aec-b0e9-5f616be535c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428311648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3428311648 |
| Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_regwen.4196619036 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3014886592 ps |
| CPU time | 704.78 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 01:08:55 PM PST 24 |
| Peak memory | 374180 kb |
| Host | smart-acdb662f-8d01-4010-b12a-e3b7069e4257 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196619036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.4196619036 |
| Directory | /workspace/13.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_smoke.4133822897 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 646229260 ps |
| CPU time | 13.44 seconds |
| Started | Feb 21 12:57:19 PM PST 24 |
| Finished | Feb 21 12:57:32 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-51e4f038-005d-4924-b2bd-edcee95a4af1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133822897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.4133822897 |
| Directory | /workspace/13.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.4078307046 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 60007279363 ps |
| CPU time | 3561.36 seconds |
| Started | Feb 21 12:57:12 PM PST 24 |
| Finished | Feb 21 01:56:34 PM PST 24 |
| Peak memory | 381368 kb |
| Host | smart-7d8ab994-fc80-45bb-bdfc-964fba930284 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078307046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.4078307046 |
| Directory | /workspace/13.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1559646163 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3823877130 ps |
| CPU time | 253.96 seconds |
| Started | Feb 21 12:57:17 PM PST 24 |
| Finished | Feb 21 01:01:32 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-cc6551ff-a91d-4ad3-85d8-e6939dc06aa5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559646163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.1559646163 |
| Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1304241499 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 705989408 ps |
| CPU time | 28.59 seconds |
| Started | Feb 21 12:57:09 PM PST 24 |
| Finished | Feb 21 12:57:38 PM PST 24 |
| Peak memory | 212940 kb |
| Host | smart-7ce38699-f8ad-464f-83f5-04587ea3fe4e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304241499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1304241499 |
| Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.297364318 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 20417102 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:57:27 PM PST 24 |
| Finished | Feb 21 12:57:28 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-81fe2702-045e-4a32-987a-fb6d4fe272ac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297364318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.297364318 |
| Directory | /workspace/14.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_bijection.304059185 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 216469759023 ps |
| CPU time | 1803.95 seconds |
| Started | Feb 21 12:57:09 PM PST 24 |
| Finished | Feb 21 01:27:14 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-971772a7-387a-4a3d-a3e6-80bc46fe8c17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304059185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection. 304059185 |
| Directory | /workspace/14.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.1814748194 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 24666821067 ps |
| CPU time | 273.46 seconds |
| Started | Feb 21 12:57:14 PM PST 24 |
| Finished | Feb 21 01:01:48 PM PST 24 |
| Peak memory | 210628 kb |
| Host | smart-8c23700f-467c-470d-8ee6-55a0de4ec57d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814748194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.1814748194 |
| Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.4054703742 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 808541370 ps |
| CPU time | 129.66 seconds |
| Started | Feb 21 12:57:16 PM PST 24 |
| Finished | Feb 21 12:59:26 PM PST 24 |
| Peak memory | 371216 kb |
| Host | smart-be4b3503-ded1-40a8-bf39-cf2247176910 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054703742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.4054703742 |
| Directory | /workspace/14.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3572847898 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1648388996 ps |
| CPU time | 130.64 seconds |
| Started | Feb 21 12:57:18 PM PST 24 |
| Finished | Feb 21 12:59:29 PM PST 24 |
| Peak memory | 214408 kb |
| Host | smart-3458e2d5-73fd-4588-958f-3ed9f8c607e4 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572847898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3572847898 |
| Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.157125604 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 15764375643 ps |
| CPU time | 241.53 seconds |
| Started | Feb 21 12:57:14 PM PST 24 |
| Finished | Feb 21 01:01:15 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-e1386161-ca29-4ad9-835b-d87e1f01630b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157125604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _mem_walk.157125604 |
| Directory | /workspace/14.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.565018212 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 184150809221 ps |
| CPU time | 1914.81 seconds |
| Started | Feb 21 12:57:09 PM PST 24 |
| Finished | Feb 21 01:29:05 PM PST 24 |
| Peak memory | 379328 kb |
| Host | smart-dbba88e9-41fe-46ff-9c2c-bfda26857f80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565018212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multip le_keys.565018212 |
| Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.3637307983 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3567762926 ps |
| CPU time | 23.53 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 12:57:35 PM PST 24 |
| Peak memory | 245372 kb |
| Host | smart-3a787103-8d60-4884-9c82-0e8aff826daa |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637307983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.3637307983 |
| Directory | /workspace/14.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2547617584 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4891273499 ps |
| CPU time | 301.41 seconds |
| Started | Feb 21 12:57:17 PM PST 24 |
| Finished | Feb 21 01:02:19 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-85bef08f-ed9c-46aa-a9e5-63f1a23559a7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547617584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.2547617584 |
| Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.734570454 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 695998261 ps |
| CPU time | 5.39 seconds |
| Started | Feb 21 12:57:14 PM PST 24 |
| Finished | Feb 21 12:57:20 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-7f80c0f4-01c0-4b4f-96be-d5580ffa8b34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734570454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.734570454 |
| Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_regwen.3902812483 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 90299524277 ps |
| CPU time | 723.01 seconds |
| Started | Feb 21 12:57:18 PM PST 24 |
| Finished | Feb 21 01:09:21 PM PST 24 |
| Peak memory | 373216 kb |
| Host | smart-897479a7-34de-439e-92a3-dc6242a00a20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902812483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3902812483 |
| Directory | /workspace/14.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_smoke.2979892760 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1082516232 ps |
| CPU time | 18.35 seconds |
| Started | Feb 21 12:57:16 PM PST 24 |
| Finished | Feb 21 12:57:35 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-eec8f268-1a19-4ae4-ad3b-8529d6c9330f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979892760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2979892760 |
| Directory | /workspace/14.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.840504424 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 35336040487 ps |
| CPU time | 3064.12 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 01:48:25 PM PST 24 |
| Peak memory | 380384 kb |
| Host | smart-dda58c83-0d27-40b4-ad33-094d1be41367 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840504424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.840504424 |
| Directory | /workspace/14.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3054474704 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 51845366467 ps |
| CPU time | 315.92 seconds |
| Started | Feb 21 12:57:10 PM PST 24 |
| Finished | Feb 21 01:02:26 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-72a5e428-6195-4efa-8331-b332e662c00f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054474704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.3054474704 |
| Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2142723660 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 7689669665 ps |
| CPU time | 106.29 seconds |
| Started | Feb 21 12:57:14 PM PST 24 |
| Finished | Feb 21 12:59:00 PM PST 24 |
| Peak memory | 351680 kb |
| Host | smart-bc05533a-4a27-4671-948f-bc92f582d129 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142723660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.2142723660 |
| Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2770035640 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 27526415385 ps |
| CPU time | 1030.74 seconds |
| Started | Feb 21 12:57:21 PM PST 24 |
| Finished | Feb 21 01:14:32 PM PST 24 |
| Peak memory | 378264 kb |
| Host | smart-156bf50d-b71c-4681-b84b-050c1c7587af |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770035640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.2770035640 |
| Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.3713360620 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 44053071 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:57:25 PM PST 24 |
| Finished | Feb 21 12:57:27 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-d95f0be5-900e-4f8c-971d-739dba34d055 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713360620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3713360620 |
| Directory | /workspace/15.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2405433883 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 236806661971 ps |
| CPU time | 2202.83 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 01:34:04 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-4d7e3fa2-4e7a-4376-a785-8bcd5eb349dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405433883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2405433883 |
| Directory | /workspace/15.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_executable.1770764951 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 15261053572 ps |
| CPU time | 70.32 seconds |
| Started | Feb 21 12:57:22 PM PST 24 |
| Finished | Feb 21 12:58:33 PM PST 24 |
| Peak memory | 210640 kb |
| Host | smart-0292ddf7-afd5-466f-b449-ec14e51ef5b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770764951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.1770764951 |
| Directory | /workspace/15.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.1870758923 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 13173756196 ps |
| CPU time | 38.08 seconds |
| Started | Feb 21 12:57:23 PM PST 24 |
| Finished | Feb 21 12:58:01 PM PST 24 |
| Peak memory | 210612 kb |
| Host | smart-27ce642a-e0ad-4438-b4dc-cefa59d43a93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870758923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.1870758923 |
| Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.4029941923 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 4489843569 ps |
| CPU time | 165.03 seconds |
| Started | Feb 21 12:57:32 PM PST 24 |
| Finished | Feb 21 01:00:18 PM PST 24 |
| Peak memory | 363948 kb |
| Host | smart-ff688c55-0ee4-497b-966f-1b34ac9c8c4b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029941923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.4029941923 |
| Directory | /workspace/15.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.840256077 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 23689470771 ps |
| CPU time | 145.12 seconds |
| Started | Feb 21 12:57:22 PM PST 24 |
| Finished | Feb 21 12:59:47 PM PST 24 |
| Peak memory | 210836 kb |
| Host | smart-db890760-5dcc-453f-8453-73725d6e35d9 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840256077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_mem_partial_access.840256077 |
| Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.2385286198 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 18276649271 ps |
| CPU time | 300.22 seconds |
| Started | Feb 21 12:57:29 PM PST 24 |
| Finished | Feb 21 01:02:29 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-0fdb0715-5728-43d6-b387-0e7a4e68063e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385286198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.2385286198 |
| Directory | /workspace/15.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.3186530369 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 20382060906 ps |
| CPU time | 1958.86 seconds |
| Started | Feb 21 12:57:22 PM PST 24 |
| Finished | Feb 21 01:30:02 PM PST 24 |
| Peak memory | 377300 kb |
| Host | smart-373edd5c-82d3-407f-8c10-a66bbe978a80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186530369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.3186530369 |
| Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.107073531 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1298060192 ps |
| CPU time | 162.54 seconds |
| Started | Feb 21 12:57:33 PM PST 24 |
| Finished | Feb 21 01:00:15 PM PST 24 |
| Peak memory | 364588 kb |
| Host | smart-f7b6d8b1-05ba-40b8-b35e-9989ac6b15ee |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107073531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s ram_ctrl_partial_access.107073531 |
| Directory | /workspace/15.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.49660004 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 56553464397 ps |
| CPU time | 251.05 seconds |
| Started | Feb 21 12:57:24 PM PST 24 |
| Finished | Feb 21 01:01:35 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-cda57e59-7cc4-471e-9df1-e4b12f5c89de |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49660004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_partial_access_b2b.49660004 |
| Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.2053198949 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1398330580 ps |
| CPU time | 5.66 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 12:57:26 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-d1cf4923-21bd-4b30-9f2a-9cd64748614d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053198949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2053198949 |
| Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_regwen.900391778 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 12828507328 ps |
| CPU time | 612.84 seconds |
| Started | Feb 21 12:57:33 PM PST 24 |
| Finished | Feb 21 01:07:46 PM PST 24 |
| Peak memory | 377216 kb |
| Host | smart-a7434342-4dbf-483c-9199-3958a8c3e30d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900391778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.900391778 |
| Directory | /workspace/15.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_smoke.72168410 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 998572097 ps |
| CPU time | 36.7 seconds |
| Started | Feb 21 12:57:28 PM PST 24 |
| Finished | Feb 21 12:58:05 PM PST 24 |
| Peak memory | 287212 kb |
| Host | smart-ace419d7-182a-48da-a767-1c2dd9a90da1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72168410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.72168410 |
| Directory | /workspace/15.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1838448656 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 8774273025 ps |
| CPU time | 290.91 seconds |
| Started | Feb 21 12:57:27 PM PST 24 |
| Finished | Feb 21 01:02:19 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-fa62355c-c623-4956-8063-6f88f241de3b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838448656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.1838448656 |
| Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.931355535 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2790346425 ps |
| CPU time | 32.43 seconds |
| Started | Feb 21 12:57:24 PM PST 24 |
| Finished | Feb 21 12:57:57 PM PST 24 |
| Peak memory | 235244 kb |
| Host | smart-5d784e16-4a75-45fd-b61b-fe821dec4c40 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931355535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.931355535 |
| Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2034686900 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4112709390 ps |
| CPU time | 50.25 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 12:58:11 PM PST 24 |
| Peak memory | 297368 kb |
| Host | smart-4bb4e260-cc47-4c12-95c7-59e75d658fcf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034686900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.2034686900 |
| Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.295748760 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 148424342 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 12:57:21 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-622ebab6-fb41-46a6-9293-97b6a28b21bc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295748760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.295748760 |
| Directory | /workspace/16.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_bijection.605081653 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 17387375970 ps |
| CPU time | 1155.99 seconds |
| Started | Feb 21 12:57:22 PM PST 24 |
| Finished | Feb 21 01:16:39 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-aa642fab-a0f5-4e95-9204-a99765c59d25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605081653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection. 605081653 |
| Directory | /workspace/16.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.2210047650 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 21366167456 ps |
| CPU time | 81.77 seconds |
| Started | Feb 21 12:57:21 PM PST 24 |
| Finished | Feb 21 12:58:43 PM PST 24 |
| Peak memory | 210756 kb |
| Host | smart-4660dc4f-7dff-4b17-8a76-3fa4a115c1d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210047650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2210047650 |
| Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.3788879838 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2988702953 ps |
| CPU time | 113.98 seconds |
| Started | Feb 21 12:57:28 PM PST 24 |
| Finished | Feb 21 12:59:22 PM PST 24 |
| Peak memory | 344592 kb |
| Host | smart-5dbd9dba-8ba5-4068-80fb-746c40c02922 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788879838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.3788879838 |
| Directory | /workspace/16.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3599614375 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 4824639453 ps |
| CPU time | 143.26 seconds |
| Started | Feb 21 12:57:23 PM PST 24 |
| Finished | Feb 21 12:59:47 PM PST 24 |
| Peak memory | 214812 kb |
| Host | smart-1a198354-9235-4f88-a852-e8284b0028fd |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599614375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.3599614375 |
| Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.258575799 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 38325499097 ps |
| CPU time | 142.46 seconds |
| Started | Feb 21 12:57:27 PM PST 24 |
| Finished | Feb 21 12:59:50 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-b4f7cfd8-87d6-45b6-95b1-2535b73eae2a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258575799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _mem_walk.258575799 |
| Directory | /workspace/16.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.1924869580 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 8870077954 ps |
| CPU time | 41.8 seconds |
| Started | Feb 21 12:57:20 PM PST 24 |
| Finished | Feb 21 12:58:02 PM PST 24 |
| Peak memory | 246252 kb |
| Host | smart-0c6156e6-b53f-4dfe-a93b-8daa6f4ab4d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924869580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.1924869580 |
| Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.554528039 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 832838508 ps |
| CPU time | 54.36 seconds |
| Started | Feb 21 12:57:33 PM PST 24 |
| Finished | Feb 21 12:58:27 PM PST 24 |
| Peak memory | 298340 kb |
| Host | smart-9504bcf8-4980-49a0-aaa0-ca5469616944 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554528039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.554528039 |
| Directory | /workspace/16.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.467768004 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 14463918891 ps |
| CPU time | 214.97 seconds |
| Started | Feb 21 12:57:21 PM PST 24 |
| Finished | Feb 21 01:00:57 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-3f0459f1-9c1c-4b0d-b58e-aa01fe5cdb3b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467768004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.sram_ctrl_partial_access_b2b.467768004 |
| Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.3744572597 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 343678819 ps |
| CPU time | 13.45 seconds |
| Started | Feb 21 12:57:32 PM PST 24 |
| Finished | Feb 21 12:57:46 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-ed14a958-425d-4c56-85a2-ec54778a643e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744572597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3744572597 |
| Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2500087664 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 8885309335 ps |
| CPU time | 709.22 seconds |
| Started | Feb 21 12:57:33 PM PST 24 |
| Finished | Feb 21 01:09:22 PM PST 24 |
| Peak memory | 377160 kb |
| Host | smart-db7543b7-46ac-4208-8ad7-37fa1d94381a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500087664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2500087664 |
| Directory | /workspace/16.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_smoke.2533904273 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2003896764 ps |
| CPU time | 40.38 seconds |
| Started | Feb 21 12:57:18 PM PST 24 |
| Finished | Feb 21 12:57:58 PM PST 24 |
| Peak memory | 295612 kb |
| Host | smart-8c9ff079-23e7-4bbb-92c2-51ca58dd61a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533904273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2533904273 |
| Directory | /workspace/16.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.4230288915 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 17689784233 ps |
| CPU time | 308.58 seconds |
| Started | Feb 21 12:57:27 PM PST 24 |
| Finished | Feb 21 01:02:36 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-82233442-1b8f-4d59-b61b-01a856e80a54 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230288915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.4230288915 |
| Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2599819381 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 751433848 ps |
| CPU time | 52.07 seconds |
| Started | Feb 21 12:57:17 PM PST 24 |
| Finished | Feb 21 12:58:10 PM PST 24 |
| Peak memory | 289272 kb |
| Host | smart-6bb9fb0d-a00f-4a4c-81df-48c119e62ddb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599819381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2599819381 |
| Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.529120937 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 17220504855 ps |
| CPU time | 866.66 seconds |
| Started | Feb 21 12:57:38 PM PST 24 |
| Finished | Feb 21 01:12:05 PM PST 24 |
| Peak memory | 367964 kb |
| Host | smart-1671b45a-f5a1-4d03-902b-6f48bd9b1579 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529120937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_access_during_key_req.529120937 |
| Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.1684244819 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 51567386 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:57:41 PM PST 24 |
| Finished | Feb 21 12:57:42 PM PST 24 |
| Peak memory | 201880 kb |
| Host | smart-0445ccb7-03f1-435f-8d1e-18622bc1ddc8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684244819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1684244819 |
| Directory | /workspace/17.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_bijection.1376200612 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 129789508128 ps |
| CPU time | 702.66 seconds |
| Started | Feb 21 12:57:29 PM PST 24 |
| Finished | Feb 21 01:09:12 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-b4a4beb4-fed1-4bc2-b0f5-bb2639cb032b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376200612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .1376200612 |
| Directory | /workspace/17.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_executable.43432350 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 12652303760 ps |
| CPU time | 180.26 seconds |
| Started | Feb 21 12:57:39 PM PST 24 |
| Finished | Feb 21 01:00:40 PM PST 24 |
| Peak memory | 302600 kb |
| Host | smart-2d62fe56-3448-4937-b2a7-88f1a7f61330 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43432350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable .43432350 |
| Directory | /workspace/17.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.1972177086 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 19978073202 ps |
| CPU time | 276.29 seconds |
| Started | Feb 21 12:57:41 PM PST 24 |
| Finished | Feb 21 01:02:17 PM PST 24 |
| Peak memory | 210648 kb |
| Host | smart-272f8615-7eba-455a-bb39-4ff8a6f033be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972177086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.1972177086 |
| Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.2729705017 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2889899179 ps |
| CPU time | 34.08 seconds |
| Started | Feb 21 12:57:23 PM PST 24 |
| Finished | Feb 21 12:57:58 PM PST 24 |
| Peak memory | 242416 kb |
| Host | smart-1201e5d3-7396-43a7-ae1e-e9d375d478dc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729705017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.2729705017 |
| Directory | /workspace/17.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3401266865 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 6460298187 ps |
| CPU time | 133.29 seconds |
| Started | Feb 21 12:57:41 PM PST 24 |
| Finished | Feb 21 12:59:55 PM PST 24 |
| Peak memory | 214752 kb |
| Host | smart-874dd6f9-0489-4aad-8be1-efff3cf2c623 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401266865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3401266865 |
| Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.2889760981 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 14598613639 ps |
| CPU time | 244.49 seconds |
| Started | Feb 21 12:57:39 PM PST 24 |
| Finished | Feb 21 01:01:44 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-eebb9833-959c-4605-bcfb-3ba7991c2071 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889760981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.2889760981 |
| Directory | /workspace/17.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.418986744 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 20421139923 ps |
| CPU time | 1121.28 seconds |
| Started | Feb 21 12:57:25 PM PST 24 |
| Finished | Feb 21 01:16:07 PM PST 24 |
| Peak memory | 379352 kb |
| Host | smart-bfbb3a67-34ff-4b1b-b97e-c851f987ce65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418986744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip le_keys.418986744 |
| Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.3221876070 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1938531454 ps |
| CPU time | 65.15 seconds |
| Started | Feb 21 12:57:23 PM PST 24 |
| Finished | Feb 21 12:58:29 PM PST 24 |
| Peak memory | 293396 kb |
| Host | smart-f042988b-51bc-4009-91c7-fb56819583c1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221876070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.3221876070 |
| Directory | /workspace/17.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1489457297 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 27648663157 ps |
| CPU time | 428.86 seconds |
| Started | Feb 21 12:57:25 PM PST 24 |
| Finished | Feb 21 01:04:35 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-da4a5f61-5042-4896-8053-9c3afb502817 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489457297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.1489457297 |
| Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.356609733 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 362643804 ps |
| CPU time | 5.61 seconds |
| Started | Feb 21 12:57:38 PM PST 24 |
| Finished | Feb 21 12:57:43 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-9808aab0-611a-4c1d-b751-b506038d52a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356609733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.356609733 |
| Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_regwen.2297282805 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 11990089925 ps |
| CPU time | 957.09 seconds |
| Started | Feb 21 12:57:37 PM PST 24 |
| Finished | Feb 21 01:13:35 PM PST 24 |
| Peak memory | 380108 kb |
| Host | smart-642892d2-76b7-4ccd-8cac-bfb67350a4ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297282805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2297282805 |
| Directory | /workspace/17.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_smoke.2597203289 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 5188837972 ps |
| CPU time | 23.65 seconds |
| Started | Feb 21 12:57:27 PM PST 24 |
| Finished | Feb 21 12:57:52 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-67275645-3101-4af8-b989-39e4cef80f13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597203289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2597203289 |
| Directory | /workspace/17.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.1862899033 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 58244648836 ps |
| CPU time | 3677.17 seconds |
| Started | Feb 21 12:57:42 PM PST 24 |
| Finished | Feb 21 01:58:59 PM PST 24 |
| Peak memory | 380304 kb |
| Host | smart-d7baf1c5-ef70-492f-8ec8-a8c6044b1c08 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862899033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.1862899033 |
| Directory | /workspace/17.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2152407358 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 11598519230 ps |
| CPU time | 241.74 seconds |
| Started | Feb 21 12:57:24 PM PST 24 |
| Finished | Feb 21 01:01:27 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-d64e8052-7f81-4b57-9d95-ef2a66964476 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152407358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.2152407358 |
| Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.656827628 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3111801776 ps |
| CPU time | 42.53 seconds |
| Started | Feb 21 12:57:40 PM PST 24 |
| Finished | Feb 21 12:58:23 PM PST 24 |
| Peak memory | 270952 kb |
| Host | smart-3cb8f1fb-850b-4c5a-8846-ffad554de4ea |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656827628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.656827628 |
| Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.30365262 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 10839011860 ps |
| CPU time | 525.27 seconds |
| Started | Feb 21 12:57:38 PM PST 24 |
| Finished | Feb 21 01:06:24 PM PST 24 |
| Peak memory | 352700 kb |
| Host | smart-704a7ff4-2cc3-449b-b87f-6bd6988c94cf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30365262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.sram_ctrl_access_during_key_req.30365262 |
| Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.2416958206 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 116323393 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:57:37 PM PST 24 |
| Finished | Feb 21 12:57:38 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-75c81cac-2a45-4612-a4d5-2dcee039d37f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416958206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2416958206 |
| Directory | /workspace/18.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_bijection.299101652 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 31800634864 ps |
| CPU time | 2244.69 seconds |
| Started | Feb 21 12:57:37 PM PST 24 |
| Finished | Feb 21 01:35:03 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-b1a379d1-88e9-4fb4-93ef-dcb747cf1c1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299101652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection. 299101652 |
| Directory | /workspace/18.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_executable.30734397 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5586013743 ps |
| CPU time | 217.47 seconds |
| Started | Feb 21 12:57:39 PM PST 24 |
| Finished | Feb 21 01:01:17 PM PST 24 |
| Peak memory | 348612 kb |
| Host | smart-fcef8a4e-d04c-45f3-b722-cf98f2929520 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30734397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable .30734397 |
| Directory | /workspace/18.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3795418586 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 7302468383 ps |
| CPU time | 66.35 seconds |
| Started | Feb 21 12:57:42 PM PST 24 |
| Finished | Feb 21 12:58:49 PM PST 24 |
| Peak memory | 210620 kb |
| Host | smart-0e70217a-0052-4ad0-862f-341dcb608b9e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795418586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3795418586 |
| Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.2373017372 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2000991934 ps |
| CPU time | 37.66 seconds |
| Started | Feb 21 12:57:37 PM PST 24 |
| Finished | Feb 21 12:58:15 PM PST 24 |
| Peak memory | 255768 kb |
| Host | smart-ca919edb-1c8c-4a26-b25c-4eb0f4715671 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373017372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.2373017372 |
| Directory | /workspace/18.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1757200124 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 16209305692 ps |
| CPU time | 136.35 seconds |
| Started | Feb 21 12:57:41 PM PST 24 |
| Finished | Feb 21 12:59:57 PM PST 24 |
| Peak memory | 214892 kb |
| Host | smart-025135ca-fceb-4a51-9673-9c09ca6c8db0 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757200124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.1757200124 |
| Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3087625283 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 14048112791 ps |
| CPU time | 272.23 seconds |
| Started | Feb 21 12:57:47 PM PST 24 |
| Finished | Feb 21 01:02:20 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-32ecab92-352a-49e8-a04d-7f2eeee339cb |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087625283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3087625283 |
| Directory | /workspace/18.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.4134601688 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5425689279 ps |
| CPU time | 430.63 seconds |
| Started | Feb 21 12:57:38 PM PST 24 |
| Finished | Feb 21 01:04:49 PM PST 24 |
| Peak memory | 376492 kb |
| Host | smart-c976cf9f-d2d8-45b4-bbb3-6aaf2df29048 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134601688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.4134601688 |
| Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.3339135708 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 955143479 ps |
| CPU time | 69.33 seconds |
| Started | Feb 21 12:57:42 PM PST 24 |
| Finished | Feb 21 12:58:52 PM PST 24 |
| Peak memory | 326872 kb |
| Host | smart-35e2196d-2a40-4b49-b2d5-f2f01c83ceb4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339135708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.3339135708 |
| Directory | /workspace/18.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1849878218 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 48618462118 ps |
| CPU time | 563.2 seconds |
| Started | Feb 21 12:57:38 PM PST 24 |
| Finished | Feb 21 01:07:01 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-2f14c906-c652-4f13-8c50-d34c293a2a9e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849878218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.1849878218 |
| Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.1914281912 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1407093300 ps |
| CPU time | 6.61 seconds |
| Started | Feb 21 12:57:41 PM PST 24 |
| Finished | Feb 21 12:57:48 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-411eac1e-acf2-489b-bb80-d61813638923 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914281912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1914281912 |
| Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_regwen.3535017993 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 145759934405 ps |
| CPU time | 868.29 seconds |
| Started | Feb 21 12:57:36 PM PST 24 |
| Finished | Feb 21 01:12:05 PM PST 24 |
| Peak memory | 376212 kb |
| Host | smart-fdbcc5d0-ef6c-406a-a646-adb59319c803 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535017993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3535017993 |
| Directory | /workspace/18.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_smoke.2699697998 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5582092151 ps |
| CPU time | 133.45 seconds |
| Started | Feb 21 12:57:37 PM PST 24 |
| Finished | Feb 21 12:59:51 PM PST 24 |
| Peak memory | 365912 kb |
| Host | smart-a32b91b0-1b6a-4d68-92eb-2a781b404448 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699697998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2699697998 |
| Directory | /workspace/18.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3307165798 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 21218916202 ps |
| CPU time | 587.48 seconds |
| Started | Feb 21 12:57:40 PM PST 24 |
| Finished | Feb 21 01:07:28 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-c0e58028-43e1-4378-aaed-84ec1fed84a7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307165798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3307165798 |
| Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.209845399 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2916898834 ps |
| CPU time | 51.2 seconds |
| Started | Feb 21 12:57:37 PM PST 24 |
| Finished | Feb 21 12:58:28 PM PST 24 |
| Peak memory | 290360 kb |
| Host | smart-e00ddca1-fa57-42e3-8785-f32e5b214e99 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209845399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.209845399 |
| Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2536620719 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3995797683 ps |
| CPU time | 606.5 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 01:07:53 PM PST 24 |
| Peak memory | 359884 kb |
| Host | smart-a1adf92e-2e42-4e9f-9415-d55eef4155a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536620719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.2536620719 |
| Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.3073451898 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 37389104 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 12:57:46 PM PST 24 |
| Peak memory | 201908 kb |
| Host | smart-932659ea-1891-4fb8-a526-c72900b0c74d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073451898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3073451898 |
| Directory | /workspace/19.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_bijection.3996298014 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 89522701634 ps |
| CPU time | 546.81 seconds |
| Started | Feb 21 12:57:43 PM PST 24 |
| Finished | Feb 21 01:06:50 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-880de233-a73c-4a16-901b-905efe9b49d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996298014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .3996298014 |
| Directory | /workspace/19.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_executable.2419251822 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 98788099366 ps |
| CPU time | 1016.33 seconds |
| Started | Feb 21 12:57:44 PM PST 24 |
| Finished | Feb 21 01:14:42 PM PST 24 |
| Peak memory | 375160 kb |
| Host | smart-f3e3c8a5-c3a4-4acc-8d19-66f7c7b53c0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419251822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.2419251822 |
| Directory | /workspace/19.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.891851379 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 16843597830 ps |
| CPU time | 153.73 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 01:00:19 PM PST 24 |
| Peak memory | 210588 kb |
| Host | smart-20dd778f-9337-4a9e-9708-711a1931b575 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891851379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esc alation.891851379 |
| Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.1380937197 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3357641923 ps |
| CPU time | 76.04 seconds |
| Started | Feb 21 12:57:43 PM PST 24 |
| Finished | Feb 21 12:58:59 PM PST 24 |
| Peak memory | 327184 kb |
| Host | smart-d70995bc-9e81-4bf3-b330-ab3a523370c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380937197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.1380937197 |
| Directory | /workspace/19.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1264821547 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 958195603 ps |
| CPU time | 70.09 seconds |
| Started | Feb 21 12:57:47 PM PST 24 |
| Finished | Feb 21 12:58:58 PM PST 24 |
| Peak memory | 211472 kb |
| Host | smart-ff7ba0f5-9003-46f4-908c-502af25b0236 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264821547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.1264821547 |
| Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.3170274916 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2086606952 ps |
| CPU time | 130.2 seconds |
| Started | Feb 21 12:57:48 PM PST 24 |
| Finished | Feb 21 12:59:59 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-54c6af6e-dbc1-42e3-a85f-fd9d45141323 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170274916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3170274916 |
| Directory | /workspace/19.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.1486229135 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 12713544597 ps |
| CPU time | 1579.52 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 01:24:06 PM PST 24 |
| Peak memory | 376292 kb |
| Host | smart-8c3f77c7-abc6-469d-a186-d3dd7736f245 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486229135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.1486229135 |
| Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.1473807417 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2312643698 ps |
| CPU time | 21.1 seconds |
| Started | Feb 21 12:57:44 PM PST 24 |
| Finished | Feb 21 12:58:06 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-74110c70-2abd-4f77-89fe-0bab70c11dbf |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473807417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.1473807417 |
| Directory | /workspace/19.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2770367475 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 26425439435 ps |
| CPU time | 421.54 seconds |
| Started | Feb 21 12:57:46 PM PST 24 |
| Finished | Feb 21 01:04:49 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-e5a87d11-2c6c-401a-bcd8-26d1303dfc35 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770367475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.2770367475 |
| Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3536013402 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2607313421 ps |
| CPU time | 6.07 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 12:57:52 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-e7fc3af4-5b2c-497d-8e0a-f3319d332266 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536013402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3536013402 |
| Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_regwen.3668470559 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 14058955729 ps |
| CPU time | 1002.78 seconds |
| Started | Feb 21 12:57:46 PM PST 24 |
| Finished | Feb 21 01:14:30 PM PST 24 |
| Peak memory | 357872 kb |
| Host | smart-382bd5f1-23f0-4706-af54-4f2c973a2ea4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668470559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3668470559 |
| Directory | /workspace/19.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_smoke.4232474142 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3465783738 ps |
| CPU time | 17.03 seconds |
| Started | Feb 21 12:57:44 PM PST 24 |
| Finished | Feb 21 12:58:02 PM PST 24 |
| Peak memory | 236716 kb |
| Host | smart-452cbdb4-63bf-49c4-a37d-10612984a739 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232474142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.4232474142 |
| Directory | /workspace/19.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1035570402 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 10781511955 ps |
| CPU time | 170.47 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 01:00:37 PM PST 24 |
| Peak memory | 201772 kb |
| Host | smart-0a280897-a827-4026-a956-7e1f6f956ab7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035570402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.1035570402 |
| Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2270183393 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 6268050051 ps |
| CPU time | 81.67 seconds |
| Started | Feb 21 12:57:46 PM PST 24 |
| Finished | Feb 21 12:59:09 PM PST 24 |
| Peak memory | 332236 kb |
| Host | smart-4c8d0ee5-74c1-48f5-b53f-9532252908ad |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270183393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.2270183393 |
| Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3399624212 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 25625994692 ps |
| CPU time | 1314.45 seconds |
| Started | Feb 21 12:56:28 PM PST 24 |
| Finished | Feb 21 01:18:23 PM PST 24 |
| Peak memory | 374904 kb |
| Host | smart-4daaf662-24ba-4f5b-bad9-f244dcc96dc8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399624212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.3399624212 |
| Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.3812293841 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 22178275 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:56:29 PM PST 24 |
| Finished | Feb 21 12:56:30 PM PST 24 |
| Peak memory | 201948 kb |
| Host | smart-fa3a5dba-9553-4cdb-a970-fd43b2bfeb13 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812293841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3812293841 |
| Directory | /workspace/2.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_bijection.1575336598 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 119949914125 ps |
| CPU time | 2642.22 seconds |
| Started | Feb 21 12:56:32 PM PST 24 |
| Finished | Feb 21 01:40:35 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-d627c381-89e5-4364-82cd-e42f413c2999 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575336598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1575336598 |
| Directory | /workspace/2.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_executable.4155422811 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 73590091315 ps |
| CPU time | 858.83 seconds |
| Started | Feb 21 12:56:39 PM PST 24 |
| Finished | Feb 21 01:10:58 PM PST 24 |
| Peak memory | 377088 kb |
| Host | smart-bc86dfaa-6d72-406b-8c8c-dcafe5595bbf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155422811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.4155422811 |
| Directory | /workspace/2.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.673650446 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3172700920 ps |
| CPU time | 141.99 seconds |
| Started | Feb 21 12:56:33 PM PST 24 |
| Finished | Feb 21 12:58:55 PM PST 24 |
| Peak memory | 359880 kb |
| Host | smart-7bf8de2f-d162-407c-aa73-5c83065f2e91 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673650446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.sram_ctrl_max_throughput.673650446 |
| Directory | /workspace/2.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2473537913 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2456253414 ps |
| CPU time | 75.11 seconds |
| Started | Feb 21 12:56:28 PM PST 24 |
| Finished | Feb 21 12:57:44 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-8902364e-eaad-419e-82eb-f53b2c1ba122 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473537913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.2473537913 |
| Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.2017288544 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2002964869 ps |
| CPU time | 121.24 seconds |
| Started | Feb 21 12:56:31 PM PST 24 |
| Finished | Feb 21 12:58:33 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-cc67fca5-aea3-4148-a353-3634862457a5 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017288544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.2017288544 |
| Directory | /workspace/2.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.1198480322 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 18121112809 ps |
| CPU time | 281.48 seconds |
| Started | Feb 21 12:56:29 PM PST 24 |
| Finished | Feb 21 01:01:11 PM PST 24 |
| Peak memory | 377264 kb |
| Host | smart-447da206-dfb3-42e4-bab8-1f19c0cc5d4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198480322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.1198480322 |
| Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.1825702350 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3073392634 ps |
| CPU time | 57.18 seconds |
| Started | Feb 21 12:56:28 PM PST 24 |
| Finished | Feb 21 12:57:26 PM PST 24 |
| Peak memory | 297428 kb |
| Host | smart-db835c24-416e-45ff-bf14-d759bd9e0631 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825702350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.1825702350 |
| Directory | /workspace/2.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.953799818 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 46143186939 ps |
| CPU time | 250.87 seconds |
| Started | Feb 21 12:56:29 PM PST 24 |
| Finished | Feb 21 01:00:40 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-fb789a81-bfe7-4cc3-8bae-2484492ba609 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953799818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.sram_ctrl_partial_access_b2b.953799818 |
| Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.3636672971 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1165259637 ps |
| CPU time | 5.63 seconds |
| Started | Feb 21 12:56:30 PM PST 24 |
| Finished | Feb 21 12:56:36 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-53008057-915b-43e6-96bb-b8f7597fe786 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636672971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3636672971 |
| Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_regwen.1019256977 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 22077709966 ps |
| CPU time | 1396.44 seconds |
| Started | Feb 21 12:56:29 PM PST 24 |
| Finished | Feb 21 01:19:46 PM PST 24 |
| Peak memory | 380368 kb |
| Host | smart-a940746c-156b-445c-9d3a-d1e65d722fc6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019256977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1019256977 |
| Directory | /workspace/2.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.4224467287 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 357417100 ps |
| CPU time | 2.98 seconds |
| Started | Feb 21 12:56:32 PM PST 24 |
| Finished | Feb 21 12:56:35 PM PST 24 |
| Peak memory | 220884 kb |
| Host | smart-627e5201-f261-4430-bae3-87449085d8be |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224467287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.4224467287 |
| Directory | /workspace/2.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_smoke.3905965106 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 929406155 ps |
| CPU time | 31.94 seconds |
| Started | Feb 21 12:56:27 PM PST 24 |
| Finished | Feb 21 12:57:00 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-5c0c2362-09bc-4f13-9c51-a42ea86fa90e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905965106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3905965106 |
| Directory | /workspace/2.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.2732744908 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 126988247989 ps |
| CPU time | 4207.13 seconds |
| Started | Feb 21 12:56:29 PM PST 24 |
| Finished | Feb 21 02:06:37 PM PST 24 |
| Peak memory | 378316 kb |
| Host | smart-65d25dca-c601-4bd9-9ae9-00a231fe91f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732744908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2732744908 |
| Directory | /workspace/2.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3241289508 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 18389656203 ps |
| CPU time | 293.88 seconds |
| Started | Feb 21 12:56:34 PM PST 24 |
| Finished | Feb 21 01:01:29 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-f011cd79-081d-4512-811e-f22d02034957 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241289508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.3241289508 |
| Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2366852689 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4654544584 ps |
| CPU time | 36.18 seconds |
| Started | Feb 21 12:56:31 PM PST 24 |
| Finished | Feb 21 12:57:08 PM PST 24 |
| Peak memory | 243440 kb |
| Host | smart-f49b9d93-06ef-41c2-96d3-fa2a22d67443 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366852689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.2366852689 |
| Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1356560618 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 24413307915 ps |
| CPU time | 520.03 seconds |
| Started | Feb 21 12:57:43 PM PST 24 |
| Finished | Feb 21 01:06:23 PM PST 24 |
| Peak memory | 364532 kb |
| Host | smart-791b3151-03a2-479b-8255-e03e6980628e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356560618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.1356560618 |
| Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.494578177 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 55160575 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:57:44 PM PST 24 |
| Finished | Feb 21 12:57:45 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-698a116f-909e-4631-bb71-bc019a4773ad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494578177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.494578177 |
| Directory | /workspace/20.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_bijection.59804888 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 264634912032 ps |
| CPU time | 2039.75 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 01:31:46 PM PST 24 |
| Peak memory | 201756 kb |
| Host | smart-771446cd-c317-4822-8ef6-7c9569ac3fac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59804888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.59804888 |
| Directory | /workspace/20.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.2629605650 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2027459695 ps |
| CPU time | 20.85 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 12:58:07 PM PST 24 |
| Peak memory | 213520 kb |
| Host | smart-8c69a75a-af16-458e-ac2a-c87195ed07ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629605650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.2629605650 |
| Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.546552891 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 3201674418 ps |
| CPU time | 28.75 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 12:58:15 PM PST 24 |
| Peak memory | 218684 kb |
| Host | smart-908eeaa6-83f1-41cf-b593-6840d6762289 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546552891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.sram_ctrl_max_throughput.546552891 |
| Directory | /workspace/20.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2623743191 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5453356062 ps |
| CPU time | 77.6 seconds |
| Started | Feb 21 12:57:47 PM PST 24 |
| Finished | Feb 21 12:59:06 PM PST 24 |
| Peak memory | 210908 kb |
| Host | smart-b6e9e14e-e565-4f3c-98b4-10c690185b0e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623743191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2623743191 |
| Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.3761835623 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 57396536655 ps |
| CPU time | 272.68 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 01:02:19 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-2b94110c-6274-4a0e-b6f8-53efbc71c975 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761835623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3761835623 |
| Directory | /workspace/20.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.3406906562 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 25547765516 ps |
| CPU time | 1700.45 seconds |
| Started | Feb 21 12:57:43 PM PST 24 |
| Finished | Feb 21 01:26:04 PM PST 24 |
| Peak memory | 378404 kb |
| Host | smart-2ea4aab6-8b83-4c96-b0c2-70e382127536 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406906562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.3406906562 |
| Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.1534555466 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1695666162 ps |
| CPU time | 81.27 seconds |
| Started | Feb 21 12:57:48 PM PST 24 |
| Finished | Feb 21 12:59:10 PM PST 24 |
| Peak memory | 311828 kb |
| Host | smart-5180ef3c-9dc9-428c-adcd-1f2ccfa442b5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534555466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1534555466 |
| Directory | /workspace/20.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.251060649 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 15415375144 ps |
| CPU time | 330.54 seconds |
| Started | Feb 21 12:57:46 PM PST 24 |
| Finished | Feb 21 01:03:18 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-b7d761c9-fa6a-4095-b704-031b2132fef9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251060649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.sram_ctrl_partial_access_b2b.251060649 |
| Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.1823341150 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1979793387 ps |
| CPU time | 5.78 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 12:57:52 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-6f1037a8-affb-4d1a-a4d9-0a0c48e7cda6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823341150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1823341150 |
| Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_regwen.295416485 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 10006771079 ps |
| CPU time | 86.76 seconds |
| Started | Feb 21 12:57:43 PM PST 24 |
| Finished | Feb 21 12:59:10 PM PST 24 |
| Peak memory | 310464 kb |
| Host | smart-0dea186b-2fea-455f-a85d-ecbf4b647c5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295416485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.295416485 |
| Directory | /workspace/20.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_smoke.4201342546 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1066032091 ps |
| CPU time | 19.09 seconds |
| Started | Feb 21 12:57:44 PM PST 24 |
| Finished | Feb 21 12:58:04 PM PST 24 |
| Peak memory | 260496 kb |
| Host | smart-26658a3d-781c-4f69-bf0d-16e6ff40d681 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201342546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4201342546 |
| Directory | /workspace/20.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.449860437 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 114995905007 ps |
| CPU time | 3595.51 seconds |
| Started | Feb 21 12:57:45 PM PST 24 |
| Finished | Feb 21 01:57:42 PM PST 24 |
| Peak memory | 380364 kb |
| Host | smart-20179fc7-9ea9-4483-93c5-33b9b5d3e274 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449860437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_stress_all.449860437 |
| Directory | /workspace/20.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.755216624 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 10109746947 ps |
| CPU time | 187.95 seconds |
| Started | Feb 21 12:57:44 PM PST 24 |
| Finished | Feb 21 01:00:53 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-c3ba1f28-4713-4cbf-ad57-0cdc54c30d67 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755216624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sram_ctrl_stress_pipeline.755216624 |
| Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3851800010 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1573635551 ps |
| CPU time | 65.37 seconds |
| Started | Feb 21 12:57:46 PM PST 24 |
| Finished | Feb 21 12:58:52 PM PST 24 |
| Peak memory | 293648 kb |
| Host | smart-4ec89021-5ad6-4755-9839-2201c062cfd8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851800010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3851800010 |
| Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.294380208 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 23230159306 ps |
| CPU time | 706.1 seconds |
| Started | Feb 21 12:57:54 PM PST 24 |
| Finished | Feb 21 01:09:40 PM PST 24 |
| Peak memory | 378292 kb |
| Host | smart-d8e7d4a4-755b-4598-a20e-c0a9be2d36b8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294380208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.294380208 |
| Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.753900290 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 39293382 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:57:55 PM PST 24 |
| Finished | Feb 21 12:57:56 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-0cad3524-18d1-4974-9b07-efde93569cb7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753900290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.753900290 |
| Directory | /workspace/21.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_bijection.2986445151 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 26028724404 ps |
| CPU time | 1698.68 seconds |
| Started | Feb 21 12:57:54 PM PST 24 |
| Finished | Feb 21 01:26:13 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-a61dfef0-5bb8-4c9d-b848-5c69e01f410a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986445151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .2986445151 |
| Directory | /workspace/21.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.2756927170 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 20578606564 ps |
| CPU time | 103.72 seconds |
| Started | Feb 21 12:57:56 PM PST 24 |
| Finished | Feb 21 12:59:40 PM PST 24 |
| Peak memory | 210516 kb |
| Host | smart-72db6e9e-054e-4cf7-98ef-8a700a7cc1d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756927170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2756927170 |
| Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.3496479832 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1501549983 ps |
| CPU time | 62.8 seconds |
| Started | Feb 21 12:57:55 PM PST 24 |
| Finished | Feb 21 12:58:58 PM PST 24 |
| Peak memory | 288460 kb |
| Host | smart-8dae6405-1d10-4365-9624-7fd471ba3d5d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496479832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.3496479832 |
| Directory | /workspace/21.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3646580834 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4361783786 ps |
| CPU time | 143.21 seconds |
| Started | Feb 21 12:58:02 PM PST 24 |
| Finished | Feb 21 01:00:26 PM PST 24 |
| Peak memory | 211520 kb |
| Host | smart-9da69ae2-a653-47c6-b14b-9b9f05602b68 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646580834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.3646580834 |
| Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.810204423 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 16422848644 ps |
| CPU time | 249.32 seconds |
| Started | Feb 21 12:57:56 PM PST 24 |
| Finished | Feb 21 01:02:06 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-0f8653f4-24f2-4b43-abc5-e9b738714230 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810204423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _mem_walk.810204423 |
| Directory | /workspace/21.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.3601932431 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 10975949341 ps |
| CPU time | 680.66 seconds |
| Started | Feb 21 12:57:55 PM PST 24 |
| Finished | Feb 21 01:09:16 PM PST 24 |
| Peak memory | 375124 kb |
| Host | smart-2f90280d-7675-493d-b257-2c5a93dc2890 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601932431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.3601932431 |
| Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.1518173170 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 890108434 ps |
| CPU time | 92.12 seconds |
| Started | Feb 21 12:57:55 PM PST 24 |
| Finished | Feb 21 12:59:28 PM PST 24 |
| Peak memory | 348404 kb |
| Host | smart-3daf5473-87d8-44a5-8596-d0f0fc79599d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518173170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1518173170 |
| Directory | /workspace/21.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1720563549 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 13549429616 ps |
| CPU time | 446.31 seconds |
| Started | Feb 21 12:58:02 PM PST 24 |
| Finished | Feb 21 01:05:29 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-baa37332-246e-44ed-be13-49372fca1e47 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720563549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.1720563549 |
| Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.2113594965 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 399279355 ps |
| CPU time | 13.33 seconds |
| Started | Feb 21 12:57:57 PM PST 24 |
| Finished | Feb 21 12:58:11 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-37c8000c-feb1-4b88-89b4-ba148e8354e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113594965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2113594965 |
| Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_regwen.3303240171 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 18474274077 ps |
| CPU time | 288.24 seconds |
| Started | Feb 21 12:57:55 PM PST 24 |
| Finished | Feb 21 01:02:43 PM PST 24 |
| Peak memory | 366048 kb |
| Host | smart-3f487065-de8f-492e-a289-dcd98477d552 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303240171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3303240171 |
| Directory | /workspace/21.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_smoke.3035850807 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1441072480 ps |
| CPU time | 92.64 seconds |
| Started | Feb 21 12:57:53 PM PST 24 |
| Finished | Feb 21 12:59:26 PM PST 24 |
| Peak memory | 361856 kb |
| Host | smart-56bcc97f-3b9a-45c4-bb67-acb2df26b24b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035850807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3035850807 |
| Directory | /workspace/21.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2228808121 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 56601338246 ps |
| CPU time | 500.66 seconds |
| Started | Feb 21 12:57:55 PM PST 24 |
| Finished | Feb 21 01:06:16 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-4a2fbece-47c7-477b-92aa-6a943f01fce6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228808121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.2228808121 |
| Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.135582948 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 11559424861 ps |
| CPU time | 34.6 seconds |
| Started | Feb 21 12:57:58 PM PST 24 |
| Finished | Feb 21 12:58:34 PM PST 24 |
| Peak memory | 241268 kb |
| Host | smart-39ba62b5-660d-444a-817e-4c7c9b13d8cb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135582948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.135582948 |
| Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3609368463 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 11448039284 ps |
| CPU time | 845.72 seconds |
| Started | Feb 21 12:57:56 PM PST 24 |
| Finished | Feb 21 01:12:02 PM PST 24 |
| Peak memory | 373268 kb |
| Host | smart-81f73e76-678d-4394-ac8e-885ae4d0b3c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609368463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.3609368463 |
| Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.2824368794 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 21549876 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:58:03 PM PST 24 |
| Finished | Feb 21 12:58:04 PM PST 24 |
| Peak memory | 201888 kb |
| Host | smart-7f08bb75-0663-4ce0-b63a-f877da23c17f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824368794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2824368794 |
| Directory | /workspace/22.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_bijection.3923129827 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 380116977305 ps |
| CPU time | 1312.19 seconds |
| Started | Feb 21 12:57:54 PM PST 24 |
| Finished | Feb 21 01:19:47 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-53dc9204-c51d-4927-919b-c2ce239602f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923129827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .3923129827 |
| Directory | /workspace/22.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.2721202264 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 113673844889 ps |
| CPU time | 109.78 seconds |
| Started | Feb 21 12:57:53 PM PST 24 |
| Finished | Feb 21 12:59:43 PM PST 24 |
| Peak memory | 210612 kb |
| Host | smart-089d3854-41cb-48b7-8d64-50c3c5434eee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721202264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.2721202264 |
| Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.1863255481 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1566067384 ps |
| CPU time | 102.62 seconds |
| Started | Feb 21 12:58:02 PM PST 24 |
| Finished | Feb 21 12:59:45 PM PST 24 |
| Peak memory | 364968 kb |
| Host | smart-43383f91-b95b-449d-88a7-f4720b9d6c31 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863255481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.1863255481 |
| Directory | /workspace/22.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.117538098 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3126145496 ps |
| CPU time | 126.17 seconds |
| Started | Feb 21 12:58:06 PM PST 24 |
| Finished | Feb 21 01:00:13 PM PST 24 |
| Peak memory | 214364 kb |
| Host | smart-c3b8bce3-994c-48e5-986c-b6106ec25ed3 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117538098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_mem_partial_access.117538098 |
| Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.1743049295 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 14348203122 ps |
| CPU time | 292.13 seconds |
| Started | Feb 21 12:58:04 PM PST 24 |
| Finished | Feb 21 01:02:56 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-9dd4cdd5-1948-42ea-ae38-232ca1d915e8 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743049295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.1743049295 |
| Directory | /workspace/22.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.643991522 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 20408129264 ps |
| CPU time | 326.15 seconds |
| Started | Feb 21 12:57:56 PM PST 24 |
| Finished | Feb 21 01:03:22 PM PST 24 |
| Peak memory | 378244 kb |
| Host | smart-c900e7b4-7966-427f-b03f-3a4794beadaf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643991522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip le_keys.643991522 |
| Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.923938700 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 751672592 ps |
| CPU time | 15.35 seconds |
| Started | Feb 21 12:57:54 PM PST 24 |
| Finished | Feb 21 12:58:09 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-c22045cd-ad64-4ef0-9937-0a47e372fe9b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923938700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s ram_ctrl_partial_access.923938700 |
| Directory | /workspace/22.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1463243049 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 15374932996 ps |
| CPU time | 363.75 seconds |
| Started | Feb 21 12:57:56 PM PST 24 |
| Finished | Feb 21 01:04:00 PM PST 24 |
| Peak memory | 216404 kb |
| Host | smart-f29b77c7-3d0a-447a-bc8f-641fbd173afb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463243049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.1463243049 |
| Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.1393827144 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 362347135 ps |
| CPU time | 12.33 seconds |
| Started | Feb 21 12:58:05 PM PST 24 |
| Finished | Feb 21 12:58:18 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-df2b659b-6532-4baf-aed6-6ac9deb82780 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393827144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1393827144 |
| Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_regwen.1348453892 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4493950694 ps |
| CPU time | 346.63 seconds |
| Started | Feb 21 12:57:56 PM PST 24 |
| Finished | Feb 21 01:03:43 PM PST 24 |
| Peak memory | 369064 kb |
| Host | smart-ca97e5c6-ed54-4238-a13d-1d8acd16930c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348453892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1348453892 |
| Directory | /workspace/22.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_smoke.1264264349 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 902621191 ps |
| CPU time | 92.41 seconds |
| Started | Feb 21 12:57:57 PM PST 24 |
| Finished | Feb 21 12:59:30 PM PST 24 |
| Peak memory | 352580 kb |
| Host | smart-0f8b3ef1-2e9b-4ed9-9e3b-acf3f5aa003e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264264349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1264264349 |
| Directory | /workspace/22.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.3323012786 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 415091831741 ps |
| CPU time | 7548.43 seconds |
| Started | Feb 21 12:58:04 PM PST 24 |
| Finished | Feb 21 03:03:54 PM PST 24 |
| Peak memory | 388508 kb |
| Host | smart-e8898f11-b7fe-4f8f-9ad5-e7abf551c857 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323012786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.3323012786 |
| Directory | /workspace/22.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.710737603 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 7763807343 ps |
| CPU time | 280.78 seconds |
| Started | Feb 21 12:57:55 PM PST 24 |
| Finished | Feb 21 01:02:36 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-c76e72d0-7df9-4b77-9b2b-d195936c123e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710737603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.710737603 |
| Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3452374904 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 818446947 ps |
| CPU time | 137.78 seconds |
| Started | Feb 21 12:57:58 PM PST 24 |
| Finished | Feb 21 01:00:17 PM PST 24 |
| Peak memory | 371352 kb |
| Host | smart-2c555501-7ca2-4c8b-8e50-b272d0733d06 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452374904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3452374904 |
| Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2025952871 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 8353781955 ps |
| CPU time | 1029.02 seconds |
| Started | Feb 21 12:58:05 PM PST 24 |
| Finished | Feb 21 01:15:14 PM PST 24 |
| Peak memory | 378272 kb |
| Host | smart-8cc80886-62d4-414f-ab73-a03b8e9f2d9f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025952871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.2025952871 |
| Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.1606656005 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 50951204 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:58:05 PM PST 24 |
| Finished | Feb 21 12:58:06 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-89f691d3-e0fd-44f8-972f-3d69dc3360e5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606656005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1606656005 |
| Directory | /workspace/23.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_bijection.1571050681 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 41684722551 ps |
| CPU time | 1340.74 seconds |
| Started | Feb 21 12:58:08 PM PST 24 |
| Finished | Feb 21 01:20:29 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-8d7bd836-0e08-45fc-a491-732c228e25fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571050681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .1571050681 |
| Directory | /workspace/23.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_executable.3529161959 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 100819968618 ps |
| CPU time | 716.66 seconds |
| Started | Feb 21 12:58:05 PM PST 24 |
| Finished | Feb 21 01:10:03 PM PST 24 |
| Peak memory | 366984 kb |
| Host | smart-abf23b6e-dca6-4bd6-ad46-fc067df47183 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529161959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.3529161959 |
| Directory | /workspace/23.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.1239377136 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 31318242769 ps |
| CPU time | 74.3 seconds |
| Started | Feb 21 12:58:08 PM PST 24 |
| Finished | Feb 21 12:59:23 PM PST 24 |
| Peak memory | 210632 kb |
| Host | smart-9ffd0a1e-0d2d-46d3-b43a-76cfcc86cc4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239377136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.1239377136 |
| Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.2934936074 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 731894696 ps |
| CPU time | 69.36 seconds |
| Started | Feb 21 12:58:06 PM PST 24 |
| Finished | Feb 21 12:59:16 PM PST 24 |
| Peak memory | 291712 kb |
| Host | smart-ea8753b4-4386-48c4-8f80-a5f864552c51 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934936074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2934936074 |
| Directory | /workspace/23.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.454646710 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1569569178 ps |
| CPU time | 134.41 seconds |
| Started | Feb 21 12:58:04 PM PST 24 |
| Finished | Feb 21 01:00:20 PM PST 24 |
| Peak memory | 214312 kb |
| Host | smart-fcc3c99c-9f0f-488e-8434-2522109c674d |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454646710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sram_ctrl_mem_partial_access.454646710 |
| Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.2593207357 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 20653956753 ps |
| CPU time | 292.49 seconds |
| Started | Feb 21 12:58:05 PM PST 24 |
| Finished | Feb 21 01:02:58 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-73d2da89-72ec-4723-9a94-4125d97acee2 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593207357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.2593207357 |
| Directory | /workspace/23.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.810706774 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 171786686831 ps |
| CPU time | 1035.29 seconds |
| Started | Feb 21 12:58:03 PM PST 24 |
| Finished | Feb 21 01:15:19 PM PST 24 |
| Peak memory | 378264 kb |
| Host | smart-ac9a0e6f-51c7-442e-84d1-587cb2d56be5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810706774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip le_keys.810706774 |
| Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.4267648516 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 874014586 ps |
| CPU time | 13.74 seconds |
| Started | Feb 21 12:58:08 PM PST 24 |
| Finished | Feb 21 12:58:22 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-f67ef4a0-c70c-439b-a46d-c1b1ca014182 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267648516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.4267648516 |
| Directory | /workspace/23.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2408429564 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3916419962 ps |
| CPU time | 250.42 seconds |
| Started | Feb 21 12:58:04 PM PST 24 |
| Finished | Feb 21 01:02:15 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-627e90a6-12c5-4b74-9261-62a490f9533f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408429564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.2408429564 |
| Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.349366481 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1466811597 ps |
| CPU time | 14.36 seconds |
| Started | Feb 21 12:58:03 PM PST 24 |
| Finished | Feb 21 12:58:18 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-8755f636-2235-4321-b010-d5f93be5c3a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349366481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.349366481 |
| Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_regwen.3876995235 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 14896120843 ps |
| CPU time | 847.28 seconds |
| Started | Feb 21 12:58:05 PM PST 24 |
| Finished | Feb 21 01:12:12 PM PST 24 |
| Peak memory | 379308 kb |
| Host | smart-5b6d42d4-fbe4-4cad-9fcb-4d2580f5fbbb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876995235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3876995235 |
| Directory | /workspace/23.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_smoke.1878093546 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3497612482 ps |
| CPU time | 41.2 seconds |
| Started | Feb 21 12:58:06 PM PST 24 |
| Finished | Feb 21 12:58:48 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-b835e9dd-4f14-43ab-a343-297cb73db0fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878093546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1878093546 |
| Directory | /workspace/23.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3858164485 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9750743977 ps |
| CPU time | 385.86 seconds |
| Started | Feb 21 12:58:08 PM PST 24 |
| Finished | Feb 21 01:04:35 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-0957a87f-b5b3-4a87-9603-937636ae09e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858164485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3858164485 |
| Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1011345533 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1513512817 ps |
| CPU time | 62.21 seconds |
| Started | Feb 21 12:58:08 PM PST 24 |
| Finished | Feb 21 12:59:11 PM PST 24 |
| Peak memory | 309436 kb |
| Host | smart-024c1f2b-2e8f-4243-9089-8e1804defff1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011345533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1011345533 |
| Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.247159688 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 12814572828 ps |
| CPU time | 1795.28 seconds |
| Started | Feb 21 12:58:21 PM PST 24 |
| Finished | Feb 21 01:28:18 PM PST 24 |
| Peak memory | 377168 kb |
| Host | smart-90fcf7ff-d8f4-4fc1-a8d1-ab8f7b3c3dbb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247159688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 24.sram_ctrl_access_during_key_req.247159688 |
| Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.2195964832 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 27164850 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:58:20 PM PST 24 |
| Finished | Feb 21 12:58:21 PM PST 24 |
| Peak memory | 202140 kb |
| Host | smart-23a0fbae-8380-40bd-aba5-40d21c04ea88 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195964832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2195964832 |
| Directory | /workspace/24.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_bijection.372755366 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 53788573470 ps |
| CPU time | 956.8 seconds |
| Started | Feb 21 12:58:21 PM PST 24 |
| Finished | Feb 21 01:14:19 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-9fa3129a-c28d-4539-880c-a26ebc0079ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372755366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection. 372755366 |
| Directory | /workspace/24.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_executable.3108946825 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 46764429543 ps |
| CPU time | 440.02 seconds |
| Started | Feb 21 12:58:23 PM PST 24 |
| Finished | Feb 21 01:05:43 PM PST 24 |
| Peak memory | 363476 kb |
| Host | smart-9eadc174-8f94-4c82-8498-e0107ad0154c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108946825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3108946825 |
| Directory | /workspace/24.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.1712299865 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 767653418 ps |
| CPU time | 145.92 seconds |
| Started | Feb 21 12:58:21 PM PST 24 |
| Finished | Feb 21 01:00:47 PM PST 24 |
| Peak memory | 364016 kb |
| Host | smart-c5a9f2a2-4653-4aba-be71-1f81802c2d72 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712299865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.1712299865 |
| Directory | /workspace/24.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1263445923 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 8622785636 ps |
| CPU time | 74.51 seconds |
| Started | Feb 21 12:58:21 PM PST 24 |
| Finished | Feb 21 12:59:36 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-edcf32cb-7c83-4412-bd75-9130173bb7c5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263445923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1263445923 |
| Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.3342048836 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 73690181705 ps |
| CPU time | 312.57 seconds |
| Started | Feb 21 12:58:19 PM PST 24 |
| Finished | Feb 21 01:03:33 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-0fe1ffc3-f857-4c73-ada9-4ee25227310c |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342048836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.3342048836 |
| Directory | /workspace/24.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.1742026367 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 20127049440 ps |
| CPU time | 316.85 seconds |
| Started | Feb 21 12:58:22 PM PST 24 |
| Finished | Feb 21 01:03:39 PM PST 24 |
| Peak memory | 323836 kb |
| Host | smart-a7b37008-0885-4e0d-9f52-bb00ca052b44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742026367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.1742026367 |
| Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.597383980 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1221081221 ps |
| CPU time | 21.46 seconds |
| Started | Feb 21 12:58:20 PM PST 24 |
| Finished | Feb 21 12:58:42 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-2d4f9193-7e4e-4fd8-a94e-aff48e80a16f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597383980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s ram_ctrl_partial_access.597383980 |
| Directory | /workspace/24.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2387511856 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 93892567699 ps |
| CPU time | 377.94 seconds |
| Started | Feb 21 12:58:19 PM PST 24 |
| Finished | Feb 21 01:04:38 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-4c4747bc-116b-47aa-bfe4-088cefc384f6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387511856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.2387511856 |
| Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.4244232645 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1404723727 ps |
| CPU time | 5.46 seconds |
| Started | Feb 21 12:58:19 PM PST 24 |
| Finished | Feb 21 12:58:25 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-cf50e9ed-1730-4110-84f5-ba677692d8a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244232645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.4244232645 |
| Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_regwen.3366221641 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 66351471197 ps |
| CPU time | 1499.06 seconds |
| Started | Feb 21 12:58:22 PM PST 24 |
| Finished | Feb 21 01:23:22 PM PST 24 |
| Peak memory | 380424 kb |
| Host | smart-40f52a10-8be5-48cd-ac16-0cdec234cd63 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366221641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3366221641 |
| Directory | /workspace/24.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_smoke.1496927606 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 735474649 ps |
| CPU time | 31.29 seconds |
| Started | Feb 21 12:58:04 PM PST 24 |
| Finished | Feb 21 12:58:35 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-6e2355bc-76e6-4409-b446-d7628da062d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496927606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1496927606 |
| Directory | /workspace/24.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1247202867 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3523744342 ps |
| CPU time | 232.79 seconds |
| Started | Feb 21 12:58:21 PM PST 24 |
| Finished | Feb 21 01:02:15 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-39b7d6f7-bfaf-4710-b83f-17b1f1cfa6fb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247202867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.1247202867 |
| Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1894786266 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 827952926 ps |
| CPU time | 145.35 seconds |
| Started | Feb 21 12:58:23 PM PST 24 |
| Finished | Feb 21 01:00:49 PM PST 24 |
| Peak memory | 370116 kb |
| Host | smart-dc2534be-3b78-430f-ad47-69fbccc621f4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894786266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1894786266 |
| Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.5270476 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5835853359 ps |
| CPU time | 511.15 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 01:07:01 PM PST 24 |
| Peak memory | 373912 kb |
| Host | smart-c7a2d971-6448-4ddc-b6ce-693ddb7cf9b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5270476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.sram_ctrl_access_during_key_req.5270476 |
| Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.1539251715 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 15071623 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 12:58:30 PM PST 24 |
| Peak memory | 201944 kb |
| Host | smart-bd829c44-1b2b-4818-8cfc-d93208cab007 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539251715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1539251715 |
| Directory | /workspace/25.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_bijection.4003098756 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 32490622843 ps |
| CPU time | 753 seconds |
| Started | Feb 21 12:58:19 PM PST 24 |
| Finished | Feb 21 01:10:53 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-4c60018c-ef43-4301-a5d6-30e1cf8883e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003098756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .4003098756 |
| Directory | /workspace/25.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.1901341086 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 9910836512 ps |
| CPU time | 93.39 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 01:00:01 PM PST 24 |
| Peak memory | 210588 kb |
| Host | smart-87e808f4-5b3e-4c4a-bc82-0d5af0dd8423 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901341086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.1901341086 |
| Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.1212560499 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 6628139609 ps |
| CPU time | 72.9 seconds |
| Started | Feb 21 12:58:22 PM PST 24 |
| Finished | Feb 21 12:59:35 PM PST 24 |
| Peak memory | 309200 kb |
| Host | smart-5d044e0a-9eb9-4f69-967a-3d3313bbfe2b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212560499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.1212560499 |
| Directory | /workspace/25.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3814960333 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 19779565504 ps |
| CPU time | 142.25 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 01:00:51 PM PST 24 |
| Peak memory | 211464 kb |
| Host | smart-a8ce74dc-8d4d-43d1-a0c0-e6e2bae03bcc |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814960333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3814960333 |
| Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.2000259723 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2064681290 ps |
| CPU time | 116.92 seconds |
| Started | Feb 21 12:58:30 PM PST 24 |
| Finished | Feb 21 01:00:27 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-c63f1fcf-33fd-4ba7-9a72-bafc3ab5357b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000259723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.2000259723 |
| Directory | /workspace/25.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.2441211721 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 49531021997 ps |
| CPU time | 1654.39 seconds |
| Started | Feb 21 12:58:19 PM PST 24 |
| Finished | Feb 21 01:25:54 PM PST 24 |
| Peak memory | 378440 kb |
| Host | smart-386218e6-4f69-4e52-8420-e7725a550c1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441211721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.2441211721 |
| Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.2809749077 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 865589966 ps |
| CPU time | 28.07 seconds |
| Started | Feb 21 12:58:22 PM PST 24 |
| Finished | Feb 21 12:58:51 PM PST 24 |
| Peak memory | 262648 kb |
| Host | smart-b5043042-b479-4d3b-baee-7f975e1caf32 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809749077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.2809749077 |
| Directory | /workspace/25.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.752135320 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 12104763689 ps |
| CPU time | 355.7 seconds |
| Started | Feb 21 12:58:19 PM PST 24 |
| Finished | Feb 21 01:04:16 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-edc32505-ba23-4437-9794-2895ab11c754 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752135320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.sram_ctrl_partial_access_b2b.752135320 |
| Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.3794227273 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1246398020 ps |
| CPU time | 6.31 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 12:58:36 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-45d67fe5-06de-4be6-abfc-8f9f248dfe25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794227273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3794227273 |
| Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_regwen.2430701748 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2270312587 ps |
| CPU time | 426.46 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 01:05:35 PM PST 24 |
| Peak memory | 371160 kb |
| Host | smart-2fccbe4b-3d8e-425f-9fc6-288606ba6917 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430701748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2430701748 |
| Directory | /workspace/25.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_smoke.2258267304 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2132802105 ps |
| CPU time | 18.98 seconds |
| Started | Feb 21 12:58:19 PM PST 24 |
| Finished | Feb 21 12:58:39 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-c16419c3-c09a-418c-8d48-d5abf8ed7f99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258267304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2258267304 |
| Directory | /workspace/25.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.821609251 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 105801259981 ps |
| CPU time | 5116.08 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 02:23:47 PM PST 24 |
| Peak memory | 387520 kb |
| Host | smart-0ba1b525-4fba-4bbe-8a1b-a365acf16492 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821609251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_stress_all.821609251 |
| Directory | /workspace/25.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2229320635 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 4531817606 ps |
| CPU time | 330.65 seconds |
| Started | Feb 21 12:58:22 PM PST 24 |
| Finished | Feb 21 01:03:53 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-a1c84f11-3165-42c1-9d4c-eb84c4e78a77 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229320635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.2229320635 |
| Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.760230075 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 12295394779 ps |
| CPU time | 70.3 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 12:59:40 PM PST 24 |
| Peak memory | 303616 kb |
| Host | smart-94cb5f4a-8b5b-4d93-8a59-39ed378f4810 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760230075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.760230075 |
| Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2216787401 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 10196177896 ps |
| CPU time | 1324.45 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 01:20:34 PM PST 24 |
| Peak memory | 377476 kb |
| Host | smart-5dcec186-eb50-44a3-86c7-3d476ae526e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216787401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.2216787401 |
| Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.1446187185 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 38462113 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 12:58:29 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-31fefacf-a117-43ff-8391-17918a07860a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446187185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1446187185 |
| Directory | /workspace/26.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_bijection.670823003 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 30405390007 ps |
| CPU time | 2090.32 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 01:33:20 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-77b55831-be88-4638-82bd-e47341aa934b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670823003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 670823003 |
| Directory | /workspace/26.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_executable.814692375 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 16813913915 ps |
| CPU time | 998.84 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 01:15:07 PM PST 24 |
| Peak memory | 370104 kb |
| Host | smart-85f0ee65-7643-4696-9d14-c33b30839b20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814692375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.814692375 |
| Directory | /workspace/26.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.2495535865 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 12655338733 ps |
| CPU time | 32.92 seconds |
| Started | Feb 21 12:58:27 PM PST 24 |
| Finished | Feb 21 12:59:01 PM PST 24 |
| Peak memory | 210600 kb |
| Host | smart-6284d897-7842-414e-b4ec-283ea682a657 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495535865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.2495535865 |
| Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.3800962555 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 720849539 ps |
| CPU time | 46.82 seconds |
| Started | Feb 21 12:58:32 PM PST 24 |
| Finished | Feb 21 12:59:20 PM PST 24 |
| Peak memory | 277860 kb |
| Host | smart-897d92e4-59ef-41f1-b24f-73aaf4de1edb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800962555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.3800962555 |
| Directory | /workspace/26.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1754440828 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 949455294 ps |
| CPU time | 70.44 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 12:59:39 PM PST 24 |
| Peak memory | 211488 kb |
| Host | smart-c9c5c17a-887a-472f-95dc-f9f3bb0be9b1 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754440828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.1754440828 |
| Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.677362101 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4112350877 ps |
| CPU time | 118.41 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 01:00:29 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-cf106628-429a-4800-ad57-cb551d8276ec |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677362101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _mem_walk.677362101 |
| Directory | /workspace/26.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.3984986239 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 12267779641 ps |
| CPU time | 1691.64 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 01:26:40 PM PST 24 |
| Peak memory | 378332 kb |
| Host | smart-2c7acf6d-2082-410c-8ce7-5caeba7c7b02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984986239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3984986239 |
| Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.1787020999 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1906551944 ps |
| CPU time | 154.93 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 01:01:05 PM PST 24 |
| Peak memory | 366864 kb |
| Host | smart-6477b421-32e2-4ad3-95be-d1fc2f6f1232 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787020999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.1787020999 |
| Directory | /workspace/26.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.670655988 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 96530830878 ps |
| CPU time | 446.52 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 01:05:56 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-275b0f06-f1b2-4fa5-90cc-81fe723917e2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670655988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.sram_ctrl_partial_access_b2b.670655988 |
| Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.740470524 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 348942872 ps |
| CPU time | 13.43 seconds |
| Started | Feb 21 12:58:30 PM PST 24 |
| Finished | Feb 21 12:58:44 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-a23742d8-2821-4e34-b6c1-fe9ad01813c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740470524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.740470524 |
| Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_regwen.2455676815 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 19145990761 ps |
| CPU time | 206.15 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 01:01:54 PM PST 24 |
| Peak memory | 361300 kb |
| Host | smart-74bfb27b-4b1b-4641-a39e-dca0aace3681 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455676815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2455676815 |
| Directory | /workspace/26.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_smoke.4041433982 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4330431758 ps |
| CPU time | 33.93 seconds |
| Started | Feb 21 12:58:28 PM PST 24 |
| Finished | Feb 21 12:59:02 PM PST 24 |
| Peak memory | 240596 kb |
| Host | smart-63ef08dc-8698-495d-b7dc-e851137d3679 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041433982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.4041433982 |
| Directory | /workspace/26.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.4245066012 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 61501228936 ps |
| CPU time | 418.8 seconds |
| Started | Feb 21 12:58:30 PM PST 24 |
| Finished | Feb 21 01:05:30 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-3e244e2f-b032-4835-a86d-268b77113a83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245066012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.4245066012 |
| Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4141064455 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3126023428 ps |
| CPU time | 44.22 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 12:59:14 PM PST 24 |
| Peak memory | 273252 kb |
| Host | smart-f710bae5-d17f-484c-84a2-a6ea27811815 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141064455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.4141064455 |
| Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3192869914 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 13851838448 ps |
| CPU time | 579.58 seconds |
| Started | Feb 21 12:58:43 PM PST 24 |
| Finished | Feb 21 01:08:23 PM PST 24 |
| Peak memory | 354640 kb |
| Host | smart-8f6cde88-d00f-4bca-a2e4-cf6445f0afeb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192869914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.3192869914 |
| Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.2915023901 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 48191088 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:58:42 PM PST 24 |
| Finished | Feb 21 12:58:43 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-6513a9cb-5020-4058-a2db-be8ad2a78740 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915023901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.2915023901 |
| Directory | /workspace/27.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_bijection.129144122 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 41697694776 ps |
| CPU time | 1418.98 seconds |
| Started | Feb 21 12:58:29 PM PST 24 |
| Finished | Feb 21 01:22:09 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-f6786620-b9b3-4c36-bd88-4d790078446b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129144122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection. 129144122 |
| Directory | /workspace/27.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_executable.655637288 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 73803193022 ps |
| CPU time | 730.1 seconds |
| Started | Feb 21 12:58:39 PM PST 24 |
| Finished | Feb 21 01:10:50 PM PST 24 |
| Peak memory | 374824 kb |
| Host | smart-c3856418-c4d1-4090-808d-b49b65f0b550 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655637288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl e.655637288 |
| Directory | /workspace/27.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.901553467 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2374271446 ps |
| CPU time | 81.75 seconds |
| Started | Feb 21 12:58:40 PM PST 24 |
| Finished | Feb 21 01:00:02 PM PST 24 |
| Peak memory | 312856 kb |
| Host | smart-60be1398-773f-4adf-9580-9fa383510909 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901553467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_max_throughput.901553467 |
| Directory | /workspace/27.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.809857832 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 962013346 ps |
| CPU time | 72.81 seconds |
| Started | Feb 21 12:58:39 PM PST 24 |
| Finished | Feb 21 12:59:52 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-90c48c45-b792-4967-bc48-bd68844ad349 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809857832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_mem_partial_access.809857832 |
| Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.32672698 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 8224048569 ps |
| CPU time | 122.68 seconds |
| Started | Feb 21 12:58:40 PM PST 24 |
| Finished | Feb 21 01:00:43 PM PST 24 |
| Peak memory | 202276 kb |
| Host | smart-c65b0f65-01a4-4c72-ae15-c4ada982e401 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ mem_walk.32672698 |
| Directory | /workspace/27.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.3355478137 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 99877161818 ps |
| CPU time | 458.87 seconds |
| Started | Feb 21 12:58:27 PM PST 24 |
| Finished | Feb 21 01:06:06 PM PST 24 |
| Peak memory | 369964 kb |
| Host | smart-520664d7-855c-4978-9861-0687cff8efa0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355478137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.3355478137 |
| Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.60999950 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 782015345 ps |
| CPU time | 64.22 seconds |
| Started | Feb 21 12:58:41 PM PST 24 |
| Finished | Feb 21 12:59:46 PM PST 24 |
| Peak memory | 302468 kb |
| Host | smart-3aa4c174-a93d-437c-af90-448b12a9c010 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60999950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sr am_ctrl_partial_access.60999950 |
| Directory | /workspace/27.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3797945036 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 77447261278 ps |
| CPU time | 456.12 seconds |
| Started | Feb 21 12:58:40 PM PST 24 |
| Finished | Feb 21 01:06:17 PM PST 24 |
| Peak memory | 210584 kb |
| Host | smart-c0798ab8-63e3-4120-ac7a-73ab3878be17 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797945036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.3797945036 |
| Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.544383489 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 405636139 ps |
| CPU time | 5.6 seconds |
| Started | Feb 21 12:58:39 PM PST 24 |
| Finished | Feb 21 12:58:45 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-6e7f8681-765c-474d-a024-0df8b4e5349f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544383489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.544383489 |
| Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_regwen.205990572 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 87766314195 ps |
| CPU time | 1254.54 seconds |
| Started | Feb 21 12:58:40 PM PST 24 |
| Finished | Feb 21 01:19:35 PM PST 24 |
| Peak memory | 380376 kb |
| Host | smart-28793217-26fe-47d5-a8c8-391d503f2ea1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205990572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.205990572 |
| Directory | /workspace/27.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_smoke.84626859 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 779899374 ps |
| CPU time | 49.8 seconds |
| Started | Feb 21 12:58:31 PM PST 24 |
| Finished | Feb 21 12:59:21 PM PST 24 |
| Peak memory | 316704 kb |
| Host | smart-aed68583-7bab-43d6-ae7e-7d127318dd80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84626859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.84626859 |
| Directory | /workspace/27.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.3336979814 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 331237534574 ps |
| CPU time | 3793.41 seconds |
| Started | Feb 21 12:58:45 PM PST 24 |
| Finished | Feb 21 02:01:59 PM PST 24 |
| Peak memory | 218388 kb |
| Host | smart-c9ec765b-0bdf-4d0d-854f-f6b06823d4a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336979814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.3336979814 |
| Directory | /workspace/27.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1383615983 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 19478747824 ps |
| CPU time | 377.43 seconds |
| Started | Feb 21 12:58:31 PM PST 24 |
| Finished | Feb 21 01:04:49 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-cb623b56-447c-444f-9ea7-48bf903dc3f9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383615983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.1383615983 |
| Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3660109319 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 710266545 ps |
| CPU time | 40.87 seconds |
| Started | Feb 21 12:58:41 PM PST 24 |
| Finished | Feb 21 12:59:22 PM PST 24 |
| Peak memory | 257308 kb |
| Host | smart-0f2b1354-0fbd-4cae-b71f-03b6700a2dfe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660109319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3660109319 |
| Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.4225527298 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 21130420321 ps |
| CPU time | 790.11 seconds |
| Started | Feb 21 12:58:43 PM PST 24 |
| Finished | Feb 21 01:11:54 PM PST 24 |
| Peak memory | 378200 kb |
| Host | smart-b72adc96-5a56-4b14-8f2f-95082cc5a9ec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225527298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.4225527298 |
| Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.3549126792 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 62089026 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:59:02 PM PST 24 |
| Finished | Feb 21 12:59:04 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-ba89bf4f-3276-491a-8e8f-a0538f43f389 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549126792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3549126792 |
| Directory | /workspace/28.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_bijection.857341711 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 27549752419 ps |
| CPU time | 1784.38 seconds |
| Started | Feb 21 12:58:41 PM PST 24 |
| Finished | Feb 21 01:28:25 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-cfdced51-c4b4-485e-a07b-955095c466d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857341711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection. 857341711 |
| Directory | /workspace/28.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.3633317026 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 33587471521 ps |
| CPU time | 96.85 seconds |
| Started | Feb 21 12:58:45 PM PST 24 |
| Finished | Feb 21 01:00:22 PM PST 24 |
| Peak memory | 214228 kb |
| Host | smart-0335562a-bdad-468d-a17a-2916e4e99141 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633317026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.3633317026 |
| Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.1555623962 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 766094493 ps |
| CPU time | 87.47 seconds |
| Started | Feb 21 12:58:41 PM PST 24 |
| Finished | Feb 21 01:00:09 PM PST 24 |
| Peak memory | 312788 kb |
| Host | smart-f678bbe2-9324-4a38-accf-cdf172995824 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555623962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.1555623962 |
| Directory | /workspace/28.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2424784747 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 992715954 ps |
| CPU time | 73.63 seconds |
| Started | Feb 21 12:58:39 PM PST 24 |
| Finished | Feb 21 12:59:53 PM PST 24 |
| Peak memory | 211256 kb |
| Host | smart-38066ecc-a10d-477c-a5f9-efef00328d76 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424784747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.2424784747 |
| Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.3256890012 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 6957230960 ps |
| CPU time | 143.3 seconds |
| Started | Feb 21 12:58:42 PM PST 24 |
| Finished | Feb 21 01:01:06 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-1e61c7ab-e992-4fd8-8f00-be472747a12b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256890012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.3256890012 |
| Directory | /workspace/28.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.3492897430 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3236117251 ps |
| CPU time | 392.35 seconds |
| Started | Feb 21 12:58:45 PM PST 24 |
| Finished | Feb 21 01:05:18 PM PST 24 |
| Peak memory | 375696 kb |
| Host | smart-eb2ac75d-a1d8-4806-9d81-eb7674ab6394 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492897430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.3492897430 |
| Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.770994823 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2814673348 ps |
| CPU time | 13.69 seconds |
| Started | Feb 21 12:58:37 PM PST 24 |
| Finished | Feb 21 12:58:51 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-337f1214-02ab-486e-b0c5-56c2fe7be012 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770994823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s ram_ctrl_partial_access.770994823 |
| Directory | /workspace/28.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1749729617 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 12477316978 ps |
| CPU time | 267.29 seconds |
| Started | Feb 21 12:58:38 PM PST 24 |
| Finished | Feb 21 01:03:06 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-6467e398-966a-4889-8715-a663fce56b62 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749729617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.1749729617 |
| Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.3768919161 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 346435518 ps |
| CPU time | 6.24 seconds |
| Started | Feb 21 12:58:43 PM PST 24 |
| Finished | Feb 21 12:58:49 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-8e395377-fbf7-4e8b-b2b2-c52f6576f299 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768919161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3768919161 |
| Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3292646794 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5350077806 ps |
| CPU time | 373.38 seconds |
| Started | Feb 21 12:58:42 PM PST 24 |
| Finished | Feb 21 01:04:56 PM PST 24 |
| Peak memory | 376300 kb |
| Host | smart-c45efabb-5e1f-4291-b9d6-a6b2d441d53b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292646794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3292646794 |
| Directory | /workspace/28.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_smoke.409544761 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 6036201328 ps |
| CPU time | 59.55 seconds |
| Started | Feb 21 12:58:43 PM PST 24 |
| Finished | Feb 21 12:59:43 PM PST 24 |
| Peak memory | 297464 kb |
| Host | smart-f1f0a386-afb9-4f00-8bef-2bb5ba9b1dd3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409544761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.409544761 |
| Directory | /workspace/28.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.2337193358 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 87524830877 ps |
| CPU time | 2766.67 seconds |
| Started | Feb 21 12:59:02 PM PST 24 |
| Finished | Feb 21 01:45:10 PM PST 24 |
| Peak memory | 376240 kb |
| Host | smart-a967f3b7-d884-4219-92e0-adac4c5a3879 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337193358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.2337193358 |
| Directory | /workspace/28.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3257843435 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 30870629460 ps |
| CPU time | 172.05 seconds |
| Started | Feb 21 12:58:40 PM PST 24 |
| Finished | Feb 21 01:01:32 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-6c0ba8f8-9955-4934-8399-e779de217265 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257843435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.3257843435 |
| Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2288166336 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 689936417 ps |
| CPU time | 25.28 seconds |
| Started | Feb 21 12:58:46 PM PST 24 |
| Finished | Feb 21 12:59:11 PM PST 24 |
| Peak memory | 210504 kb |
| Host | smart-efb18430-4dcd-493a-b480-d58ebcd9b105 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288166336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2288166336 |
| Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1530598193 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 9646400935 ps |
| CPU time | 897.77 seconds |
| Started | Feb 21 12:59:02 PM PST 24 |
| Finished | Feb 21 01:14:01 PM PST 24 |
| Peak memory | 355728 kb |
| Host | smart-0804e8f0-f3bc-4aec-9acb-1653dbdb4210 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530598193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.1530598193 |
| Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.1174468236 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 39874843 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:58:59 PM PST 24 |
| Finished | Feb 21 12:59:00 PM PST 24 |
| Peak memory | 202128 kb |
| Host | smart-6be823d1-df12-4e31-988b-28ce039d9185 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174468236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1174468236 |
| Directory | /workspace/29.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_bijection.426528230 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 55435247595 ps |
| CPU time | 1258.79 seconds |
| Started | Feb 21 12:58:55 PM PST 24 |
| Finished | Feb 21 01:19:54 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-cb9efe13-647f-44d9-b9fa-99dbfbbffa67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426528230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection. 426528230 |
| Directory | /workspace/29.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.3152128203 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3863627821 ps |
| CPU time | 61.22 seconds |
| Started | Feb 21 12:58:58 PM PST 24 |
| Finished | Feb 21 12:59:59 PM PST 24 |
| Peak memory | 210688 kb |
| Host | smart-5fddf208-31f0-4414-bc01-398b6c31ec75 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152128203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.3152128203 |
| Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.1171945148 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 762287399 ps |
| CPU time | 67.01 seconds |
| Started | Feb 21 12:59:01 PM PST 24 |
| Finished | Feb 21 01:00:09 PM PST 24 |
| Peak memory | 309460 kb |
| Host | smart-3203f51a-c58b-48d6-ba54-6a53c69e6a82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171945148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.1171945148 |
| Directory | /workspace/29.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3153768185 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 6265905945 ps |
| CPU time | 137.47 seconds |
| Started | Feb 21 12:59:03 PM PST 24 |
| Finished | Feb 21 01:01:21 PM PST 24 |
| Peak memory | 214916 kb |
| Host | smart-54a9dd99-e760-414f-828e-dafd7a4dd8c8 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153768185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.3153768185 |
| Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.130229416 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 33108158956 ps |
| CPU time | 151.58 seconds |
| Started | Feb 21 12:59:01 PM PST 24 |
| Finished | Feb 21 01:01:33 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-a5411f44-afb8-469a-b858-bdf5e6f83059 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130229416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.130229416 |
| Directory | /workspace/29.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.3520621260 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1965755415 ps |
| CPU time | 231.37 seconds |
| Started | Feb 21 12:59:01 PM PST 24 |
| Finished | Feb 21 01:02:53 PM PST 24 |
| Peak memory | 371176 kb |
| Host | smart-18071022-4079-4007-bfd7-0ac45b81b949 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520621260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.3520621260 |
| Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.2527307041 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 4897356585 ps |
| CPU time | 24.19 seconds |
| Started | Feb 21 12:58:58 PM PST 24 |
| Finished | Feb 21 12:59:22 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-ae9c4c2b-4501-4c9f-a3c7-3ac3be63ecef |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527307041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.2527307041 |
| Directory | /workspace/29.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3152328808 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 70385443319 ps |
| CPU time | 413.95 seconds |
| Started | Feb 21 12:59:02 PM PST 24 |
| Finished | Feb 21 01:05:57 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-3a604204-3a86-4c75-9bd6-98368035958d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152328808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.3152328808 |
| Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.1117593824 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 918790573 ps |
| CPU time | 12.64 seconds |
| Started | Feb 21 12:59:01 PM PST 24 |
| Finished | Feb 21 12:59:14 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-47eba70c-1139-4a43-b06a-b124900388b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117593824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1117593824 |
| Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_regwen.2779054092 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 9092142890 ps |
| CPU time | 589.44 seconds |
| Started | Feb 21 12:58:58 PM PST 24 |
| Finished | Feb 21 01:08:47 PM PST 24 |
| Peak memory | 378348 kb |
| Host | smart-72ca8326-06a8-4406-a138-56d73424a28a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779054092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2779054092 |
| Directory | /workspace/29.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_smoke.3334645323 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2217475751 ps |
| CPU time | 40.64 seconds |
| Started | Feb 21 12:58:56 PM PST 24 |
| Finished | Feb 21 12:59:37 PM PST 24 |
| Peak memory | 291388 kb |
| Host | smart-a5f741d1-8d03-43cc-897c-f94aa6b60f2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334645323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3334645323 |
| Directory | /workspace/29.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1984110792 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 14369761612 ps |
| CPU time | 293.96 seconds |
| Started | Feb 21 12:59:02 PM PST 24 |
| Finished | Feb 21 01:03:57 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-ebbe7306-5a70-4602-a97e-80e7a8fe471d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984110792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.1984110792 |
| Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1151623322 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 776841606 ps |
| CPU time | 66.73 seconds |
| Started | Feb 21 12:59:01 PM PST 24 |
| Finished | Feb 21 01:00:09 PM PST 24 |
| Peak memory | 301496 kb |
| Host | smart-2ec4c299-0cc0-40b5-ad52-bdf0dd8b1e9f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151623322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1151623322 |
| Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3182553170 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 29800269153 ps |
| CPU time | 552.75 seconds |
| Started | Feb 21 12:56:43 PM PST 24 |
| Finished | Feb 21 01:05:57 PM PST 24 |
| Peak memory | 360804 kb |
| Host | smart-39f73310-8fe1-463f-9956-09a2f24ebc1a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182553170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.3182553170 |
| Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.1530901014 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 15152618 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:56:43 PM PST 24 |
| Finished | Feb 21 12:56:44 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-7c5d97cc-35e1-43e5-9df5-1f820718449b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530901014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1530901014 |
| Directory | /workspace/3.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_bijection.291077833 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 123089068903 ps |
| CPU time | 922.12 seconds |
| Started | Feb 21 12:56:36 PM PST 24 |
| Finished | Feb 21 01:11:58 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-ab95452a-8f3d-48b7-8de5-9939e46bc0b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291077833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.291077833 |
| Directory | /workspace/3.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_executable.1581852232 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 9747150044 ps |
| CPU time | 407.71 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 01:03:45 PM PST 24 |
| Peak memory | 364660 kb |
| Host | smart-c6512def-d12a-44ee-a608-256a72d8423a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581852232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1581852232 |
| Directory | /workspace/3.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.718229868 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 11806747499 ps |
| CPU time | 121.7 seconds |
| Started | Feb 21 12:56:47 PM PST 24 |
| Finished | Feb 21 12:58:49 PM PST 24 |
| Peak memory | 210652 kb |
| Host | smart-d28e4c56-43e2-4ce5-af86-20839eaedb81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718229868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca lation.718229868 |
| Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.1789260190 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2820397974 ps |
| CPU time | 40.21 seconds |
| Started | Feb 21 12:56:42 PM PST 24 |
| Finished | Feb 21 12:57:24 PM PST 24 |
| Peak memory | 259196 kb |
| Host | smart-144b8bf8-8b47-45a2-9449-a20f0d10af17 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789260190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.1789260190 |
| Directory | /workspace/3.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2815219671 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 4295614851 ps |
| CPU time | 72.02 seconds |
| Started | Feb 21 12:56:47 PM PST 24 |
| Finished | Feb 21 12:58:00 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-851f9c88-1c43-4f3e-ba9c-555179bcc1be |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815219671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.2815219671 |
| Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.525084880 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 57363160782 ps |
| CPU time | 272.51 seconds |
| Started | Feb 21 12:56:40 PM PST 24 |
| Finished | Feb 21 01:01:14 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-f16a07cb-fbd1-4245-943e-ca1774ff686a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525084880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.525084880 |
| Directory | /workspace/3.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.2164380738 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5274178153 ps |
| CPU time | 154.67 seconds |
| Started | Feb 21 12:56:31 PM PST 24 |
| Finished | Feb 21 12:59:06 PM PST 24 |
| Peak memory | 332620 kb |
| Host | smart-6886ed2d-cb27-4054-83da-f913c0789608 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164380738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2164380738 |
| Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.2166631504 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1164855325 ps |
| CPU time | 20.26 seconds |
| Started | Feb 21 12:56:29 PM PST 24 |
| Finished | Feb 21 12:56:49 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-e193c25e-4c22-4347-854c-57d7e10cfa56 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166631504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.2166631504 |
| Directory | /workspace/3.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1984158905 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 17148419829 ps |
| CPU time | 425.42 seconds |
| Started | Feb 21 12:56:41 PM PST 24 |
| Finished | Feb 21 01:03:47 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-8241ca79-1a06-4701-9cc9-a126f6ad8b54 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984158905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.1984158905 |
| Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.492558384 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 913836209 ps |
| CPU time | 5.75 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 12:56:52 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-83adf69a-0138-4a0a-aecb-f2d657439b2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492558384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.492558384 |
| Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_regwen.3549260973 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 27744863569 ps |
| CPU time | 993.61 seconds |
| Started | Feb 21 12:56:40 PM PST 24 |
| Finished | Feb 21 01:13:15 PM PST 24 |
| Peak memory | 375196 kb |
| Host | smart-c24cd172-7d80-41d4-8ac4-27d0ecc0420a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549260973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3549260973 |
| Directory | /workspace/3.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.329734959 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1576307824 ps |
| CPU time | 1.78 seconds |
| Started | Feb 21 12:56:45 PM PST 24 |
| Finished | Feb 21 12:56:48 PM PST 24 |
| Peak memory | 221752 kb |
| Host | smart-bb3b0af1-a507-41ae-a008-274515ca2bfe |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329734959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_sec_cm.329734959 |
| Directory | /workspace/3.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_smoke.898157085 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 408177563 ps |
| CPU time | 18.24 seconds |
| Started | Feb 21 12:56:36 PM PST 24 |
| Finished | Feb 21 12:56:54 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-fef9e1e9-341f-4b40-a2b5-5127e9380d02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898157085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.898157085 |
| Directory | /workspace/3.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.3299598428 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 38611005718 ps |
| CPU time | 2307.75 seconds |
| Started | Feb 21 12:56:42 PM PST 24 |
| Finished | Feb 21 01:35:11 PM PST 24 |
| Peak memory | 305844 kb |
| Host | smart-e4462736-70cc-4f5b-8dea-2b4e57d0450f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299598428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3299598428 |
| Directory | /workspace/3.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3676377472 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5178438225 ps |
| CPU time | 385.7 seconds |
| Started | Feb 21 12:56:32 PM PST 24 |
| Finished | Feb 21 01:02:58 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-20243885-27c1-4202-b74a-df1f4292b118 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676377472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.3676377472 |
| Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.536515691 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1443675581 ps |
| CPU time | 50.38 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 12:57:37 PM PST 24 |
| Peak memory | 275092 kb |
| Host | smart-a409f627-c8d1-4a47-81e6-551b75acd1f8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536515691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.536515691 |
| Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.582602864 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 24526245057 ps |
| CPU time | 281.91 seconds |
| Started | Feb 21 12:59:07 PM PST 24 |
| Finished | Feb 21 01:03:49 PM PST 24 |
| Peak memory | 347648 kb |
| Host | smart-67b2879e-75fe-4897-ba6b-9219a84045e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582602864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.sram_ctrl_access_during_key_req.582602864 |
| Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.1404687744 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 17278026 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:59:13 PM PST 24 |
| Finished | Feb 21 12:59:14 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-81ed27d5-e7b6-4d3d-850a-2995cd62d48c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404687744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1404687744 |
| Directory | /workspace/30.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_bijection.3027326209 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 18113316754 ps |
| CPU time | 1200.75 seconds |
| Started | Feb 21 12:59:15 PM PST 24 |
| Finished | Feb 21 01:19:16 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-a2fe7154-c016-44d6-875c-38f78f98622d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027326209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .3027326209 |
| Directory | /workspace/30.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_executable.328101026 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 30027755355 ps |
| CPU time | 417.33 seconds |
| Started | Feb 21 12:59:08 PM PST 24 |
| Finished | Feb 21 01:06:06 PM PST 24 |
| Peak memory | 349404 kb |
| Host | smart-b262ba10-51fe-40a2-b2b7-c776492c9171 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328101026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl e.328101026 |
| Directory | /workspace/30.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.231812493 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13673085161 ps |
| CPU time | 87.6 seconds |
| Started | Feb 21 12:59:06 PM PST 24 |
| Finished | Feb 21 01:00:34 PM PST 24 |
| Peak memory | 210696 kb |
| Host | smart-de654684-7bef-4fb2-a8af-99195c58a6c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231812493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc alation.231812493 |
| Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.3573053417 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3082319092 ps |
| CPU time | 88.52 seconds |
| Started | Feb 21 12:59:08 PM PST 24 |
| Finished | Feb 21 01:00:37 PM PST 24 |
| Peak memory | 332512 kb |
| Host | smart-174e077c-66a6-48b8-9cad-4f4c6387f833 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573053417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3573053417 |
| Directory | /workspace/30.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.4003380286 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 8888282912 ps |
| CPU time | 144.76 seconds |
| Started | Feb 21 12:59:14 PM PST 24 |
| Finished | Feb 21 01:01:39 PM PST 24 |
| Peak memory | 211532 kb |
| Host | smart-c8ba068d-4df6-4fe2-bbde-70952262714f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003380286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.4003380286 |
| Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.2205083536 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 6956013150 ps |
| CPU time | 135.33 seconds |
| Started | Feb 21 12:59:03 PM PST 24 |
| Finished | Feb 21 01:01:19 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-5c63c84a-7094-41d1-a447-70155d4cc6fc |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205083536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.2205083536 |
| Directory | /workspace/30.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1611303780 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2946920333 ps |
| CPU time | 93.4 seconds |
| Started | Feb 21 12:59:03 PM PST 24 |
| Finished | Feb 21 01:00:37 PM PST 24 |
| Peak memory | 310752 kb |
| Host | smart-60d30db3-58df-49ff-8fa0-2383db5dbbef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611303780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1611303780 |
| Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.2763110914 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1084460276 ps |
| CPU time | 121.83 seconds |
| Started | Feb 21 12:59:02 PM PST 24 |
| Finished | Feb 21 01:01:04 PM PST 24 |
| Peak memory | 369996 kb |
| Host | smart-53beccff-5ebd-4295-a4f1-45d5f028e201 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763110914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.2763110914 |
| Directory | /workspace/30.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3323668764 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 114938976815 ps |
| CPU time | 434.8 seconds |
| Started | Feb 21 12:59:07 PM PST 24 |
| Finished | Feb 21 01:06:23 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-dbf47d54-878e-4b4e-9c95-313eb30d2af0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323668764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3323668764 |
| Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.32418938 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 345599513 ps |
| CPU time | 6.61 seconds |
| Started | Feb 21 12:59:05 PM PST 24 |
| Finished | Feb 21 12:59:12 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-6bb9fd70-3436-4749-bb3d-4cd71664717e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.32418938 |
| Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_regwen.3817298465 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 34773460994 ps |
| CPU time | 1109.68 seconds |
| Started | Feb 21 12:59:18 PM PST 24 |
| Finished | Feb 21 01:17:48 PM PST 24 |
| Peak memory | 380284 kb |
| Host | smart-8088e986-e6f2-4586-8d30-974aaa6cc38a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817298465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3817298465 |
| Directory | /workspace/30.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_smoke.490082430 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 956970173 ps |
| CPU time | 28.3 seconds |
| Started | Feb 21 12:59:00 PM PST 24 |
| Finished | Feb 21 12:59:29 PM PST 24 |
| Peak memory | 263744 kb |
| Host | smart-5404f31b-eb12-4054-b8c5-e7a31d64edb6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490082430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.490082430 |
| Directory | /workspace/30.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.773088639 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 478308265106 ps |
| CPU time | 5752.17 seconds |
| Started | Feb 21 12:59:12 PM PST 24 |
| Finished | Feb 21 02:35:05 PM PST 24 |
| Peak memory | 380320 kb |
| Host | smart-533a28fe-e64c-4f08-93eb-f58f5f58b18c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773088639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_stress_all.773088639 |
| Directory | /workspace/30.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1862590201 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 8706260780 ps |
| CPU time | 333.95 seconds |
| Started | Feb 21 12:59:11 PM PST 24 |
| Finished | Feb 21 01:04:45 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-d353c2a4-6000-4ae3-ad9d-23e9c6c4d41a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862590201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1862590201 |
| Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1122716021 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 853150756 ps |
| CPU time | 108.3 seconds |
| Started | Feb 21 12:59:08 PM PST 24 |
| Finished | Feb 21 01:00:56 PM PST 24 |
| Peak memory | 349584 kb |
| Host | smart-684c86d6-a91f-4885-8810-e7f7d501d851 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122716021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1122716021 |
| Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2674932604 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 19368390469 ps |
| CPU time | 809.24 seconds |
| Started | Feb 21 12:59:17 PM PST 24 |
| Finished | Feb 21 01:12:47 PM PST 24 |
| Peak memory | 374392 kb |
| Host | smart-99227bcf-2448-4ec5-a704-0f17659e31fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674932604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2674932604 |
| Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.2096196033 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 41979469 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:59:22 PM PST 24 |
| Finished | Feb 21 12:59:22 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-334887d5-d275-4cfc-a0e8-d08854564ca2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096196033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2096196033 |
| Directory | /workspace/31.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.4010353263 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 761621818 ps |
| CPU time | 95.06 seconds |
| Started | Feb 21 12:59:14 PM PST 24 |
| Finished | Feb 21 01:00:49 PM PST 24 |
| Peak memory | 357652 kb |
| Host | smart-a3d8627b-6b4f-41d7-8e9a-11e1dbaa5c4c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010353263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.4010353263 |
| Directory | /workspace/31.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1598637397 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1600057038 ps |
| CPU time | 127.75 seconds |
| Started | Feb 21 12:59:14 PM PST 24 |
| Finished | Feb 21 01:01:23 PM PST 24 |
| Peak memory | 218400 kb |
| Host | smart-eb9f9f4b-8115-47f2-950d-e4398e33c97a |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598637397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.1598637397 |
| Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.2273583365 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 4109544133 ps |
| CPU time | 263.4 seconds |
| Started | Feb 21 12:59:14 PM PST 24 |
| Finished | Feb 21 01:03:38 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-9b07b9c7-f4ad-49a5-b6a0-f91a9a2dce8a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273583365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.2273583365 |
| Directory | /workspace/31.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.517774502 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 79665414775 ps |
| CPU time | 1454.26 seconds |
| Started | Feb 21 12:59:23 PM PST 24 |
| Finished | Feb 21 01:23:38 PM PST 24 |
| Peak memory | 378228 kb |
| Host | smart-380bc08f-45b5-419c-b8dc-63d5dd8c3e55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517774502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip le_keys.517774502 |
| Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.2068808966 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1305443623 ps |
| CPU time | 23.54 seconds |
| Started | Feb 21 12:59:14 PM PST 24 |
| Finished | Feb 21 12:59:38 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-d5708ea5-f68c-4621-9e40-48e4e484f630 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068808966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.2068808966 |
| Directory | /workspace/31.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2204469030 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 26928268802 ps |
| CPU time | 392.84 seconds |
| Started | Feb 21 12:59:19 PM PST 24 |
| Finished | Feb 21 01:05:52 PM PST 24 |
| Peak memory | 216112 kb |
| Host | smart-0ef161e1-2c9b-496a-8fcf-de9b47da775c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204469030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2204469030 |
| Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.1018557729 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1529217890 ps |
| CPU time | 6.96 seconds |
| Started | Feb 21 12:59:13 PM PST 24 |
| Finished | Feb 21 12:59:20 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-f593d9a3-16fb-4eb2-b1fc-fa9d163c3abc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018557729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1018557729 |
| Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2177194754 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 54599326530 ps |
| CPU time | 1532.3 seconds |
| Started | Feb 21 12:59:27 PM PST 24 |
| Finished | Feb 21 01:25:00 PM PST 24 |
| Peak memory | 375248 kb |
| Host | smart-d236dd64-ec88-4922-a038-a4f2923f1bf7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177194754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2177194754 |
| Directory | /workspace/31.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1209299218 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1420388062 ps |
| CPU time | 24.67 seconds |
| Started | Feb 21 12:59:23 PM PST 24 |
| Finished | Feb 21 12:59:48 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-05d7b5f7-7b9b-4507-9fc8-68d08cd03a25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209299218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1209299218 |
| Directory | /workspace/31.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.2982192803 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 254970884202 ps |
| CPU time | 3321.77 seconds |
| Started | Feb 21 12:59:13 PM PST 24 |
| Finished | Feb 21 01:54:35 PM PST 24 |
| Peak memory | 378200 kb |
| Host | smart-afab14ee-9d0e-4e5a-b490-e98d58ac7628 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982192803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.2982192803 |
| Directory | /workspace/31.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3029813597 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 19997378850 ps |
| CPU time | 409.75 seconds |
| Started | Feb 21 12:59:15 PM PST 24 |
| Finished | Feb 21 01:06:05 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-4037c86c-5bcb-4c09-9e5c-72f87b0545b1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029813597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.3029813597 |
| Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1881609180 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 924110704 ps |
| CPU time | 60.92 seconds |
| Started | Feb 21 12:59:15 PM PST 24 |
| Finished | Feb 21 01:00:16 PM PST 24 |
| Peak memory | 290604 kb |
| Host | smart-c6bbdb8f-e28e-4636-8b91-e8ddb0694600 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881609180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1881609180 |
| Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3765064845 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 61314986680 ps |
| CPU time | 1153.33 seconds |
| Started | Feb 21 12:59:24 PM PST 24 |
| Finished | Feb 21 01:18:37 PM PST 24 |
| Peak memory | 379316 kb |
| Host | smart-6e39591d-194d-4ac1-bc68-4c82d49ba3bf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765064845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.3765064845 |
| Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.205858983 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 28971865 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:59:25 PM PST 24 |
| Finished | Feb 21 12:59:27 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-74b8c993-4c34-430f-a168-4bf2e99e065c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205858983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.205858983 |
| Directory | /workspace/32.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_bijection.2883910372 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 439108218739 ps |
| CPU time | 2211.05 seconds |
| Started | Feb 21 12:59:24 PM PST 24 |
| Finished | Feb 21 01:36:15 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-cdd0fa90-e53c-4165-8f30-dc9c18b4a287 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883910372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .2883910372 |
| Directory | /workspace/32.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_executable.3402310558 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 7703840117 ps |
| CPU time | 358.43 seconds |
| Started | Feb 21 12:59:22 PM PST 24 |
| Finished | Feb 21 01:05:21 PM PST 24 |
| Peak memory | 366956 kb |
| Host | smart-8e4f5b0a-0c62-4f05-a2eb-44dae1adfa78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402310558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3402310558 |
| Directory | /workspace/32.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.3705913245 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 3134501688 ps |
| CPU time | 127.42 seconds |
| Started | Feb 21 12:59:23 PM PST 24 |
| Finished | Feb 21 01:01:31 PM PST 24 |
| Peak memory | 348316 kb |
| Host | smart-3560ff64-855c-46b3-842a-bbb8a729d5e3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705913245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.3705913245 |
| Directory | /workspace/32.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.4086293137 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 6243762274 ps |
| CPU time | 139.67 seconds |
| Started | Feb 21 12:59:22 PM PST 24 |
| Finished | Feb 21 01:01:42 PM PST 24 |
| Peak memory | 214872 kb |
| Host | smart-7022e63f-9b06-42fc-8bf3-1c37a6ab14be |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086293137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.4086293137 |
| Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3228584201 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 3943952130 ps |
| CPU time | 260.14 seconds |
| Started | Feb 21 12:59:29 PM PST 24 |
| Finished | Feb 21 01:03:50 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-831acb09-cf03-4a1c-8330-f19a7889be86 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228584201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3228584201 |
| Directory | /workspace/32.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.899267673 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 117676546720 ps |
| CPU time | 1268.63 seconds |
| Started | Feb 21 12:59:23 PM PST 24 |
| Finished | Feb 21 01:20:32 PM PST 24 |
| Peak memory | 379116 kb |
| Host | smart-c73461d5-f6ed-4db1-95a4-772d0f838266 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899267673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip le_keys.899267673 |
| Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1352181240 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2887591009 ps |
| CPU time | 147.86 seconds |
| Started | Feb 21 12:59:25 PM PST 24 |
| Finished | Feb 21 01:01:54 PM PST 24 |
| Peak memory | 364820 kb |
| Host | smart-f994e546-7ac3-4ee8-9537-887c4f2ce273 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352181240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1352181240 |
| Directory | /workspace/32.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3062540084 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 17337945047 ps |
| CPU time | 187.85 seconds |
| Started | Feb 21 12:59:29 PM PST 24 |
| Finished | Feb 21 01:02:38 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-75787f7a-51f7-4268-82ad-2385baa7d2ab |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062540084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.3062540084 |
| Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.4049249408 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1399314136 ps |
| CPU time | 5.55 seconds |
| Started | Feb 21 12:59:23 PM PST 24 |
| Finished | Feb 21 12:59:29 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-7af4884a-84df-4c87-97f6-4d00551f573e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049249408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.4049249408 |
| Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_regwen.1497806072 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 65864044894 ps |
| CPU time | 1085.94 seconds |
| Started | Feb 21 12:59:24 PM PST 24 |
| Finished | Feb 21 01:17:30 PM PST 24 |
| Peak memory | 379356 kb |
| Host | smart-0e97bc85-27fd-42d2-a252-de6127c71e3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497806072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1497806072 |
| Directory | /workspace/32.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_smoke.4205674755 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1434611522 ps |
| CPU time | 10.02 seconds |
| Started | Feb 21 12:59:14 PM PST 24 |
| Finished | Feb 21 12:59:24 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-d4c7e4cc-7d3c-4cac-9cbd-db0181be41c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205674755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.4205674755 |
| Directory | /workspace/32.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.3537016469 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 52024732174 ps |
| CPU time | 4272.59 seconds |
| Started | Feb 21 12:59:24 PM PST 24 |
| Finished | Feb 21 02:10:38 PM PST 24 |
| Peak memory | 379220 kb |
| Host | smart-d7034fdd-3952-4d24-a31d-0848edbf7568 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537016469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.3537016469 |
| Directory | /workspace/32.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1459951104 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 16245173201 ps |
| CPU time | 322.64 seconds |
| Started | Feb 21 12:59:22 PM PST 24 |
| Finished | Feb 21 01:04:45 PM PST 24 |
| Peak memory | 202376 kb |
| Host | smart-40413942-3a80-4e4e-8e83-d98d76d8a826 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459951104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.1459951104 |
| Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1898910630 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2766468186 ps |
| CPU time | 26.73 seconds |
| Started | Feb 21 12:59:22 PM PST 24 |
| Finished | Feb 21 12:59:49 PM PST 24 |
| Peak memory | 210664 kb |
| Host | smart-c7d9d64c-5c04-40a8-8076-0c74e8fbd890 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898910630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1898910630 |
| Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3249365782 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 10509086598 ps |
| CPU time | 337.2 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:05:17 PM PST 24 |
| Peak memory | 350704 kb |
| Host | smart-d3bf59b8-f44a-4c1d-9e56-70af33362ace |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249365782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.3249365782 |
| Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.3235612673 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 13737132 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 12:59:40 PM PST 24 |
| Peak memory | 201912 kb |
| Host | smart-1402fea6-5ef2-41ca-b966-de440c28bca6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235612673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3235612673 |
| Directory | /workspace/33.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_bijection.3046607391 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 125548226952 ps |
| CPU time | 2368.9 seconds |
| Started | Feb 21 12:59:29 PM PST 24 |
| Finished | Feb 21 01:38:59 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-a3a4a931-76d8-4251-824f-5f941b7d4a65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046607391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .3046607391 |
| Directory | /workspace/33.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_executable.2507066388 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 82484711964 ps |
| CPU time | 908.22 seconds |
| Started | Feb 21 12:59:40 PM PST 24 |
| Finished | Feb 21 01:14:49 PM PST 24 |
| Peak memory | 369308 kb |
| Host | smart-010234fc-3262-444a-8e56-cb40984674f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507066388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.2507066388 |
| Directory | /workspace/33.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.2676951267 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 13506113129 ps |
| CPU time | 341.72 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:05:21 PM PST 24 |
| Peak memory | 210672 kb |
| Host | smart-090467a2-12ed-4fcc-a664-d106fc48e740 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676951267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.2676951267 |
| Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.2338037874 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1447468869 ps |
| CPU time | 27.48 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:00:06 PM PST 24 |
| Peak memory | 212488 kb |
| Host | smart-fae5f8c8-0139-41f1-a37e-934ee1b53121 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338037874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2338037874 |
| Directory | /workspace/33.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1784004911 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5340118979 ps |
| CPU time | 132.35 seconds |
| Started | Feb 21 12:59:42 PM PST 24 |
| Finished | Feb 21 01:01:55 PM PST 24 |
| Peak memory | 211468 kb |
| Host | smart-587fcc30-fc71-4099-bc31-025cbc773aa7 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784004911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.1784004911 |
| Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.2674901377 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 28125492366 ps |
| CPU time | 266.58 seconds |
| Started | Feb 21 12:59:42 PM PST 24 |
| Finished | Feb 21 01:04:09 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-b9c25875-3c1c-424e-ae08-703f4c6bd7ad |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674901377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.2674901377 |
| Directory | /workspace/33.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.957838373 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 67881023834 ps |
| CPU time | 1419.15 seconds |
| Started | Feb 21 12:59:23 PM PST 24 |
| Finished | Feb 21 01:23:02 PM PST 24 |
| Peak memory | 377320 kb |
| Host | smart-a77d0f99-35f7-4b36-b477-c4ca080ec9f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957838373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.957838373 |
| Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.1285122362 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1011830925 ps |
| CPU time | 163.61 seconds |
| Started | Feb 21 12:59:41 PM PST 24 |
| Finished | Feb 21 01:02:25 PM PST 24 |
| Peak memory | 362824 kb |
| Host | smart-a08b3aef-1a86-403f-b0f0-c0c6455dd24a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285122362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.1285122362 |
| Directory | /workspace/33.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.3289308798 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 357519327 ps |
| CPU time | 6.39 seconds |
| Started | Feb 21 12:59:41 PM PST 24 |
| Finished | Feb 21 12:59:48 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-84697713-69ca-49ec-9016-c68c86182581 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289308798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3289308798 |
| Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_regwen.3132566237 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 5892234433 ps |
| CPU time | 1145.53 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:18:45 PM PST 24 |
| Peak memory | 379328 kb |
| Host | smart-a715ee76-4710-4554-9297-2f8c8d295560 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132566237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3132566237 |
| Directory | /workspace/33.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_smoke.1331756273 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1112138361 ps |
| CPU time | 47.86 seconds |
| Started | Feb 21 12:59:22 PM PST 24 |
| Finished | Feb 21 01:00:10 PM PST 24 |
| Peak memory | 293052 kb |
| Host | smart-4e22942b-d9bc-473d-b9c2-a7857643a835 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331756273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1331756273 |
| Directory | /workspace/33.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.2475627798 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 436221317218 ps |
| CPU time | 6663.92 seconds |
| Started | Feb 21 12:59:41 PM PST 24 |
| Finished | Feb 21 02:50:46 PM PST 24 |
| Peak memory | 381332 kb |
| Host | smart-616d7946-a00e-4d7a-a21c-5d6943119bb0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475627798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.2475627798 |
| Directory | /workspace/33.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1033645522 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5717342606 ps |
| CPU time | 496.02 seconds |
| Started | Feb 21 12:59:25 PM PST 24 |
| Finished | Feb 21 01:07:42 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-053aaa59-85cc-447d-b2b7-a0def0f3a17c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033645522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.1033645522 |
| Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3675550547 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 673861833 ps |
| CPU time | 26.47 seconds |
| Started | Feb 21 12:59:43 PM PST 24 |
| Finished | Feb 21 01:00:10 PM PST 24 |
| Peak memory | 210636 kb |
| Host | smart-55db1f37-097a-4282-adf0-8f77ef9e9ab1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675550547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3675550547 |
| Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3337231942 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 14105186074 ps |
| CPU time | 1081.66 seconds |
| Started | Feb 21 01:00:01 PM PST 24 |
| Finished | Feb 21 01:18:04 PM PST 24 |
| Peak memory | 380532 kb |
| Host | smart-078c462d-6233-40bb-a985-1f22e6eea173 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337231942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3337231942 |
| Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.2297171598 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 42519076 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 01:00:04 PM PST 24 |
| Finished | Feb 21 01:00:05 PM PST 24 |
| Peak memory | 202136 kb |
| Host | smart-da372fbd-cc0c-40af-b701-ef66b69315ac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297171598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2297171598 |
| Directory | /workspace/34.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_bijection.2400213159 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 17396683656 ps |
| CPU time | 1193 seconds |
| Started | Feb 21 12:59:41 PM PST 24 |
| Finished | Feb 21 01:19:35 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-113c14b6-5cd0-4a58-9fbb-a959842e67fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400213159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .2400213159 |
| Directory | /workspace/34.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_executable.2823523187 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 4917154419 ps |
| CPU time | 129.14 seconds |
| Started | Feb 21 12:59:57 PM PST 24 |
| Finished | Feb 21 01:02:07 PM PST 24 |
| Peak memory | 296080 kb |
| Host | smart-f230be7d-9a26-4a71-8d08-99bce24cd1e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823523187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.2823523187 |
| Directory | /workspace/34.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.996114776 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 18314257901 ps |
| CPU time | 73.26 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:00:53 PM PST 24 |
| Peak memory | 210604 kb |
| Host | smart-1fe8f46c-94e7-4032-b033-21ff9623f723 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996114776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc alation.996114776 |
| Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.2115748183 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 722426480 ps |
| CPU time | 27.25 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:00:07 PM PST 24 |
| Peak memory | 210640 kb |
| Host | smart-dc2816ba-c370-46f6-ad49-83af64283252 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115748183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2115748183 |
| Directory | /workspace/34.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1213766435 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2484278405 ps |
| CPU time | 72.31 seconds |
| Started | Feb 21 12:59:59 PM PST 24 |
| Finished | Feb 21 01:01:12 PM PST 24 |
| Peak memory | 211728 kb |
| Host | smart-5e7b45f0-4931-46fc-b968-db87adeb3b41 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213766435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.1213766435 |
| Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.2124683113 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 28749301000 ps |
| CPU time | 147.5 seconds |
| Started | Feb 21 01:00:04 PM PST 24 |
| Finished | Feb 21 01:02:32 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-386b6a24-eebd-4fd9-b4d6-c27e89d34505 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124683113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2124683113 |
| Directory | /workspace/34.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1254141670 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 32855572587 ps |
| CPU time | 1395.29 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:22:55 PM PST 24 |
| Peak memory | 378212 kb |
| Host | smart-e2d71439-ee2d-4b2e-829e-d4f771217291 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254141670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1254141670 |
| Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.3429388861 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 391848848 ps |
| CPU time | 16.51 seconds |
| Started | Feb 21 12:59:42 PM PST 24 |
| Finished | Feb 21 12:59:59 PM PST 24 |
| Peak memory | 216320 kb |
| Host | smart-015a0952-41cb-46a9-ab7a-fbd6bc8071d6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429388861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.3429388861 |
| Directory | /workspace/34.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1851498437 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 24482689856 ps |
| CPU time | 491.2 seconds |
| Started | Feb 21 12:59:41 PM PST 24 |
| Finished | Feb 21 01:07:53 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-b37d60c7-7fe0-48ea-9dd1-a18178c8b4f5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851498437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.1851498437 |
| Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.870031686 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 787579634 ps |
| CPU time | 5.58 seconds |
| Started | Feb 21 12:59:58 PM PST 24 |
| Finished | Feb 21 01:00:05 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-b0626836-7dad-42b6-9d26-a0d9fe0f102d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870031686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.870031686 |
| Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_regwen.2231350378 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 5905452120 ps |
| CPU time | 61.21 seconds |
| Started | Feb 21 12:59:53 PM PST 24 |
| Finished | Feb 21 01:00:54 PM PST 24 |
| Peak memory | 216596 kb |
| Host | smart-c840f102-fb1b-43c7-a63a-5e37d00be012 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231350378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2231350378 |
| Directory | /workspace/34.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1262272513 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 723712725 ps |
| CPU time | 29.03 seconds |
| Started | Feb 21 12:59:42 PM PST 24 |
| Finished | Feb 21 01:00:11 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-faa15484-34b5-4afe-8d94-3864f770b102 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262272513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1262272513 |
| Directory | /workspace/34.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.4013550598 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 79532426164 ps |
| CPU time | 3242.89 seconds |
| Started | Feb 21 12:59:57 PM PST 24 |
| Finished | Feb 21 01:54:00 PM PST 24 |
| Peak memory | 387612 kb |
| Host | smart-2c3ca98f-03f4-41a3-afb9-f752afb59c72 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013550598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.4013550598 |
| Directory | /workspace/34.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1574606500 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5291932750 ps |
| CPU time | 338.16 seconds |
| Started | Feb 21 12:59:39 PM PST 24 |
| Finished | Feb 21 01:05:17 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-1406425d-b874-4913-a586-f941514ed532 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574606500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.1574606500 |
| Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3531993731 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1464661479 ps |
| CPU time | 54.87 seconds |
| Started | Feb 21 12:59:41 PM PST 24 |
| Finished | Feb 21 01:00:36 PM PST 24 |
| Peak memory | 289740 kb |
| Host | smart-6c65576b-c169-4590-ab0b-60b61c17d709 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531993731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3531993731 |
| Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.324544804 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 8596426224 ps |
| CPU time | 1482.29 seconds |
| Started | Feb 21 12:59:58 PM PST 24 |
| Finished | Feb 21 01:24:41 PM PST 24 |
| Peak memory | 378296 kb |
| Host | smart-d92106db-40e4-461c-a6a8-c82ad46ef46c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324544804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sram_ctrl_access_during_key_req.324544804 |
| Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.1059726193 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 168518178 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:59:58 PM PST 24 |
| Finished | Feb 21 01:00:00 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-194bbba3-fbbd-486c-b5b7-715791857859 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059726193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1059726193 |
| Directory | /workspace/35.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_bijection.754543757 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 188063682081 ps |
| CPU time | 2003.07 seconds |
| Started | Feb 21 01:00:01 PM PST 24 |
| Finished | Feb 21 01:33:25 PM PST 24 |
| Peak memory | 210616 kb |
| Host | smart-4637cf0d-6edb-4be6-95c5-305f5ca60d1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754543757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection. 754543757 |
| Directory | /workspace/35.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.3601072311 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 8325604561 ps |
| CPU time | 98.34 seconds |
| Started | Feb 21 12:59:55 PM PST 24 |
| Finished | Feb 21 01:01:34 PM PST 24 |
| Peak memory | 210596 kb |
| Host | smart-80a7ddec-e441-4d3c-ac85-fa8585596544 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601072311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.3601072311 |
| Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.3436501118 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3012355325 ps |
| CPU time | 55.14 seconds |
| Started | Feb 21 12:59:57 PM PST 24 |
| Finished | Feb 21 01:00:53 PM PST 24 |
| Peak memory | 293628 kb |
| Host | smart-43630e02-2e46-45ba-8152-f1fe079e0ba8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436501118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.3436501118 |
| Directory | /workspace/35.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2848197981 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1566381011 ps |
| CPU time | 134.37 seconds |
| Started | Feb 21 12:59:54 PM PST 24 |
| Finished | Feb 21 01:02:09 PM PST 24 |
| Peak memory | 211940 kb |
| Host | smart-1b187f86-abae-4835-b8d6-a6685682537a |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848197981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.2848197981 |
| Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.4080273994 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 7055309007 ps |
| CPU time | 122.47 seconds |
| Started | Feb 21 12:59:59 PM PST 24 |
| Finished | Feb 21 01:02:03 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-ebc7b6dc-727e-4e7b-980f-941bcdca11e8 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080273994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.4080273994 |
| Directory | /workspace/35.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.922485706 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 13342464377 ps |
| CPU time | 1719.88 seconds |
| Started | Feb 21 12:59:58 PM PST 24 |
| Finished | Feb 21 01:28:39 PM PST 24 |
| Peak memory | 377248 kb |
| Host | smart-4ab7a472-1a8e-492a-8603-4ea2fa357993 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922485706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.922485706 |
| Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.2728515296 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2868524739 ps |
| CPU time | 23.73 seconds |
| Started | Feb 21 12:59:52 PM PST 24 |
| Finished | Feb 21 01:00:16 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-6a468c96-291e-4059-b9a4-1c8437d931f7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728515296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.2728515296 |
| Directory | /workspace/35.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3892590426 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 30365376638 ps |
| CPU time | 318.93 seconds |
| Started | Feb 21 01:00:01 PM PST 24 |
| Finished | Feb 21 01:05:21 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-57f3b21b-b1c5-4647-988c-6910e4745b44 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892590426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.3892590426 |
| Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.3270570085 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 399047764 ps |
| CPU time | 5.5 seconds |
| Started | Feb 21 12:59:55 PM PST 24 |
| Finished | Feb 21 01:00:01 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-5ce2561a-51f2-441b-b1b2-f409f2613442 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270570085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3270570085 |
| Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_regwen.428070301 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 6819086034 ps |
| CPU time | 1076.81 seconds |
| Started | Feb 21 01:00:03 PM PST 24 |
| Finished | Feb 21 01:18:00 PM PST 24 |
| Peak memory | 377260 kb |
| Host | smart-f38ada89-5a1f-448a-8226-07fe76935b29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428070301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.428070301 |
| Directory | /workspace/35.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_smoke.766800765 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 767817777 ps |
| CPU time | 48.53 seconds |
| Started | Feb 21 12:59:57 PM PST 24 |
| Finished | Feb 21 01:00:47 PM PST 24 |
| Peak memory | 311528 kb |
| Host | smart-f02085fb-8bb6-4daf-ab78-f673003ab4cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766800765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.766800765 |
| Directory | /workspace/35.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1286719011 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 7516244252 ps |
| CPU time | 249.64 seconds |
| Started | Feb 21 12:59:53 PM PST 24 |
| Finished | Feb 21 01:04:02 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-0bc1ed9b-f8f6-4b3f-b60a-e3567545f054 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286719011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1286719011 |
| Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.803607371 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1444427664 ps |
| CPU time | 39.65 seconds |
| Started | Feb 21 12:59:59 PM PST 24 |
| Finished | Feb 21 01:00:40 PM PST 24 |
| Peak memory | 255548 kb |
| Host | smart-17932aa0-1680-4cec-97ac-efa2785f8d35 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803607371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_throughput_w_partial_write.803607371 |
| Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2417758072 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 30366485765 ps |
| CPU time | 1173.71 seconds |
| Started | Feb 21 12:59:57 PM PST 24 |
| Finished | Feb 21 01:19:32 PM PST 24 |
| Peak memory | 378324 kb |
| Host | smart-b353750f-bfa4-4bf3-847d-566059d20306 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417758072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2417758072 |
| Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.1786693006 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 21096874 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 01:00:15 PM PST 24 |
| Finished | Feb 21 01:00:16 PM PST 24 |
| Peak memory | 201920 kb |
| Host | smart-64ab1ff6-8d54-46fb-8caa-01bbc8f799f5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786693006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1786693006 |
| Directory | /workspace/36.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_bijection.1325275003 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 8290483320 ps |
| CPU time | 551.42 seconds |
| Started | Feb 21 12:59:55 PM PST 24 |
| Finished | Feb 21 01:09:07 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-0d4d1acb-ca6b-45e5-a747-ed37595a6def |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325275003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .1325275003 |
| Directory | /workspace/36.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_executable.2234958269 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2513023258 ps |
| CPU time | 80.58 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:01:29 PM PST 24 |
| Peak memory | 311380 kb |
| Host | smart-0801bfb5-ac86-4a0d-814b-a6ae0eb23fcd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234958269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.2234958269 |
| Directory | /workspace/36.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.4271326650 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2682221162 ps |
| CPU time | 85.88 seconds |
| Started | Feb 21 12:59:58 PM PST 24 |
| Finished | Feb 21 01:01:24 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-acbca890-cd3e-4640-8d72-3d134f023566 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271326650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.4271326650 |
| Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.923436427 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 761598161 ps |
| CPU time | 60.32 seconds |
| Started | Feb 21 12:59:59 PM PST 24 |
| Finished | Feb 21 01:01:01 PM PST 24 |
| Peak memory | 300524 kb |
| Host | smart-b78bd740-cac4-49a9-87f8-6bcf80f0ccbf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923436427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.sram_ctrl_max_throughput.923436427 |
| Directory | /workspace/36.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.4011879617 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2390886346 ps |
| CPU time | 73.26 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:01:21 PM PST 24 |
| Peak memory | 211440 kb |
| Host | smart-7be591b8-ea04-4f86-8f70-d1ac187d2be4 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011879617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.4011879617 |
| Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.2097851682 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 9142766051 ps |
| CPU time | 156.32 seconds |
| Started | Feb 21 01:00:06 PM PST 24 |
| Finished | Feb 21 01:02:43 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-ded3c83d-acd7-43c1-a55b-427eb17758e2 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097851682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.2097851682 |
| Directory | /workspace/36.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.3542304673 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 15660366587 ps |
| CPU time | 491.05 seconds |
| Started | Feb 21 12:59:58 PM PST 24 |
| Finished | Feb 21 01:08:09 PM PST 24 |
| Peak memory | 365000 kb |
| Host | smart-c3f09290-0c13-423b-afa6-b20e066d60f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542304673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.3542304673 |
| Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.2844849422 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1812307992 ps |
| CPU time | 22.86 seconds |
| Started | Feb 21 01:00:00 PM PST 24 |
| Finished | Feb 21 01:00:23 PM PST 24 |
| Peak memory | 245240 kb |
| Host | smart-fcd4c321-03dc-49cb-8cf9-3042c65ad0f3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844849422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.2844849422 |
| Directory | /workspace/36.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.11734080 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 14451654035 ps |
| CPU time | 317.51 seconds |
| Started | Feb 21 01:00:00 PM PST 24 |
| Finished | Feb 21 01:05:18 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-37d6bb16-2d82-482b-b338-2ba32ec64eab |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11734080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_partial_access_b2b.11734080 |
| Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.3572859265 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 353713550 ps |
| CPU time | 5.48 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:00:14 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-afa6f900-0238-4348-b3ff-459acb7a09fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572859265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3572859265 |
| Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_regwen.936422025 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3888336230 ps |
| CPU time | 856.67 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:14:25 PM PST 24 |
| Peak memory | 378284 kb |
| Host | smart-9e3d30ad-b916-4374-a721-904db1bfc4e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936422025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.936422025 |
| Directory | /workspace/36.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_smoke.3749058579 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 414666007 ps |
| CPU time | 8.15 seconds |
| Started | Feb 21 12:59:57 PM PST 24 |
| Finished | Feb 21 01:00:05 PM PST 24 |
| Peak memory | 208108 kb |
| Host | smart-0167b6e7-e95d-4070-a3b3-5a4a93838251 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749058579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3749058579 |
| Directory | /workspace/36.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.4017575051 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 32285031223 ps |
| CPU time | 264.37 seconds |
| Started | Feb 21 12:59:59 PM PST 24 |
| Finished | Feb 21 01:04:24 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-80c0b53d-6911-4691-ac49-d5d5c5d5f22f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017575051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.4017575051 |
| Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.459984047 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2836167201 ps |
| CPU time | 30.99 seconds |
| Started | Feb 21 12:59:55 PM PST 24 |
| Finished | Feb 21 01:00:26 PM PST 24 |
| Peak memory | 223668 kb |
| Host | smart-720d1183-8920-4a7f-a94b-96b303e3feab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459984047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.459984047 |
| Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.846876749 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 18206360253 ps |
| CPU time | 378.03 seconds |
| Started | Feb 21 01:00:08 PM PST 24 |
| Finished | Feb 21 01:06:27 PM PST 24 |
| Peak memory | 338856 kb |
| Host | smart-c1e39a15-3619-4a90-baa3-685d573e7e5b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846876749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 37.sram_ctrl_access_during_key_req.846876749 |
| Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.1080590963 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 16701722 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:00:15 PM PST 24 |
| Finished | Feb 21 01:00:16 PM PST 24 |
| Peak memory | 201964 kb |
| Host | smart-a6b72786-39cc-496d-8fbc-6f18823e327e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080590963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1080590963 |
| Directory | /workspace/37.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_bijection.3365389304 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 23570119881 ps |
| CPU time | 1556.56 seconds |
| Started | Feb 21 01:00:08 PM PST 24 |
| Finished | Feb 21 01:26:05 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-1a9b69c9-be35-434a-b4a3-8a2e6360e38a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365389304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .3365389304 |
| Directory | /workspace/37.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.3392487596 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 734091156 ps |
| CPU time | 36.28 seconds |
| Started | Feb 21 01:00:06 PM PST 24 |
| Finished | Feb 21 01:00:43 PM PST 24 |
| Peak memory | 251472 kb |
| Host | smart-6cd9f86a-938b-400b-9a21-f233bf3bbe54 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392487596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3392487596 |
| Directory | /workspace/37.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3529670287 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1966064224 ps |
| CPU time | 131.87 seconds |
| Started | Feb 21 01:00:11 PM PST 24 |
| Finished | Feb 21 01:02:23 PM PST 24 |
| Peak memory | 211556 kb |
| Host | smart-be5778c7-d61f-420f-81f2-73d4dc4c57ce |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529670287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.3529670287 |
| Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.914685917 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3943273415 ps |
| CPU time | 249.74 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:04:17 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-45ff2f79-1c39-402b-ae9c-bd5361add33b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914685917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _mem_walk.914685917 |
| Directory | /workspace/37.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.3405368502 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 121820870355 ps |
| CPU time | 701.38 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:11:49 PM PST 24 |
| Peak memory | 365184 kb |
| Host | smart-fe0d0991-634e-48f8-b770-1ce92a27f31e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405368502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.3405368502 |
| Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.2045972891 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1679999173 ps |
| CPU time | 16.08 seconds |
| Started | Feb 21 01:00:05 PM PST 24 |
| Finished | Feb 21 01:00:22 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-37a15d74-2c6b-4ea8-b0e5-8add8eb694e7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045972891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.2045972891 |
| Directory | /workspace/37.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3251938346 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 44429919417 ps |
| CPU time | 332.85 seconds |
| Started | Feb 21 01:00:15 PM PST 24 |
| Finished | Feb 21 01:05:48 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-23451623-2de7-4456-b81c-16003c657fdb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251938346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3251938346 |
| Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.2159167343 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 352529037 ps |
| CPU time | 13.89 seconds |
| Started | Feb 21 01:00:30 PM PST 24 |
| Finished | Feb 21 01:00:44 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-9ed8b9b9-c02f-4275-9878-fcc9f3d27c0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159167343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2159167343 |
| Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_regwen.859196028 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 55457153212 ps |
| CPU time | 1624.98 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:27:13 PM PST 24 |
| Peak memory | 379340 kb |
| Host | smart-86ddc25a-fa10-4b9b-ba62-b0d9a975add2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859196028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.859196028 |
| Directory | /workspace/37.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_smoke.391234829 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1040853736 ps |
| CPU time | 16.07 seconds |
| Started | Feb 21 01:00:05 PM PST 24 |
| Finished | Feb 21 01:00:22 PM PST 24 |
| Peak memory | 236568 kb |
| Host | smart-18e19ed4-d94d-43b9-8e3b-f08569b44b1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391234829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.391234829 |
| Directory | /workspace/37.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.855151603 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 48551388282 ps |
| CPU time | 5138.68 seconds |
| Started | Feb 21 01:00:15 PM PST 24 |
| Finished | Feb 21 02:25:55 PM PST 24 |
| Peak memory | 380348 kb |
| Host | smart-67cda9c8-ca8e-44ab-86c1-a83476b173ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855151603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_stress_all.855151603 |
| Directory | /workspace/37.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.142454929 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 21423060163 ps |
| CPU time | 373.61 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:06:21 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-d75b2ec0-401d-4495-9a8c-0731d8e74ed8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142454929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_stress_pipeline.142454929 |
| Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3292138422 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 784972308 ps |
| CPU time | 120.46 seconds |
| Started | Feb 21 01:00:07 PM PST 24 |
| Finished | Feb 21 01:02:09 PM PST 24 |
| Peak memory | 346560 kb |
| Host | smart-b962e92a-8fbd-4d9d-a71c-53068d0b3366 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292138422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3292138422 |
| Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2763030179 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 16510437579 ps |
| CPU time | 1418.38 seconds |
| Started | Feb 21 01:00:20 PM PST 24 |
| Finished | Feb 21 01:23:59 PM PST 24 |
| Peak memory | 378280 kb |
| Host | smart-19c41bb4-94d5-41f4-b690-56bd31a61753 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763030179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.2763030179 |
| Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.2464041889 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 14778849 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:00:16 PM PST 24 |
| Finished | Feb 21 01:00:17 PM PST 24 |
| Peak memory | 201948 kb |
| Host | smart-223ac329-d450-4337-935d-1020613eec83 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464041889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.2464041889 |
| Directory | /workspace/38.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2916439216 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 120700285205 ps |
| CPU time | 571.25 seconds |
| Started | Feb 21 01:00:12 PM PST 24 |
| Finished | Feb 21 01:09:44 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-69878558-97f5-4a33-9438-7adcf4cc2f53 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916439216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2916439216 |
| Directory | /workspace/38.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.167464374 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 4236246114 ps |
| CPU time | 40.99 seconds |
| Started | Feb 21 01:00:17 PM PST 24 |
| Finished | Feb 21 01:00:59 PM PST 24 |
| Peak memory | 210512 kb |
| Host | smart-6adad68d-ad85-46cd-ab2d-892ea8466afc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167464374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_esc alation.167464374 |
| Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.1389262329 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1577570490 ps |
| CPU time | 29.24 seconds |
| Started | Feb 21 01:00:17 PM PST 24 |
| Finished | Feb 21 01:00:47 PM PST 24 |
| Peak memory | 218740 kb |
| Host | smart-0bd75bc6-09bf-4645-b7d4-ab6446a6a458 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389262329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.1389262329 |
| Directory | /workspace/38.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.4174894840 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2362733733 ps |
| CPU time | 73.88 seconds |
| Started | Feb 21 01:00:14 PM PST 24 |
| Finished | Feb 21 01:01:28 PM PST 24 |
| Peak memory | 211888 kb |
| Host | smart-e14eb473-7ec7-42da-ab98-ff256530eff0 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174894840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.4174894840 |
| Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.1563997215 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 16454585281 ps |
| CPU time | 114.75 seconds |
| Started | Feb 21 01:00:17 PM PST 24 |
| Finished | Feb 21 01:02:12 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-40d87a7f-2be0-47ff-b8a5-3930a305b263 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563997215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1563997215 |
| Directory | /workspace/38.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.637693116 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 46367221110 ps |
| CPU time | 1366.51 seconds |
| Started | Feb 21 01:00:18 PM PST 24 |
| Finished | Feb 21 01:23:05 PM PST 24 |
| Peak memory | 379280 kb |
| Host | smart-3bc97817-14d0-46a1-ad55-495f0bd3ead0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637693116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip le_keys.637693116 |
| Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.2681137740 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 7476038982 ps |
| CPU time | 31.36 seconds |
| Started | Feb 21 01:00:18 PM PST 24 |
| Finished | Feb 21 01:00:50 PM PST 24 |
| Peak memory | 210560 kb |
| Host | smart-30d47f19-8068-4dce-91fc-54f2b4d9cdd2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681137740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.2681137740 |
| Directory | /workspace/38.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2917851299 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 11800169212 ps |
| CPU time | 263.61 seconds |
| Started | Feb 21 01:00:14 PM PST 24 |
| Finished | Feb 21 01:04:38 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-5dba053b-fd77-4289-8226-b34298d9faee |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917851299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.2917851299 |
| Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.2614885453 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 350645891 ps |
| CPU time | 5.27 seconds |
| Started | Feb 21 01:00:14 PM PST 24 |
| Finished | Feb 21 01:00:20 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-13fc3595-2833-4865-9a5c-82e0ea17df93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614885453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2614885453 |
| Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_regwen.3823326327 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3292163675 ps |
| CPU time | 1011.65 seconds |
| Started | Feb 21 01:00:19 PM PST 24 |
| Finished | Feb 21 01:17:12 PM PST 24 |
| Peak memory | 376248 kb |
| Host | smart-d4897761-9988-48fd-ae1a-aab00ce92a54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823326327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3823326327 |
| Directory | /workspace/38.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_smoke.1109781097 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3218934945 ps |
| CPU time | 73.53 seconds |
| Started | Feb 21 01:00:17 PM PST 24 |
| Finished | Feb 21 01:01:32 PM PST 24 |
| Peak memory | 356736 kb |
| Host | smart-7430357f-82c0-4cc3-9a79-b2a63d228ce7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109781097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1109781097 |
| Directory | /workspace/38.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.3505319616 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 17287877201 ps |
| CPU time | 1987.08 seconds |
| Started | Feb 21 01:00:17 PM PST 24 |
| Finished | Feb 21 01:33:25 PM PST 24 |
| Peak memory | 380348 kb |
| Host | smart-b1cf8267-d1ec-4bf7-ac52-1dfd30878a35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505319616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.3505319616 |
| Directory | /workspace/38.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.731865378 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 4769099949 ps |
| CPU time | 381.05 seconds |
| Started | Feb 21 01:00:19 PM PST 24 |
| Finished | Feb 21 01:06:40 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-9b9814bf-e045-4267-9c4f-f0fe46daaa4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731865378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_stress_pipeline.731865378 |
| Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.954201830 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 5753732844 ps |
| CPU time | 92.89 seconds |
| Started | Feb 21 01:00:16 PM PST 24 |
| Finished | Feb 21 01:01:49 PM PST 24 |
| Peak memory | 322072 kb |
| Host | smart-5d22cbfb-ca1f-473d-8cf6-bec81440ee83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954201830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.954201830 |
| Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.888526189 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3501010311 ps |
| CPU time | 398.4 seconds |
| Started | Feb 21 01:00:30 PM PST 24 |
| Finished | Feb 21 01:07:09 PM PST 24 |
| Peak memory | 363964 kb |
| Host | smart-1b86377d-1b7f-4f61-89aa-b0763b97e44d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888526189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.888526189 |
| Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3692358286 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 22176397 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:00:37 PM PST 24 |
| Finished | Feb 21 01:00:38 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-474ec291-77ba-428a-bb91-64c9f9688dcb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692358286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3692358286 |
| Directory | /workspace/39.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_bijection.2617588908 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 48564249391 ps |
| CPU time | 879.83 seconds |
| Started | Feb 21 01:00:37 PM PST 24 |
| Finished | Feb 21 01:15:17 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-a76f5628-2c3b-403e-9dde-64163e43fc1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617588908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .2617588908 |
| Directory | /workspace/39.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.4121471235 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 789279574 ps |
| CPU time | 102.47 seconds |
| Started | Feb 21 01:00:29 PM PST 24 |
| Finished | Feb 21 01:02:12 PM PST 24 |
| Peak memory | 349652 kb |
| Host | smart-df4ad636-217d-414d-965e-9cea75671c22 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121471235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.4121471235 |
| Directory | /workspace/39.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2591175740 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 4690762830 ps |
| CPU time | 76.49 seconds |
| Started | Feb 21 01:00:32 PM PST 24 |
| Finished | Feb 21 01:01:49 PM PST 24 |
| Peak memory | 210880 kb |
| Host | smart-996582d3-beb1-41f5-b14a-5516c23de5c0 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591175740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2591175740 |
| Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.3868173353 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 17216666479 ps |
| CPU time | 149.01 seconds |
| Started | Feb 21 01:00:28 PM PST 24 |
| Finished | Feb 21 01:02:58 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-691d5d0c-fd0a-48e6-9a13-0c4b0a8b4d2f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868173353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3868173353 |
| Directory | /workspace/39.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.2382400365 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 94728867788 ps |
| CPU time | 993.78 seconds |
| Started | Feb 21 01:00:29 PM PST 24 |
| Finished | Feb 21 01:17:03 PM PST 24 |
| Peak memory | 379356 kb |
| Host | smart-356a3baa-721b-4067-b88b-3c5e69e9c2f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382400365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.2382400365 |
| Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.2060773030 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5032392357 ps |
| CPU time | 72.14 seconds |
| Started | Feb 21 01:00:30 PM PST 24 |
| Finished | Feb 21 01:01:42 PM PST 24 |
| Peak memory | 311752 kb |
| Host | smart-6c7a621a-22fc-4b64-9da4-f72ca817aa75 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060773030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.2060773030 |
| Directory | /workspace/39.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2469163205 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 5592836897 ps |
| CPU time | 346.36 seconds |
| Started | Feb 21 01:00:29 PM PST 24 |
| Finished | Feb 21 01:06:16 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-70fcc9d0-13e5-45ea-8029-204982bf789b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469163205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.2469163205 |
| Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.2882046923 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 354446189 ps |
| CPU time | 13.74 seconds |
| Started | Feb 21 01:00:28 PM PST 24 |
| Finished | Feb 21 01:00:42 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-4e15c28e-015b-4b5a-a51d-f20e689fad9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882046923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2882046923 |
| Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_regwen.820598299 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 7030778041 ps |
| CPU time | 487.94 seconds |
| Started | Feb 21 01:00:27 PM PST 24 |
| Finished | Feb 21 01:08:35 PM PST 24 |
| Peak memory | 377148 kb |
| Host | smart-be22aaa5-8e34-4793-9098-932514c09cd3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820598299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.820598299 |
| Directory | /workspace/39.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_smoke.3615484127 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 761902143 ps |
| CPU time | 13.67 seconds |
| Started | Feb 21 01:00:14 PM PST 24 |
| Finished | Feb 21 01:00:28 PM PST 24 |
| Peak memory | 208924 kb |
| Host | smart-6cd21e2d-f5ad-480c-96fa-e90b80c19c17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615484127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3615484127 |
| Directory | /workspace/39.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3739456595 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7858557352 ps |
| CPU time | 326.46 seconds |
| Started | Feb 21 01:00:28 PM PST 24 |
| Finished | Feb 21 01:05:55 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-c2e391eb-3d63-4c0f-acd1-40f435293c5e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739456595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.3739456595 |
| Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3776378321 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 710318697 ps |
| CPU time | 30.91 seconds |
| Started | Feb 21 01:00:37 PM PST 24 |
| Finished | Feb 21 01:01:08 PM PST 24 |
| Peak memory | 227780 kb |
| Host | smart-5e29b380-2e37-4393-8c91-5c972b0d983c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776378321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3776378321 |
| Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1945645216 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13895649553 ps |
| CPU time | 1091.41 seconds |
| Started | Feb 21 12:56:41 PM PST 24 |
| Finished | Feb 21 01:14:53 PM PST 24 |
| Peak memory | 375132 kb |
| Host | smart-05ae86eb-9df6-43bd-8c5a-88e61dc7633d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945645216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.1945645216 |
| Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.3561916622 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 50847733 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:56:43 PM PST 24 |
| Finished | Feb 21 12:56:44 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-f0dd4e9e-f309-41ac-9ca0-f4f0a2da2d02 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561916622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.3561916622 |
| Directory | /workspace/4.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_bijection.1960880017 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 95140845371 ps |
| CPU time | 807.9 seconds |
| Started | Feb 21 12:56:45 PM PST 24 |
| Finished | Feb 21 01:10:13 PM PST 24 |
| Peak memory | 210624 kb |
| Host | smart-4c27eb93-81ef-4280-8db0-a61565827140 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960880017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 1960880017 |
| Directory | /workspace/4.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.2168007185 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3999442045 ps |
| CPU time | 39.16 seconds |
| Started | Feb 21 12:56:44 PM PST 24 |
| Finished | Feb 21 12:57:24 PM PST 24 |
| Peak memory | 210692 kb |
| Host | smart-b2fdc21e-70c3-42ae-a9f6-04e2a43c19d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168007185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.2168007185 |
| Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.1396700441 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4836009670 ps |
| CPU time | 67.83 seconds |
| Started | Feb 21 12:56:41 PM PST 24 |
| Finished | Feb 21 12:57:49 PM PST 24 |
| Peak memory | 305728 kb |
| Host | smart-72a614e3-d581-4605-ad6a-215a33e5eb29 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396700441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.1396700441 |
| Directory | /workspace/4.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1728772829 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2624477198 ps |
| CPU time | 73.99 seconds |
| Started | Feb 21 12:56:43 PM PST 24 |
| Finished | Feb 21 12:57:58 PM PST 24 |
| Peak memory | 211492 kb |
| Host | smart-e1546712-9ecd-42fb-93c0-9b60c598c7a5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728772829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.1728772829 |
| Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.2711071472 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 13785450484 ps |
| CPU time | 281.69 seconds |
| Started | Feb 21 12:56:45 PM PST 24 |
| Finished | Feb 21 01:01:27 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-9f1f99c8-6c88-4ad9-ab96-b0c5ea322135 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711071472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2711071472 |
| Directory | /workspace/4.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.2853468267 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 148004835539 ps |
| CPU time | 1354.27 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 01:19:21 PM PST 24 |
| Peak memory | 379344 kb |
| Host | smart-8c5839d5-2373-405d-aab4-4d2cb6179654 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853468267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.2853468267 |
| Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.2927977715 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1465109242 ps |
| CPU time | 108.95 seconds |
| Started | Feb 21 12:56:41 PM PST 24 |
| Finished | Feb 21 12:58:31 PM PST 24 |
| Peak memory | 353852 kb |
| Host | smart-d43626df-7e59-446c-bcc1-21274264209a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927977715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.2927977715 |
| Directory | /workspace/4.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1551362628 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 25799606538 ps |
| CPU time | 394.78 seconds |
| Started | Feb 21 12:56:56 PM PST 24 |
| Finished | Feb 21 01:03:33 PM PST 24 |
| Peak memory | 210616 kb |
| Host | smart-e53035a2-ba8c-4c83-b37e-39462afc6e1e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551362628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.1551362628 |
| Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.4293959594 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2095925810 ps |
| CPU time | 6.33 seconds |
| Started | Feb 21 12:56:41 PM PST 24 |
| Finished | Feb 21 12:56:48 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-799043a4-7a7f-45e6-8958-b44f66fcde9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293959594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4293959594 |
| Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_regwen.3372267280 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1297991303 ps |
| CPU time | 192.06 seconds |
| Started | Feb 21 12:56:40 PM PST 24 |
| Finished | Feb 21 12:59:52 PM PST 24 |
| Peak memory | 354180 kb |
| Host | smart-e634633d-ee53-442f-bfc4-bfcff6924463 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372267280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3372267280 |
| Directory | /workspace/4.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.2327246986 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 223622401 ps |
| CPU time | 1.9 seconds |
| Started | Feb 21 12:56:50 PM PST 24 |
| Finished | Feb 21 12:56:52 PM PST 24 |
| Peak memory | 221024 kb |
| Host | smart-5c1f4823-8598-40a0-92dc-23a5c4b9a788 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327246986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2327246986 |
| Directory | /workspace/4.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_smoke.2449318224 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 462228734 ps |
| CPU time | 137.98 seconds |
| Started | Feb 21 12:56:44 PM PST 24 |
| Finished | Feb 21 12:59:03 PM PST 24 |
| Peak memory | 373380 kb |
| Host | smart-f3d9b132-066c-49d8-8f2d-4e943dda3eae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449318224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2449318224 |
| Directory | /workspace/4.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.648569929 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 16523653085 ps |
| CPU time | 305.63 seconds |
| Started | Feb 21 12:56:42 PM PST 24 |
| Finished | Feb 21 01:01:48 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-b5630d0f-7c41-46a3-a1ef-33d6dc9f5512 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648569929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_stress_pipeline.648569929 |
| Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4092097189 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3131945186 ps |
| CPU time | 138.88 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 12:59:05 PM PST 24 |
| Peak memory | 365280 kb |
| Host | smart-fea82259-dd3a-4304-baec-121fc1f41485 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092097189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.4092097189 |
| Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2037966437 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 9737963282 ps |
| CPU time | 587 seconds |
| Started | Feb 21 01:00:43 PM PST 24 |
| Finished | Feb 21 01:10:30 PM PST 24 |
| Peak memory | 372132 kb |
| Host | smart-81372d5e-d306-4ec1-b28b-6066d6605bb1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037966437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2037966437 |
| Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.1723919661 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 14932005 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:00:42 PM PST 24 |
| Finished | Feb 21 01:00:43 PM PST 24 |
| Peak memory | 201892 kb |
| Host | smart-65ca6daa-8d40-4758-8454-0c02e99ddcae |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723919661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1723919661 |
| Directory | /workspace/40.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_bijection.694010463 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 105172445472 ps |
| CPU time | 1774.7 seconds |
| Started | Feb 21 01:00:28 PM PST 24 |
| Finished | Feb 21 01:30:03 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-0c50b0db-8619-41cf-8c38-35bca7b54fa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694010463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection. 694010463 |
| Directory | /workspace/40.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.817149730 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 30167489555 ps |
| CPU time | 150.96 seconds |
| Started | Feb 21 01:00:42 PM PST 24 |
| Finished | Feb 21 01:03:14 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-d39b6858-a7d8-4ee6-9679-3d61a484f424 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817149730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc alation.817149730 |
| Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.623505354 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3073469036 ps |
| CPU time | 88.48 seconds |
| Started | Feb 21 01:00:32 PM PST 24 |
| Finished | Feb 21 01:02:01 PM PST 24 |
| Peak memory | 330128 kb |
| Host | smart-db2a80e4-a63e-43dc-99be-2d10347f21a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623505354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.sram_ctrl_max_throughput.623505354 |
| Directory | /workspace/40.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2219245377 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 9353105604 ps |
| CPU time | 83.56 seconds |
| Started | Feb 21 01:00:43 PM PST 24 |
| Finished | Feb 21 01:02:07 PM PST 24 |
| Peak memory | 218756 kb |
| Host | smart-0f3abd0f-536d-45a9-84f0-a1ef61d88a7a |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219245377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.2219245377 |
| Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.4212991546 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 8221817849 ps |
| CPU time | 126.72 seconds |
| Started | Feb 21 01:00:44 PM PST 24 |
| Finished | Feb 21 01:02:51 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-de885234-046a-45c0-a3f9-69d7eaee8064 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212991546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.4212991546 |
| Directory | /workspace/40.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.2944973149 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 17504045857 ps |
| CPU time | 865.18 seconds |
| Started | Feb 21 01:00:31 PM PST 24 |
| Finished | Feb 21 01:14:57 PM PST 24 |
| Peak memory | 378360 kb |
| Host | smart-af9254b2-f785-4a35-a6bd-27af58cad68b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944973149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.2944973149 |
| Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.583085895 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3432151993 ps |
| CPU time | 105.62 seconds |
| Started | Feb 21 01:00:31 PM PST 24 |
| Finished | Feb 21 01:02:17 PM PST 24 |
| Peak memory | 349480 kb |
| Host | smart-c30b7b43-1ecd-42a9-975d-d68fa394cecc |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583085895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.583085895 |
| Directory | /workspace/40.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.263395489 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 107580267645 ps |
| CPU time | 516.83 seconds |
| Started | Feb 21 01:00:28 PM PST 24 |
| Finished | Feb 21 01:09:05 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-8b3dc407-436e-40cc-a194-58496f80351e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263395489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_partial_access_b2b.263395489 |
| Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.3602697811 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1532936936 ps |
| CPU time | 6.86 seconds |
| Started | Feb 21 01:00:44 PM PST 24 |
| Finished | Feb 21 01:00:52 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-ff0d4632-f77e-4e35-af52-7f4954e006f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602697811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3602697811 |
| Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_regwen.3644636307 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3962403803 ps |
| CPU time | 762.28 seconds |
| Started | Feb 21 01:00:44 PM PST 24 |
| Finished | Feb 21 01:13:27 PM PST 24 |
| Peak memory | 362936 kb |
| Host | smart-8edacd68-1792-4262-8057-9333754779f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644636307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3644636307 |
| Directory | /workspace/40.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_smoke.812679638 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6400726335 ps |
| CPU time | 39.71 seconds |
| Started | Feb 21 01:00:28 PM PST 24 |
| Finished | Feb 21 01:01:08 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-c3e89688-e57a-4027-8235-de672589c96e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812679638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.812679638 |
| Directory | /workspace/40.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.224355795 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 5740094986 ps |
| CPU time | 385.21 seconds |
| Started | Feb 21 01:00:26 PM PST 24 |
| Finished | Feb 21 01:06:52 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-15c1c224-7bca-452e-b026-68d7fda71e98 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224355795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_stress_pipeline.224355795 |
| Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.286996869 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 730849823 ps |
| CPU time | 33.29 seconds |
| Started | Feb 21 01:00:43 PM PST 24 |
| Finished | Feb 21 01:01:17 PM PST 24 |
| Peak memory | 236636 kb |
| Host | smart-9094e640-7250-44cc-9fdf-7b838e189be6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286996869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.286996869 |
| Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1447289548 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 38738528600 ps |
| CPU time | 1120.61 seconds |
| Started | Feb 21 01:00:42 PM PST 24 |
| Finished | Feb 21 01:19:23 PM PST 24 |
| Peak memory | 362956 kb |
| Host | smart-13658aea-2739-45bb-ab0b-6b9a7cff2f57 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447289548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.1447289548 |
| Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.1588091072 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 19672185 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:00:59 PM PST 24 |
| Finished | Feb 21 01:00:59 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-bab98575-c68c-44ee-a2c1-091f135977c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588091072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1588091072 |
| Directory | /workspace/41.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_bijection.3852000841 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 114806165882 ps |
| CPU time | 2185.81 seconds |
| Started | Feb 21 01:00:45 PM PST 24 |
| Finished | Feb 21 01:37:11 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-336145e6-6adb-4076-973c-0594bbeafa95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852000841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .3852000841 |
| Directory | /workspace/41.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.3115578446 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14246120552 ps |
| CPU time | 128.28 seconds |
| Started | Feb 21 01:00:43 PM PST 24 |
| Finished | Feb 21 01:02:52 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-a9fba493-ecdb-421f-8060-00dfab973260 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115578446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3115578446 |
| Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.4199017019 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2998201858 ps |
| CPU time | 32.44 seconds |
| Started | Feb 21 01:00:48 PM PST 24 |
| Finished | Feb 21 01:01:21 PM PST 24 |
| Peak memory | 241856 kb |
| Host | smart-375a52db-cf13-4d79-be3f-9ff6e192c793 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199017019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.4199017019 |
| Directory | /workspace/41.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2066739107 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3704121278 ps |
| CPU time | 80.81 seconds |
| Started | Feb 21 01:00:55 PM PST 24 |
| Finished | Feb 21 01:02:16 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-67e65d2b-5cf9-472c-a561-6b44cdf7d6c6 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066739107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.2066739107 |
| Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.2745532297 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 32903090679 ps |
| CPU time | 138.31 seconds |
| Started | Feb 21 01:01:03 PM PST 24 |
| Finished | Feb 21 01:03:23 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-6ba687a5-9ee4-451e-ad63-d511cf25df80 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745532297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2745532297 |
| Directory | /workspace/41.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.2186099977 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 24900805778 ps |
| CPU time | 1520.32 seconds |
| Started | Feb 21 01:00:47 PM PST 24 |
| Finished | Feb 21 01:26:09 PM PST 24 |
| Peak memory | 375456 kb |
| Host | smart-fbdee504-580b-4902-92b6-a71a5b901184 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186099977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.2186099977 |
| Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.2198582119 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 9139611719 ps |
| CPU time | 21.75 seconds |
| Started | Feb 21 01:00:46 PM PST 24 |
| Finished | Feb 21 01:01:08 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-eeabcbb3-1796-415e-8a05-deced41fcfb1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198582119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.2198582119 |
| Directory | /workspace/41.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2833290432 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13998119182 ps |
| CPU time | 352.97 seconds |
| Started | Feb 21 01:00:42 PM PST 24 |
| Finished | Feb 21 01:06:35 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-571a5d49-0470-4938-b498-a029780952a1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833290432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.2833290432 |
| Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.439985149 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 633637753 ps |
| CPU time | 6.56 seconds |
| Started | Feb 21 01:00:56 PM PST 24 |
| Finished | Feb 21 01:01:02 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-8485b1e4-b436-415a-8dd7-b2d2204d133b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439985149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.439985149 |
| Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_regwen.33000476 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 15329355767 ps |
| CPU time | 864.65 seconds |
| Started | Feb 21 01:00:46 PM PST 24 |
| Finished | Feb 21 01:15:11 PM PST 24 |
| Peak memory | 379392 kb |
| Host | smart-42bae0ab-949b-441d-ba13-8d56bcfe8313 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.33000476 |
| Directory | /workspace/41.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_smoke.183040172 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1256230212 ps |
| CPU time | 13.72 seconds |
| Started | Feb 21 01:00:43 PM PST 24 |
| Finished | Feb 21 01:00:57 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-e6bb9ef1-36b6-4ec9-9441-64bbfa4d0ee5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183040172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.183040172 |
| Directory | /workspace/41.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2208206823 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 21042434614 ps |
| CPU time | 428.77 seconds |
| Started | Feb 21 01:00:45 PM PST 24 |
| Finished | Feb 21 01:07:54 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-7000861f-31d1-464c-9414-9b0a4c7d5f0b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208206823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.2208206823 |
| Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1295881218 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2981995121 ps |
| CPU time | 44.01 seconds |
| Started | Feb 21 01:00:43 PM PST 24 |
| Finished | Feb 21 01:01:28 PM PST 24 |
| Peak memory | 273288 kb |
| Host | smart-6365d53e-a745-411e-b28c-606140599654 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295881218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1295881218 |
| Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.742268257 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 9348067809 ps |
| CPU time | 600.98 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:10:58 PM PST 24 |
| Peak memory | 345560 kb |
| Host | smart-20fb1015-2d7a-472f-88c1-91f73b4c031b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742268257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sram_ctrl_access_during_key_req.742268257 |
| Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.983193229 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 38489131 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:00:56 PM PST 24 |
| Finished | Feb 21 01:00:57 PM PST 24 |
| Peak memory | 202132 kb |
| Host | smart-d54325b4-abbc-4898-9ab9-fd24c7aeb943 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983193229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.983193229 |
| Directory | /workspace/42.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_bijection.253004205 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 32476251260 ps |
| CPU time | 742.29 seconds |
| Started | Feb 21 01:00:56 PM PST 24 |
| Finished | Feb 21 01:13:18 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-0a46f3d1-5626-4867-910f-806169903482 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253004205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection. 253004205 |
| Directory | /workspace/42.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.924250484 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 8487462921 ps |
| CPU time | 77.36 seconds |
| Started | Feb 21 01:01:04 PM PST 24 |
| Finished | Feb 21 01:02:22 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-a28659b9-2a4a-42e8-9268-41c91b11eb94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924250484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc alation.924250484 |
| Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.2339802387 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 4185931436 ps |
| CPU time | 28.9 seconds |
| Started | Feb 21 01:01:03 PM PST 24 |
| Finished | Feb 21 01:01:33 PM PST 24 |
| Peak memory | 210876 kb |
| Host | smart-cad835d9-bc27-445a-876f-0f417e6103b2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339802387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2339802387 |
| Directory | /workspace/42.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.742036482 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 10893370107 ps |
| CPU time | 80.53 seconds |
| Started | Feb 21 01:01:05 PM PST 24 |
| Finished | Feb 21 01:02:26 PM PST 24 |
| Peak memory | 212032 kb |
| Host | smart-b1769691-644c-4e30-9d5a-fe964e1e7a28 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742036482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_mem_partial_access.742036482 |
| Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.2586870986 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 21515400104 ps |
| CPU time | 147.24 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:03:26 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-543a98ff-7fb7-4b84-ac7e-3c50073695de |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586870986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.2586870986 |
| Directory | /workspace/42.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.503769197 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 3245924370 ps |
| CPU time | 464.91 seconds |
| Started | Feb 21 01:00:58 PM PST 24 |
| Finished | Feb 21 01:08:44 PM PST 24 |
| Peak memory | 371148 kb |
| Host | smart-f742f3bf-ac9a-4cf2-9063-24932a87d6ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503769197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip le_keys.503769197 |
| Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.1207549865 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 5112998298 ps |
| CPU time | 23.54 seconds |
| Started | Feb 21 01:00:59 PM PST 24 |
| Finished | Feb 21 01:01:23 PM PST 24 |
| Peak memory | 210608 kb |
| Host | smart-879f76eb-8229-453c-a97c-e38c1b140e7c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207549865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.1207549865 |
| Directory | /workspace/42.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.64010236 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 17603779872 ps |
| CPU time | 382.12 seconds |
| Started | Feb 21 01:00:58 PM PST 24 |
| Finished | Feb 21 01:07:21 PM PST 24 |
| Peak memory | 202312 kb |
| Host | smart-01e90988-5ff7-4f5b-b573-b6508c6bcf78 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64010236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_partial_access_b2b.64010236 |
| Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.170316326 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 935454676 ps |
| CPU time | 5.49 seconds |
| Started | Feb 21 01:00:56 PM PST 24 |
| Finished | Feb 21 01:01:02 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-f1548679-3ed4-4309-8292-574c7dd44b8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170316326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.170316326 |
| Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_regwen.3510454017 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2888604916 ps |
| CPU time | 514.92 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:09:33 PM PST 24 |
| Peak memory | 379232 kb |
| Host | smart-fd88c896-e3d0-4e34-9582-b4ae2a6044f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510454017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3510454017 |
| Directory | /workspace/42.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_smoke.3074193160 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 787202613 ps |
| CPU time | 113.16 seconds |
| Started | Feb 21 01:00:58 PM PST 24 |
| Finished | Feb 21 01:02:52 PM PST 24 |
| Peak memory | 331200 kb |
| Host | smart-066d9d88-3eb0-4900-b77f-bedbe4c4c661 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074193160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3074193160 |
| Directory | /workspace/42.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.1335235577 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 121824323741 ps |
| CPU time | 3545.98 seconds |
| Started | Feb 21 01:00:56 PM PST 24 |
| Finished | Feb 21 02:00:03 PM PST 24 |
| Peak memory | 385472 kb |
| Host | smart-f1c789ed-5ad9-4b8b-a08e-46e9e5c3af00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335235577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1335235577 |
| Directory | /workspace/42.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.918299259 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 6669096958 ps |
| CPU time | 226.86 seconds |
| Started | Feb 21 01:01:04 PM PST 24 |
| Finished | Feb 21 01:04:51 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-0e5a08f7-a0fe-4f80-8508-dea0fbfdd600 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918299259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_stress_pipeline.918299259 |
| Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2500793187 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7642484751 ps |
| CPU time | 126.79 seconds |
| Started | Feb 21 01:00:55 PM PST 24 |
| Finished | Feb 21 01:03:02 PM PST 24 |
| Peak memory | 343712 kb |
| Host | smart-beb68cd5-15c2-4afe-8b77-051612b4f14a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500793187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2500793187 |
| Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.547644359 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 13713658119 ps |
| CPU time | 1121.42 seconds |
| Started | Feb 21 01:00:56 PM PST 24 |
| Finished | Feb 21 01:19:38 PM PST 24 |
| Peak memory | 378440 kb |
| Host | smart-e2f2bc10-4058-4bbf-a648-1f90da3deabf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547644359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 43.sram_ctrl_access_during_key_req.547644359 |
| Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.2692049855 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 45709821 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:01:22 PM PST 24 |
| Finished | Feb 21 01:01:23 PM PST 24 |
| Peak memory | 201924 kb |
| Host | smart-1287d884-ad6e-488d-a893-81fd293ead19 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692049855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2692049855 |
| Directory | /workspace/43.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_bijection.610733898 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 24246381948 ps |
| CPU time | 503.71 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:09:21 PM PST 24 |
| Peak memory | 210632 kb |
| Host | smart-2a686775-5be2-4407-af83-a02290202c1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610733898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection. 610733898 |
| Directory | /workspace/43.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_executable.3573928898 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5119400365 ps |
| CPU time | 129.07 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:03:07 PM PST 24 |
| Peak memory | 298424 kb |
| Host | smart-aabdd461-b3f8-44c7-9211-7a23c0bf69f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573928898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.3573928898 |
| Directory | /workspace/43.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.2437552665 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 9665808262 ps |
| CPU time | 46.57 seconds |
| Started | Feb 21 01:01:03 PM PST 24 |
| Finished | Feb 21 01:01:50 PM PST 24 |
| Peak memory | 214324 kb |
| Host | smart-43bb4be7-8703-4d06-ab96-0c350f492518 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437552665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2437552665 |
| Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.51649892 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1509650355 ps |
| CPU time | 107.52 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:02:45 PM PST 24 |
| Peak memory | 354612 kb |
| Host | smart-4124b844-7f47-4eb6-9aa9-3e6484d774ea |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51649892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 43.sram_ctrl_max_throughput.51649892 |
| Directory | /workspace/43.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1114932003 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3925434696 ps |
| CPU time | 73.27 seconds |
| Started | Feb 21 01:01:18 PM PST 24 |
| Finished | Feb 21 01:02:33 PM PST 24 |
| Peak memory | 211548 kb |
| Host | smart-615af9dd-2317-477a-8fb7-b01f40020207 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114932003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.1114932003 |
| Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.3762663221 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6879960037 ps |
| CPU time | 137.44 seconds |
| Started | Feb 21 01:01:20 PM PST 24 |
| Finished | Feb 21 01:03:39 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-c1d2c492-aa30-4486-9f61-63ca71a81961 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762663221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3762663221 |
| Directory | /workspace/43.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.992986437 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 22404957793 ps |
| CPU time | 1470.22 seconds |
| Started | Feb 21 01:00:58 PM PST 24 |
| Finished | Feb 21 01:25:29 PM PST 24 |
| Peak memory | 377252 kb |
| Host | smart-8f220d44-a61d-4794-b194-82e553cf9008 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992986437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip le_keys.992986437 |
| Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.3952183925 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1937106285 ps |
| CPU time | 23.01 seconds |
| Started | Feb 21 01:00:55 PM PST 24 |
| Finished | Feb 21 01:01:19 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-7842149d-616b-4f46-bb15-e72a4f1187e2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952183925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.3952183925 |
| Directory | /workspace/43.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2859530163 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 19382770301 ps |
| CPU time | 447.91 seconds |
| Started | Feb 21 01:01:04 PM PST 24 |
| Finished | Feb 21 01:08:33 PM PST 24 |
| Peak memory | 202124 kb |
| Host | smart-686d0043-6ab3-4b78-9770-262b78a77862 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859530163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.2859530163 |
| Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.3598559433 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 360132209 ps |
| CPU time | 5.63 seconds |
| Started | Feb 21 01:01:17 PM PST 24 |
| Finished | Feb 21 01:01:24 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-83bc1996-5209-492c-b33b-0aee86464670 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598559433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3598559433 |
| Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_smoke.4031440690 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1951594323 ps |
| CPU time | 13.8 seconds |
| Started | Feb 21 01:00:59 PM PST 24 |
| Finished | Feb 21 01:01:14 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-85595391-70e9-4f80-8c5e-06cfaeca9608 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031440690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4031440690 |
| Directory | /workspace/43.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.1371824281 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 235373546820 ps |
| CPU time | 1636.35 seconds |
| Started | Feb 21 01:01:17 PM PST 24 |
| Finished | Feb 21 01:28:34 PM PST 24 |
| Peak memory | 375808 kb |
| Host | smart-4705a725-9b5f-4969-b7e1-8c2861266c15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371824281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.1371824281 |
| Directory | /workspace/43.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2207086649 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 7884629839 ps |
| CPU time | 296.54 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:05:55 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-5235ee7e-89bb-4dc3-a628-712d909699f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207086649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.2207086649 |
| Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2557043413 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1473005193 ps |
| CPU time | 36.27 seconds |
| Started | Feb 21 01:00:57 PM PST 24 |
| Finished | Feb 21 01:01:35 PM PST 24 |
| Peak memory | 237756 kb |
| Host | smart-ae61a984-d9fe-4260-b0b8-879105a63396 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557043413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2557043413 |
| Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1304865572 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 18050760885 ps |
| CPU time | 715.46 seconds |
| Started | Feb 21 01:01:19 PM PST 24 |
| Finished | Feb 21 01:13:16 PM PST 24 |
| Peak memory | 379244 kb |
| Host | smart-770f3207-1071-4152-87a3-c571daf98179 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304865572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.1304865572 |
| Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.4025962726 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 36529079 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 01:01:20 PM PST 24 |
| Finished | Feb 21 01:01:22 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-627c80b7-1b3f-4338-8a23-99d3e9c5c895 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025962726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.4025962726 |
| Directory | /workspace/44.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2765705657 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 42094228410 ps |
| CPU time | 757.36 seconds |
| Started | Feb 21 01:01:20 PM PST 24 |
| Finished | Feb 21 01:13:59 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-ce2e0ef6-2c3b-43ea-9ec5-b41036e3ecc8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765705657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2765705657 |
| Directory | /workspace/44.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2639974034 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1923015541 ps |
| CPU time | 27 seconds |
| Started | Feb 21 01:01:21 PM PST 24 |
| Finished | Feb 21 01:01:49 PM PST 24 |
| Peak memory | 210568 kb |
| Host | smart-ce9d4ab1-7c55-4220-a86f-80fee1810de6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639974034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2639974034 |
| Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.525885218 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2744588342 ps |
| CPU time | 32.52 seconds |
| Started | Feb 21 01:01:16 PM PST 24 |
| Finished | Feb 21 01:01:50 PM PST 24 |
| Peak memory | 235212 kb |
| Host | smart-714a0307-d5be-453a-a230-2fe782f1bf46 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525885218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.sram_ctrl_max_throughput.525885218 |
| Directory | /workspace/44.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1903247176 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 8682792472 ps |
| CPU time | 144.46 seconds |
| Started | Feb 21 01:01:20 PM PST 24 |
| Finished | Feb 21 01:03:46 PM PST 24 |
| Peak memory | 214820 kb |
| Host | smart-1a0b835c-9798-497e-9711-961bb16f416e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903247176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.1903247176 |
| Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.3156547213 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 43099981304 ps |
| CPU time | 316.68 seconds |
| Started | Feb 21 01:01:15 PM PST 24 |
| Finished | Feb 21 01:06:32 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-e94af8d1-5ced-4402-9d05-aeefedac6a6a |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156547213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.3156547213 |
| Directory | /workspace/44.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.344778388 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 61324108517 ps |
| CPU time | 1507.17 seconds |
| Started | Feb 21 01:01:18 PM PST 24 |
| Finished | Feb 21 01:26:27 PM PST 24 |
| Peak memory | 371192 kb |
| Host | smart-af19cd85-06b8-44f3-9b41-2da79de5cd2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344778388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multip le_keys.344778388 |
| Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.508686283 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 518753097 ps |
| CPU time | 100.84 seconds |
| Started | Feb 21 01:01:18 PM PST 24 |
| Finished | Feb 21 01:03:01 PM PST 24 |
| Peak memory | 355652 kb |
| Host | smart-e60fc9dd-a20a-4203-93d7-6e1f6c0e55cc |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508686283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.508686283 |
| Directory | /workspace/44.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.438105126 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 75367153911 ps |
| CPU time | 446.32 seconds |
| Started | Feb 21 01:01:18 PM PST 24 |
| Finished | Feb 21 01:08:47 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-3dc31229-c2f5-4949-befb-0a645233d9a3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438105126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.sram_ctrl_partial_access_b2b.438105126 |
| Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2677460557 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 509581181 ps |
| CPU time | 13.79 seconds |
| Started | Feb 21 01:01:16 PM PST 24 |
| Finished | Feb 21 01:01:31 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-66435b1d-bca8-4cc7-bee2-67c6e5ea2fa4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677460557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2677460557 |
| Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_regwen.1002183566 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 12520747274 ps |
| CPU time | 196.75 seconds |
| Started | Feb 21 01:01:16 PM PST 24 |
| Finished | Feb 21 01:04:33 PM PST 24 |
| Peak memory | 375432 kb |
| Host | smart-a762bb57-a61d-4d37-a420-9bd854230d4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002183566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1002183566 |
| Directory | /workspace/44.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_smoke.1509974260 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3563213756 ps |
| CPU time | 23.99 seconds |
| Started | Feb 21 01:01:17 PM PST 24 |
| Finished | Feb 21 01:01:43 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-52d52949-456a-4692-b538-987255f4b254 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509974260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1509974260 |
| Directory | /workspace/44.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3504793556 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 11012354463 ps |
| CPU time | 374.15 seconds |
| Started | Feb 21 01:01:15 PM PST 24 |
| Finished | Feb 21 01:07:29 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-9b28bf45-1ce9-4272-8e46-3f704898874a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504793556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3504793556 |
| Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4248856473 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1568834402 ps |
| CPU time | 49.37 seconds |
| Started | Feb 21 01:01:27 PM PST 24 |
| Finished | Feb 21 01:02:16 PM PST 24 |
| Peak memory | 275868 kb |
| Host | smart-2d9add4a-8ebc-4e49-a5c9-4450dec38df6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248856473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.4248856473 |
| Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.4197744711 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 20202024423 ps |
| CPU time | 522.53 seconds |
| Started | Feb 21 01:01:19 PM PST 24 |
| Finished | Feb 21 01:10:04 PM PST 24 |
| Peak memory | 347604 kb |
| Host | smart-403dcebc-8f49-41f1-8555-a79ce9d317dc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197744711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.4197744711 |
| Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.1453844326 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 34775024 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:01:31 PM PST 24 |
| Peak memory | 201944 kb |
| Host | smart-426532f7-2527-4a23-9fcd-51984c275939 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453844326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1453844326 |
| Directory | /workspace/45.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_bijection.2870627705 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 249199940118 ps |
| CPU time | 1014.33 seconds |
| Started | Feb 21 01:01:16 PM PST 24 |
| Finished | Feb 21 01:18:11 PM PST 24 |
| Peak memory | 202332 kb |
| Host | smart-6b42132c-ab7e-48a2-9779-89fa361e4162 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870627705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .2870627705 |
| Directory | /workspace/45.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1433355407 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 22049020763 ps |
| CPU time | 68.38 seconds |
| Started | Feb 21 01:01:19 PM PST 24 |
| Finished | Feb 21 01:02:29 PM PST 24 |
| Peak memory | 210536 kb |
| Host | smart-a482261b-5c1d-4570-bb34-b53f9798e7f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433355407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.1433355407 |
| Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.3601235358 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1436303765 ps |
| CPU time | 53.71 seconds |
| Started | Feb 21 01:01:17 PM PST 24 |
| Finished | Feb 21 01:02:11 PM PST 24 |
| Peak memory | 283984 kb |
| Host | smart-4a2dd02a-a0c8-4911-96b4-43ab74f96ef7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601235358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.3601235358 |
| Directory | /workspace/45.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3993075130 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1060618131 ps |
| CPU time | 74.36 seconds |
| Started | Feb 21 01:01:20 PM PST 24 |
| Finished | Feb 21 01:02:36 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-84045592-194b-4d9a-8b6d-9fea461be697 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993075130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3993075130 |
| Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.3896921514 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 86009467377 ps |
| CPU time | 131.89 seconds |
| Started | Feb 21 01:01:27 PM PST 24 |
| Finished | Feb 21 01:03:39 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-9a9b1796-e1bc-4afa-98b8-75a118729776 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896921514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.3896921514 |
| Directory | /workspace/45.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.3605104819 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 10898618886 ps |
| CPU time | 739.1 seconds |
| Started | Feb 21 01:01:22 PM PST 24 |
| Finished | Feb 21 01:13:41 PM PST 24 |
| Peak memory | 375252 kb |
| Host | smart-fcc8cc34-c848-419c-ab2a-b5af07b300d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605104819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.3605104819 |
| Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.3473729020 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 3253530075 ps |
| CPU time | 34.79 seconds |
| Started | Feb 21 01:01:26 PM PST 24 |
| Finished | Feb 21 01:02:01 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-c0343dc8-56e5-4337-8c01-dcd56b6c040a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473729020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.3473729020 |
| Directory | /workspace/45.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2977655731 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 22271811312 ps |
| CPU time | 438.14 seconds |
| Started | Feb 21 01:01:16 PM PST 24 |
| Finished | Feb 21 01:08:35 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-bba27fa4-02a3-4255-9d1d-2ce2eadee06f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977655731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.2977655731 |
| Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.748390061 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1357279964 ps |
| CPU time | 13.38 seconds |
| Started | Feb 21 01:01:18 PM PST 24 |
| Finished | Feb 21 01:01:34 PM PST 24 |
| Peak memory | 202560 kb |
| Host | smart-cbb5b7c4-102d-4007-8c46-4bbaebc2f419 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748390061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.748390061 |
| Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_regwen.1615353516 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 17961728104 ps |
| CPU time | 1508.05 seconds |
| Started | Feb 21 01:01:20 PM PST 24 |
| Finished | Feb 21 01:26:30 PM PST 24 |
| Peak memory | 372392 kb |
| Host | smart-364af8d1-f861-4545-b8ef-bbafd2a7cb7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615353516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1615353516 |
| Directory | /workspace/45.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_smoke.4102511143 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 798960634 ps |
| CPU time | 118.94 seconds |
| Started | Feb 21 01:01:15 PM PST 24 |
| Finished | Feb 21 01:03:14 PM PST 24 |
| Peak memory | 336248 kb |
| Host | smart-c433215b-e0f5-49f0-896c-0673ae91c8b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102511143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.4102511143 |
| Directory | /workspace/45.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.4290841645 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 12213414492 ps |
| CPU time | 233.98 seconds |
| Started | Feb 21 01:01:16 PM PST 24 |
| Finished | Feb 21 01:05:11 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-df569047-2ed6-421f-a8b8-19c003770aab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290841645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.4290841645 |
| Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3653257023 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1402635208 ps |
| CPU time | 30.22 seconds |
| Started | Feb 21 01:01:22 PM PST 24 |
| Finished | Feb 21 01:01:52 PM PST 24 |
| Peak memory | 218824 kb |
| Host | smart-a34ff411-f19d-4c0a-a2e9-1a18167c32f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653257023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3653257023 |
| Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3977995865 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 197696141600 ps |
| CPU time | 1243.56 seconds |
| Started | Feb 21 01:01:32 PM PST 24 |
| Finished | Feb 21 01:22:16 PM PST 24 |
| Peak memory | 377224 kb |
| Host | smart-70b4d7b1-72d8-4bee-b52d-78e7b459ecd6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977995865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.3977995865 |
| Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1352145233 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14846986 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:01:32 PM PST 24 |
| Peak memory | 201932 kb |
| Host | smart-c7deaa7b-387d-4b78-ae83-af590696236e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352145233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1352145233 |
| Directory | /workspace/46.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_bijection.2403723129 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 324143789934 ps |
| CPU time | 2046.26 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:35:37 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-ecf6c6e6-2089-4e59-822d-ac0e4bdce54d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403723129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .2403723129 |
| Directory | /workspace/46.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.3163950249 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 13568584474 ps |
| CPU time | 147.28 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:03:58 PM PST 24 |
| Peak memory | 210680 kb |
| Host | smart-e8324b6a-6a12-4334-a28f-c527e7b902f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163950249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.3163950249 |
| Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.1960521814 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2968555572 ps |
| CPU time | 45.28 seconds |
| Started | Feb 21 01:01:27 PM PST 24 |
| Finished | Feb 21 01:02:13 PM PST 24 |
| Peak memory | 278356 kb |
| Host | smart-5d6022ba-7cf6-41ff-8538-d0b888f68752 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960521814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.1960521814 |
| Directory | /workspace/46.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1481156865 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 54646362403 ps |
| CPU time | 166.34 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:04:17 PM PST 24 |
| Peak memory | 211440 kb |
| Host | smart-17c93251-77d4-44b7-a8bb-1018c5b6ddc6 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481156865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1481156865 |
| Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.3984739275 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 7249699747 ps |
| CPU time | 143.19 seconds |
| Started | Feb 21 01:01:27 PM PST 24 |
| Finished | Feb 21 01:03:51 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-209bd711-8b63-495c-82eb-2001ba6d7a39 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984739275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.3984739275 |
| Directory | /workspace/46.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.2701935166 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 23743326352 ps |
| CPU time | 1483.21 seconds |
| Started | Feb 21 01:01:28 PM PST 24 |
| Finished | Feb 21 01:26:12 PM PST 24 |
| Peak memory | 378332 kb |
| Host | smart-604b9f26-d827-41f7-bb84-55563843ce5a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701935166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.2701935166 |
| Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.4078694400 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 814319202 ps |
| CPU time | 14.44 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:01:44 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-9ae9c98c-eb2c-421c-a1e1-10a808fbbae9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078694400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.4078694400 |
| Directory | /workspace/46.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2062502484 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 17022007610 ps |
| CPU time | 197.49 seconds |
| Started | Feb 21 01:01:28 PM PST 24 |
| Finished | Feb 21 01:04:46 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-0366af48-2681-48bf-ba7d-a2c7cd314380 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062502484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.2062502484 |
| Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.1303396577 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 363984700 ps |
| CPU time | 13.6 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:01:44 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-10449ef9-54b5-46cf-b787-1681b8ad9d94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303396577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1303396577 |
| Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_regwen.4088939109 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 23365585198 ps |
| CPU time | 1303.12 seconds |
| Started | Feb 21 01:01:31 PM PST 24 |
| Finished | Feb 21 01:23:15 PM PST 24 |
| Peak memory | 379836 kb |
| Host | smart-77b681dc-ae09-46ac-8649-8c79a91d6eb4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088939109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.4088939109 |
| Directory | /workspace/46.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_smoke.2861915985 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 5221292037 ps |
| CPU time | 18.2 seconds |
| Started | Feb 21 01:01:32 PM PST 24 |
| Finished | Feb 21 01:01:51 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-31777a52-81f2-43c1-83db-eaec62789eae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861915985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2861915985 |
| Directory | /workspace/46.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.2881370409 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 45804779678 ps |
| CPU time | 3218.45 seconds |
| Started | Feb 21 01:01:33 PM PST 24 |
| Finished | Feb 21 01:55:12 PM PST 24 |
| Peak memory | 379316 kb |
| Host | smart-5654cd96-8646-4e8e-8847-c8bf0f03c67f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881370409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.2881370409 |
| Directory | /workspace/46.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3446057328 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2911252239 ps |
| CPU time | 206.89 seconds |
| Started | Feb 21 01:01:29 PM PST 24 |
| Finished | Feb 21 01:04:56 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-676216d4-2dea-47bd-b4f7-3e227fdb708b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446057328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3446057328 |
| Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1777045503 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1692077615 ps |
| CPU time | 124.07 seconds |
| Started | Feb 21 01:01:29 PM PST 24 |
| Finished | Feb 21 01:03:34 PM PST 24 |
| Peak memory | 362856 kb |
| Host | smart-154bd1f7-bb07-4ee1-89d3-2f89c7c3e2a1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777045503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.1777045503 |
| Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1209139653 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 88145013301 ps |
| CPU time | 921.66 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:17:07 PM PST 24 |
| Peak memory | 354712 kb |
| Host | smart-cfcd1628-ad66-4fb0-a09e-70d6163cc06c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209139653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.1209139653 |
| Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.683739369 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 82265896 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:01:46 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-b54ee50f-5418-43b9-8508-0a4f17edcf26 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683739369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.683739369 |
| Directory | /workspace/47.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_bijection.1523054726 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 267553343893 ps |
| CPU time | 2170.26 seconds |
| Started | Feb 21 01:01:28 PM PST 24 |
| Finished | Feb 21 01:37:38 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-9ef0fbd9-5410-4004-926d-b00383fa674c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523054726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .1523054726 |
| Directory | /workspace/47.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.903069809 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 36342360677 ps |
| CPU time | 128.08 seconds |
| Started | Feb 21 01:01:46 PM PST 24 |
| Finished | Feb 21 01:03:54 PM PST 24 |
| Peak memory | 210612 kb |
| Host | smart-98dd03b3-a440-403d-acda-4e1a1b20287c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903069809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc alation.903069809 |
| Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.604453683 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1616207622 ps |
| CPU time | 92.13 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:03:03 PM PST 24 |
| Peak memory | 337340 kb |
| Host | smart-83f68fbf-50a7-4731-9352-28e92fd40b15 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604453683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.sram_ctrl_max_throughput.604453683 |
| Directory | /workspace/47.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.140802971 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3783069879 ps |
| CPU time | 75.48 seconds |
| Started | Feb 21 01:01:43 PM PST 24 |
| Finished | Feb 21 01:02:59 PM PST 24 |
| Peak memory | 218676 kb |
| Host | smart-2fab153b-85d6-4dec-abcd-989c11c06677 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140802971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.140802971 |
| Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.2140815143 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 8585778112 ps |
| CPU time | 125.31 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:03:50 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-7005e17e-a609-4a85-9120-90a062c2cb8e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140815143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2140815143 |
| Directory | /workspace/47.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.1653150607 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 29118204813 ps |
| CPU time | 536.5 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:10:27 PM PST 24 |
| Peak memory | 355236 kb |
| Host | smart-12a95f68-7f7a-46e0-9036-d0e798887324 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653150607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.1653150607 |
| Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.3858383114 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3562250814 ps |
| CPU time | 29.69 seconds |
| Started | Feb 21 01:01:32 PM PST 24 |
| Finished | Feb 21 01:02:02 PM PST 24 |
| Peak memory | 201828 kb |
| Host | smart-9236af84-680e-43b8-9675-105b85ef7eda |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858383114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.3858383114 |
| Directory | /workspace/47.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3947021126 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 58730132573 ps |
| CPU time | 357.34 seconds |
| Started | Feb 21 01:01:28 PM PST 24 |
| Finished | Feb 21 01:07:25 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-b3273e15-1f10-4669-99b8-26ed3e1900a3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947021126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3947021126 |
| Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.1927522675 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 363953036 ps |
| CPU time | 5.62 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:01:51 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-f6466997-a2dc-48e8-aef1-5becaefaf8bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927522675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1927522675 |
| Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_regwen.1000797032 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 6323741451 ps |
| CPU time | 72.07 seconds |
| Started | Feb 21 01:01:44 PM PST 24 |
| Finished | Feb 21 01:02:56 PM PST 24 |
| Peak memory | 287152 kb |
| Host | smart-398cfaed-aa8a-400a-bf17-627ba23bc4ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000797032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1000797032 |
| Directory | /workspace/47.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_smoke.3543236374 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 809355984 ps |
| CPU time | 13.79 seconds |
| Started | Feb 21 01:01:32 PM PST 24 |
| Finished | Feb 21 01:01:46 PM PST 24 |
| Peak memory | 207520 kb |
| Host | smart-29e9d08d-b0c2-48e1-9fbb-fe5f6be29779 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543236374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3543236374 |
| Directory | /workspace/47.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1528776151 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3747687785 ps |
| CPU time | 277.8 seconds |
| Started | Feb 21 01:01:30 PM PST 24 |
| Finished | Feb 21 01:06:08 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-6f38976e-c9b6-4635-a0cb-fe92dfec36c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528776151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.1528776151 |
| Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2681906230 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 751501606 ps |
| CPU time | 47.74 seconds |
| Started | Feb 21 01:01:29 PM PST 24 |
| Finished | Feb 21 01:02:17 PM PST 24 |
| Peak memory | 275520 kb |
| Host | smart-f2b5842d-dfb1-4513-bec9-6fc3bcdfdda7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681906230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.2681906230 |
| Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.467010052 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2255821301 ps |
| CPU time | 259.83 seconds |
| Started | Feb 21 01:01:44 PM PST 24 |
| Finished | Feb 21 01:06:04 PM PST 24 |
| Peak memory | 362816 kb |
| Host | smart-dbd6e0f5-98f3-41a0-99c0-39ad8e8ad391 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467010052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 48.sram_ctrl_access_during_key_req.467010052 |
| Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.86841066 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 24777141 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 01:01:57 PM PST 24 |
| Finished | Feb 21 01:01:58 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-363284b9-43cd-42f9-ad00-a8d9e3cf7061 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86841066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_alert_test.86841066 |
| Directory | /workspace/48.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_bijection.2048631705 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 383291966169 ps |
| CPU time | 2009.92 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:35:16 PM PST 24 |
| Peak memory | 202400 kb |
| Host | smart-261ecb2f-1073-4947-b18f-3b6db1210a3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048631705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .2048631705 |
| Directory | /workspace/48.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_executable.4058338663 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 10279191216 ps |
| CPU time | 869.67 seconds |
| Started | Feb 21 01:01:44 PM PST 24 |
| Finished | Feb 21 01:16:14 PM PST 24 |
| Peak memory | 373300 kb |
| Host | smart-65044a5d-50c8-47dc-bccb-42d2618e9bcd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058338663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.4058338663 |
| Directory | /workspace/48.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.1557927601 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 49886454155 ps |
| CPU time | 123.74 seconds |
| Started | Feb 21 01:01:44 PM PST 24 |
| Finished | Feb 21 01:03:48 PM PST 24 |
| Peak memory | 210504 kb |
| Host | smart-c2f89799-018f-40ba-a920-ed10e108fd4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557927601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.1557927601 |
| Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.2531273817 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1436083533 ps |
| CPU time | 53.93 seconds |
| Started | Feb 21 01:01:43 PM PST 24 |
| Finished | Feb 21 01:02:37 PM PST 24 |
| Peak memory | 284156 kb |
| Host | smart-b0c37d08-fcae-4ba1-9a07-5852600b8974 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531273817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.2531273817 |
| Directory | /workspace/48.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3812256944 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1550676220 ps |
| CPU time | 134.68 seconds |
| Started | Feb 21 01:01:54 PM PST 24 |
| Finished | Feb 21 01:04:10 PM PST 24 |
| Peak memory | 214352 kb |
| Host | smart-f08e3ea2-bb4b-411f-b6a0-0a405e409b6d |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812256944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.3812256944 |
| Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.901911422 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 22457990451 ps |
| CPU time | 146.06 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:04:11 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-5aae193d-a6a0-4a01-99df-204be05b5783 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901911422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _mem_walk.901911422 |
| Directory | /workspace/48.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.723672473 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 29893966392 ps |
| CPU time | 668.34 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:12:54 PM PST 24 |
| Peak memory | 375820 kb |
| Host | smart-eaedc6e4-8ba7-4a70-9c7d-232fa3d3b8af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723672473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip le_keys.723672473 |
| Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.2295726627 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 781407578 ps |
| CPU time | 11.97 seconds |
| Started | Feb 21 01:01:45 PM PST 24 |
| Finished | Feb 21 01:01:57 PM PST 24 |
| Peak memory | 202320 kb |
| Host | smart-8da0dbd3-479e-4b67-94c0-0a47ba124f06 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295726627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.2295726627 |
| Directory | /workspace/48.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3595600970 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 10157722141 ps |
| CPU time | 245.01 seconds |
| Started | Feb 21 01:01:44 PM PST 24 |
| Finished | Feb 21 01:05:49 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-9607bdf1-e9c6-4e9d-a47b-a2cc607f02f1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595600970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.3595600970 |
| Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.593105504 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 350850838 ps |
| CPU time | 5.54 seconds |
| Started | Feb 21 01:01:48 PM PST 24 |
| Finished | Feb 21 01:01:54 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-6646d3ff-0d05-4ac5-9bfe-bd915c319c0e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593105504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.593105504 |
| Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_regwen.753581199 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2373527231 ps |
| CPU time | 481.75 seconds |
| Started | Feb 21 01:01:44 PM PST 24 |
| Finished | Feb 21 01:09:46 PM PST 24 |
| Peak memory | 367068 kb |
| Host | smart-92f1402c-492a-4dad-9363-ee6d3c4462f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753581199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.753581199 |
| Directory | /workspace/48.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_smoke.73243618 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1363178041 ps |
| CPU time | 15.25 seconds |
| Started | Feb 21 01:01:43 PM PST 24 |
| Finished | Feb 21 01:01:59 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-be9f6037-b433-4baa-a57a-9d925bf19cca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73243618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.73243618 |
| Directory | /workspace/48.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.4029869778 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 227231890033 ps |
| CPU time | 2083.43 seconds |
| Started | Feb 21 01:01:55 PM PST 24 |
| Finished | Feb 21 01:36:39 PM PST 24 |
| Peak memory | 380412 kb |
| Host | smart-f774c4d9-3f91-4818-a37d-baccd10a0356 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029869778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.4029869778 |
| Directory | /workspace/48.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3536489194 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 15001104915 ps |
| CPU time | 273.06 seconds |
| Started | Feb 21 01:01:48 PM PST 24 |
| Finished | Feb 21 01:06:22 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-fabf6611-c409-4b4c-9b04-75c26f35a7c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536489194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.3536489194 |
| Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.710542591 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1184867019 ps |
| CPU time | 138.29 seconds |
| Started | Feb 21 01:01:44 PM PST 24 |
| Finished | Feb 21 01:04:02 PM PST 24 |
| Peak memory | 347460 kb |
| Host | smart-69ee74f5-4142-4b95-9c25-54f949c393a8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710542591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.710542591 |
| Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4199195734 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 8094000363 ps |
| CPU time | 1405.86 seconds |
| Started | Feb 21 01:01:58 PM PST 24 |
| Finished | Feb 21 01:25:24 PM PST 24 |
| Peak memory | 374092 kb |
| Host | smart-cf15f7bb-2b1b-4436-80f1-a9c75322e36a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199195734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.4199195734 |
| Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.947191615 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 12397478 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:01:56 PM PST 24 |
| Finished | Feb 21 01:01:57 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-18555db2-45ee-444b-8895-2f3c2b8998df |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947191615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.947191615 |
| Directory | /workspace/49.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_bijection.2283942162 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 127043697982 ps |
| CPU time | 2103.63 seconds |
| Started | Feb 21 01:01:55 PM PST 24 |
| Finished | Feb 21 01:37:00 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-f8800287-5790-4b0a-9bb5-4b0659e83199 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283942162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2283942162 |
| Directory | /workspace/49.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.254452088 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 21892734236 ps |
| CPU time | 124.7 seconds |
| Started | Feb 21 01:01:54 PM PST 24 |
| Finished | Feb 21 01:04:00 PM PST 24 |
| Peak memory | 210628 kb |
| Host | smart-a868642f-0e24-434e-a3be-e81e60ec05b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254452088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_esc alation.254452088 |
| Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.3159908751 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2565564938 ps |
| CPU time | 28.08 seconds |
| Started | Feb 21 01:01:55 PM PST 24 |
| Finished | Feb 21 01:02:24 PM PST 24 |
| Peak memory | 210640 kb |
| Host | smart-86c9101f-0d02-4d78-b595-4e757cd4fda3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159908751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.3159908751 |
| Directory | /workspace/49.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.944686684 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4597675229 ps |
| CPU time | 145.78 seconds |
| Started | Feb 21 01:01:54 PM PST 24 |
| Finished | Feb 21 01:04:21 PM PST 24 |
| Peak memory | 211468 kb |
| Host | smart-2e6898a2-f28a-4bd0-92e1-f4014cbba721 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944686684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_mem_partial_access.944686684 |
| Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.1892862886 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 33282697276 ps |
| CPU time | 308.92 seconds |
| Started | Feb 21 01:01:58 PM PST 24 |
| Finished | Feb 21 01:07:07 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-5cfd8a48-7513-406f-bbaa-ae1d83338692 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892862886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1892862886 |
| Directory | /workspace/49.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.353131691 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 9940208893 ps |
| CPU time | 147.2 seconds |
| Started | Feb 21 01:01:57 PM PST 24 |
| Finished | Feb 21 01:04:24 PM PST 24 |
| Peak memory | 376168 kb |
| Host | smart-980c1cb1-b916-42b6-893e-829caaac4df2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353131691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip le_keys.353131691 |
| Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.1531469674 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 11548933770 ps |
| CPU time | 28.36 seconds |
| Started | Feb 21 01:01:54 PM PST 24 |
| Finished | Feb 21 01:02:24 PM PST 24 |
| Peak memory | 260884 kb |
| Host | smart-83115ee7-0de5-46d1-9978-d194c5774800 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531469674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.1531469674 |
| Directory | /workspace/49.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1341647906 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 10480997174 ps |
| CPU time | 429.45 seconds |
| Started | Feb 21 01:01:56 PM PST 24 |
| Finished | Feb 21 01:09:06 PM PST 24 |
| Peak memory | 210608 kb |
| Host | smart-8b3e1ae8-cb13-4d48-927e-f35febf01694 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341647906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1341647906 |
| Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.842083020 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1256492758 ps |
| CPU time | 13.39 seconds |
| Started | Feb 21 01:01:55 PM PST 24 |
| Finished | Feb 21 01:02:09 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-d27d736f-971b-4d20-93c4-7f8bce20207d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842083020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.842083020 |
| Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_regwen.497250819 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 11439111860 ps |
| CPU time | 328.69 seconds |
| Started | Feb 21 01:01:55 PM PST 24 |
| Finished | Feb 21 01:07:25 PM PST 24 |
| Peak memory | 370088 kb |
| Host | smart-962eb9b9-9955-43ec-b851-0e83b12b0887 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497250819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.497250819 |
| Directory | /workspace/49.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_smoke.2661366501 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 835772997 ps |
| CPU time | 34.21 seconds |
| Started | Feb 21 01:01:56 PM PST 24 |
| Finished | Feb 21 01:02:31 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-a2123901-9861-45b2-8ad0-7613ddb7f00d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661366501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2661366501 |
| Directory | /workspace/49.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.1891130386 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 183743493680 ps |
| CPU time | 3009.92 seconds |
| Started | Feb 21 01:01:56 PM PST 24 |
| Finished | Feb 21 01:52:07 PM PST 24 |
| Peak memory | 299192 kb |
| Host | smart-d5f2ca4e-5f92-4e61-a10c-efbc7c01ce47 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891130386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.1891130386 |
| Directory | /workspace/49.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3939633951 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3856550337 ps |
| CPU time | 262.98 seconds |
| Started | Feb 21 01:01:55 PM PST 24 |
| Finished | Feb 21 01:06:19 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-5848b0e8-7bca-4287-9a01-a641bb0dc690 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939633951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3939633951 |
| Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1754811315 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 786770359 ps |
| CPU time | 66.45 seconds |
| Started | Feb 21 01:01:54 PM PST 24 |
| Finished | Feb 21 01:03:02 PM PST 24 |
| Peak memory | 324036 kb |
| Host | smart-b10005ac-5ae6-4843-b390-2dab5e3e6357 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754811315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1754811315 |
| Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.286915331 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 12354917944 ps |
| CPU time | 2351.59 seconds |
| Started | Feb 21 12:56:49 PM PST 24 |
| Finished | Feb 21 01:36:01 PM PST 24 |
| Peak memory | 378368 kb |
| Host | smart-7251af3b-fad4-41e6-9a89-9b2150ccc811 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286915331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_access_during_key_req.286915331 |
| Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.841825571 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 46133748 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 12:57:07 PM PST 24 |
| Peak memory | 201944 kb |
| Host | smart-f3d06036-4680-441f-965c-04ce1e671cc1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841825571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.841825571 |
| Directory | /workspace/5.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_bijection.883221744 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 22435066193 ps |
| CPU time | 1460.34 seconds |
| Started | Feb 21 12:56:41 PM PST 24 |
| Finished | Feb 21 01:21:02 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-05534bbf-392f-4598-8567-dc3fd6483982 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883221744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.883221744 |
| Directory | /workspace/5.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_executable.745588204 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5232891872 ps |
| CPU time | 112.31 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 12:58:39 PM PST 24 |
| Peak memory | 344712 kb |
| Host | smart-bf10a230-173a-4ab6-b674-875bdfa4f06d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745588204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable .745588204 |
| Directory | /workspace/5.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.1668949784 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1843486098 ps |
| CPU time | 57.54 seconds |
| Started | Feb 21 12:56:57 PM PST 24 |
| Finished | Feb 21 12:57:55 PM PST 24 |
| Peak memory | 290044 kb |
| Host | smart-800e6d85-e5a3-44d4-9e0c-61a544501282 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668949784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.1668949784 |
| Directory | /workspace/5.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.442405729 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1585747034 ps |
| CPU time | 125.49 seconds |
| Started | Feb 21 12:56:52 PM PST 24 |
| Finished | Feb 21 12:58:58 PM PST 24 |
| Peak memory | 211336 kb |
| Host | smart-29962890-16c7-4221-8be9-95a2241d830e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442405729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. sram_ctrl_mem_partial_access.442405729 |
| Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.1399412504 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 18294282853 ps |
| CPU time | 146.14 seconds |
| Started | Feb 21 12:56:53 PM PST 24 |
| Finished | Feb 21 12:59:20 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-6a8aaee8-59f8-4ad8-ac56-ef69a5bf98a6 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399412504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.1399412504 |
| Directory | /workspace/5.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.2183849635 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 16097442396 ps |
| CPU time | 1193.18 seconds |
| Started | Feb 21 12:56:56 PM PST 24 |
| Finished | Feb 21 01:16:51 PM PST 24 |
| Peak memory | 378244 kb |
| Host | smart-47c27a22-9424-453c-bea6-e6047bae5150 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183849635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.2183849635 |
| Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.3601005957 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 406493993 ps |
| CPU time | 16.96 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 12:57:03 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-f8d0c10d-2f07-4a0a-83e8-2ebf2f2d564b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601005957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.3601005957 |
| Directory | /workspace/5.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1118514566 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 57082684951 ps |
| CPU time | 367.51 seconds |
| Started | Feb 21 12:56:48 PM PST 24 |
| Finished | Feb 21 01:02:56 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-b6d3b288-acea-4c8b-bc32-2047be4f8c38 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118514566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1118514566 |
| Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.2014073749 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1689968461 ps |
| CPU time | 13.41 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 12:57:10 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-d70ad387-dd47-461d-9d1f-e11235f93706 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014073749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2014073749 |
| Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_regwen.3924676419 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1669113828 ps |
| CPU time | 84.98 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 12:58:11 PM PST 24 |
| Peak memory | 302784 kb |
| Host | smart-75bd2bd1-4409-46a9-b040-cf11097133d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924676419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3924676419 |
| Directory | /workspace/5.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_smoke.977261453 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 7690718729 ps |
| CPU time | 142.58 seconds |
| Started | Feb 21 12:56:43 PM PST 24 |
| Finished | Feb 21 12:59:06 PM PST 24 |
| Peak memory | 365076 kb |
| Host | smart-6fbbf6c4-a157-4e7b-a488-f0f5a84758af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977261453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.977261453 |
| Directory | /workspace/5.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.3156469152 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 611281721933 ps |
| CPU time | 4996.72 seconds |
| Started | Feb 21 12:56:51 PM PST 24 |
| Finished | Feb 21 02:20:08 PM PST 24 |
| Peak memory | 381328 kb |
| Host | smart-122e7dc7-bb88-4bc9-9ee6-b334c2f3afdc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156469152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3156469152 |
| Directory | /workspace/5.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1284471857 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 19625061986 ps |
| CPU time | 320.22 seconds |
| Started | Feb 21 12:56:42 PM PST 24 |
| Finished | Feb 21 01:02:03 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-1f6e75e7-c7b5-408c-b17c-1031646f4739 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284471857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.1284471857 |
| Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4259473737 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1314180468 ps |
| CPU time | 93.77 seconds |
| Started | Feb 21 12:56:46 PM PST 24 |
| Finished | Feb 21 12:58:21 PM PST 24 |
| Peak memory | 335252 kb |
| Host | smart-eb5c13d9-4720-48f0-8658-3bc62ed03437 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259473737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.4259473737 |
| Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.155766466 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 12316663728 ps |
| CPU time | 441.13 seconds |
| Started | Feb 21 12:56:51 PM PST 24 |
| Finished | Feb 21 01:04:13 PM PST 24 |
| Peak memory | 353708 kb |
| Host | smart-6e2caf76-1932-462d-b650-5be2f77b22ee |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155766466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_access_during_key_req.155766466 |
| Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.141867225 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 24537539 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 12:56:50 PM PST 24 |
| Finished | Feb 21 12:56:51 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-ebe3dec4-e8da-4a2c-98c9-0aef3c1e3913 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141867225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.141867225 |
| Directory | /workspace/6.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_bijection.515544927 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 249051828978 ps |
| CPU time | 1053.11 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 01:14:39 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-c1e10854-7750-4bb1-9ccf-af7df4321af8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515544927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.515544927 |
| Directory | /workspace/6.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_executable.940207736 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 18081936640 ps |
| CPU time | 281.8 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 01:01:46 PM PST 24 |
| Peak memory | 372100 kb |
| Host | smart-1419d439-0de5-4cad-98f3-7846849d2b6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940207736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable .940207736 |
| Directory | /workspace/6.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.1928422803 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5550257934 ps |
| CPU time | 29.66 seconds |
| Started | Feb 21 12:56:56 PM PST 24 |
| Finished | Feb 21 12:57:27 PM PST 24 |
| Peak memory | 210640 kb |
| Host | smart-53ba3acd-e59a-4643-bf69-63319e7975d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928422803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.1928422803 |
| Directory | /workspace/6.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3512492730 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9587402964 ps |
| CPU time | 140.8 seconds |
| Started | Feb 21 12:57:03 PM PST 24 |
| Finished | Feb 21 12:59:24 PM PST 24 |
| Peak memory | 214724 kb |
| Host | smart-60f4c61c-6f62-44f6-b036-0d58b63b04d5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512492730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.3512492730 |
| Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.3967304460 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 14082835168 ps |
| CPU time | 266.71 seconds |
| Started | Feb 21 12:56:52 PM PST 24 |
| Finished | Feb 21 01:01:20 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-324a4d61-195c-4f67-aee9-b59220e5d676 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967304460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.3967304460 |
| Directory | /workspace/6.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.1770034154 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 5342238676 ps |
| CPU time | 41.02 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:57:46 PM PST 24 |
| Peak memory | 210676 kb |
| Host | smart-f5b7c14b-81d1-4011-a41f-e413d09f4b23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770034154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.1770034154 |
| Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.4155920517 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5638587587 ps |
| CPU time | 37.26 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 12:57:33 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-f5b9768b-3360-4b6a-8304-d9623d446578 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155920517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.4155920517 |
| Directory | /workspace/6.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2653010881 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 54781357390 ps |
| CPU time | 292.37 seconds |
| Started | Feb 21 12:57:00 PM PST 24 |
| Finished | Feb 21 01:01:53 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-19adc935-4ee9-44b4-99dc-34064fc15e4e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653010881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.2653010881 |
| Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.3371600830 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 361969389 ps |
| CPU time | 13.63 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 12:57:10 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-527e886c-5cef-4301-ac75-7d8316adb1be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371600830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3371600830 |
| Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2228657292 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 31007355325 ps |
| CPU time | 327.03 seconds |
| Started | Feb 21 12:56:53 PM PST 24 |
| Finished | Feb 21 01:02:21 PM PST 24 |
| Peak memory | 334244 kb |
| Host | smart-c42c726c-d2d4-4f94-87db-44f36c987212 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228657292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2228657292 |
| Directory | /workspace/6.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_smoke.1780067621 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2847275291 ps |
| CPU time | 28.42 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 12:57:27 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-e6c91d2f-bbf4-457c-b68d-87c67686a5de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780067621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1780067621 |
| Directory | /workspace/6.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.2787528152 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 496686054448 ps |
| CPU time | 5229.43 seconds |
| Started | Feb 21 12:57:03 PM PST 24 |
| Finished | Feb 21 02:24:13 PM PST 24 |
| Peak memory | 387532 kb |
| Host | smart-0ad7b0b9-4435-4539-9e42-fc83128f56aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787528152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.2787528152 |
| Directory | /workspace/6.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2128357990 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 19380727928 ps |
| CPU time | 401.17 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 01:03:40 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-85e902e7-1399-4bfb-81ba-b14bae1be4f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128357990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.2128357990 |
| Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2320055059 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 10294514111 ps |
| CPU time | 49.87 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 12:57:46 PM PST 24 |
| Peak memory | 284204 kb |
| Host | smart-36fbd51f-b45a-4abf-ae2b-4baa9d950472 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320055059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2320055059 |
| Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.600430351 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 5960197846 ps |
| CPU time | 126.09 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 12:59:03 PM PST 24 |
| Peak memory | 328552 kb |
| Host | smart-e3db61d8-3815-47e6-b117-cd5044b10911 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600430351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_access_during_key_req.600430351 |
| Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.54453099 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 37518217 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 12:56:59 PM PST 24 |
| Peak memory | 201928 kb |
| Host | smart-09e2f022-142b-4e46-8440-ca779cc84da8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54453099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_alert_test.54453099 |
| Directory | /workspace/7.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_bijection.3312240887 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 64919141833 ps |
| CPU time | 2312.98 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 01:35:32 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-7d956597-8dea-43c7-b804-b3736d1ae811 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312240887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 3312240887 |
| Directory | /workspace/7.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_executable.674300440 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 66410675232 ps |
| CPU time | 654.15 seconds |
| Started | Feb 21 12:57:01 PM PST 24 |
| Finished | Feb 21 01:07:55 PM PST 24 |
| Peak memory | 370620 kb |
| Host | smart-04d2f405-6d3d-4bd9-827c-18fab9658190 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674300440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable .674300440 |
| Directory | /workspace/7.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.1168332736 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 14231277186 ps |
| CPU time | 180.02 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 12:59:59 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-12c9b850-108a-4dbb-8f80-25e6034e4db8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168332736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1168332736 |
| Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.4251363913 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 748092250 ps |
| CPU time | 47.52 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:57:52 PM PST 24 |
| Peak memory | 284192 kb |
| Host | smart-bad1a05e-6633-4ab2-a14b-9be70fca447f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251363913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.4251363913 |
| Directory | /workspace/7.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2017856938 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 9974536863 ps |
| CPU time | 148.82 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 12:59:35 PM PST 24 |
| Peak memory | 211472 kb |
| Host | smart-d64a0e4c-2c8d-46b0-aa0c-9154fa18b07b |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017856938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.2017856938 |
| Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.2472650949 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 28672128934 ps |
| CPU time | 141.26 seconds |
| Started | Feb 21 12:56:59 PM PST 24 |
| Finished | Feb 21 12:59:21 PM PST 24 |
| Peak memory | 202352 kb |
| Host | smart-8b6eff8a-07a5-4ce6-8fda-cdea97a07d41 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472650949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2472650949 |
| Directory | /workspace/7.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.2277243725 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 13734012155 ps |
| CPU time | 870.64 seconds |
| Started | Feb 21 12:56:52 PM PST 24 |
| Finished | Feb 21 01:11:24 PM PST 24 |
| Peak memory | 376276 kb |
| Host | smart-cf76b483-06a4-4f9a-9a7f-d34a81de3db3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277243725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.2277243725 |
| Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.1287304226 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 379311588 ps |
| CPU time | 7.32 seconds |
| Started | Feb 21 12:56:56 PM PST 24 |
| Finished | Feb 21 12:57:05 PM PST 24 |
| Peak memory | 202292 kb |
| Host | smart-c34d4bc4-33f3-4f2d-bdeb-f1ee347dc8a6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287304226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.1287304226 |
| Directory | /workspace/7.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.556385693 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 102347017840 ps |
| CPU time | 556.62 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 01:06:15 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-00b14d40-4e65-42db-a6c2-97b210b924de |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556385693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.sram_ctrl_partial_access_b2b.556385693 |
| Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.303708934 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 704375524 ps |
| CPU time | 13.81 seconds |
| Started | Feb 21 12:56:59 PM PST 24 |
| Finished | Feb 21 12:57:13 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-b7b446f5-1a8e-4040-bba3-566536ef208f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303708934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.303708934 |
| Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_regwen.540573318 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 45907050858 ps |
| CPU time | 1306.97 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 01:18:43 PM PST 24 |
| Peak memory | 379376 kb |
| Host | smart-1b5ff58d-6423-4b29-9540-debc69b03b8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540573318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.540573318 |
| Directory | /workspace/7.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_smoke.4050478932 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 718039428 ps |
| CPU time | 12.12 seconds |
| Started | Feb 21 12:56:58 PM PST 24 |
| Finished | Feb 21 12:57:10 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-4941d206-282e-4e11-8792-9bb622f0a1c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050478932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.4050478932 |
| Directory | /workspace/7.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.517628123 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 336753338941 ps |
| CPU time | 3136.31 seconds |
| Started | Feb 21 12:57:00 PM PST 24 |
| Finished | Feb 21 01:49:18 PM PST 24 |
| Peak memory | 373180 kb |
| Host | smart-0dbb6230-ae48-4da9-a755-1ad07c81d400 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517628123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_stress_all.517628123 |
| Directory | /workspace/7.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1998649746 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 15434961864 ps |
| CPU time | 338.59 seconds |
| Started | Feb 21 12:56:55 PM PST 24 |
| Finished | Feb 21 01:02:35 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-704974e5-8847-485a-a43c-a0918e3e8697 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998649746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.1998649746 |
| Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1053724373 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3106874660 ps |
| CPU time | 78.76 seconds |
| Started | Feb 21 12:56:50 PM PST 24 |
| Finished | Feb 21 12:58:09 PM PST 24 |
| Peak memory | 310620 kb |
| Host | smart-f425f186-08b8-4163-bd69-3bfa87e41729 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053724373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1053724373 |
| Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3720121829 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1843602688 ps |
| CPU time | 406.43 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 01:03:54 PM PST 24 |
| Peak memory | 375480 kb |
| Host | smart-9fdcb519-0f27-4853-9072-bb018c2919d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720121829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.3720121829 |
| Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.1724239400 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 27890261 ps |
| CPU time | 0.6 seconds |
| Started | Feb 21 12:56:59 PM PST 24 |
| Finished | Feb 21 12:57:01 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-26d02c0d-2352-49ca-9fa8-b6ecc4f4177d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724239400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.1724239400 |
| Directory | /workspace/8.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_bijection.1939842577 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 88382349162 ps |
| CPU time | 1933.14 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 01:29:19 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-e9d83cbf-66f3-44ff-a458-fcd4417aaae8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939842577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 1939842577 |
| Directory | /workspace/8.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_executable.2801024994 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5962950083 ps |
| CPU time | 202.86 seconds |
| Started | Feb 21 12:57:06 PM PST 24 |
| Finished | Feb 21 01:00:29 PM PST 24 |
| Peak memory | 315064 kb |
| Host | smart-b1736be2-078b-4889-9710-972bd20f2c4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801024994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.2801024994 |
| Directory | /workspace/8.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.811920991 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 10841057669 ps |
| CPU time | 64.97 seconds |
| Started | Feb 21 12:57:06 PM PST 24 |
| Finished | Feb 21 12:58:12 PM PST 24 |
| Peak memory | 210844 kb |
| Host | smart-019e7aac-0059-404d-8323-82e61aad4fd9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811920991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca lation.811920991 |
| Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.170421907 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1540060532 ps |
| CPU time | 99.43 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 12:58:46 PM PST 24 |
| Peak memory | 323972 kb |
| Host | smart-694e0c80-c2a6-4916-9e10-52225933bb99 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170421907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.sram_ctrl_max_throughput.170421907 |
| Directory | /workspace/8.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2204584180 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 11082203477 ps |
| CPU time | 76.76 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 12:58:19 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-2aa0e175-3df6-48db-a0fd-f9720fa777fb |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204584180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.2204584180 |
| Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.3018058258 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 7112677516 ps |
| CPU time | 144.48 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:59:29 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-686bf436-55a1-458f-8d81-01ee7311d30e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018058258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.3018058258 |
| Directory | /workspace/8.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.2056016872 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 7391528875 ps |
| CPU time | 383.23 seconds |
| Started | Feb 21 12:56:56 PM PST 24 |
| Finished | Feb 21 01:03:21 PM PST 24 |
| Peak memory | 344556 kb |
| Host | smart-1da39492-f0a6-407b-96ad-11dd7ae68657 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056016872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2056016872 |
| Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.746738601 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 925839180 ps |
| CPU time | 97.26 seconds |
| Started | Feb 21 12:57:01 PM PST 24 |
| Finished | Feb 21 12:58:39 PM PST 24 |
| Peak memory | 354568 kb |
| Host | smart-a1571fdb-d7c0-407a-af6c-e4eb49a27ce9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746738601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.746738601 |
| Directory | /workspace/8.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.727419125 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 12122070823 ps |
| CPU time | 309.27 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 01:02:17 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-4cfcc4bb-b4a0-464c-928c-5082f3380930 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727419125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.sram_ctrl_partial_access_b2b.727419125 |
| Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3054699550 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1408724221 ps |
| CPU time | 5.51 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 12:57:13 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-e3457693-4760-4d29-a737-abbcb6ed3274 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054699550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3054699550 |
| Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_regwen.2358421693 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2084322443 ps |
| CPU time | 1170.24 seconds |
| Started | Feb 21 12:57:06 PM PST 24 |
| Finished | Feb 21 01:16:36 PM PST 24 |
| Peak memory | 378472 kb |
| Host | smart-66a0f985-603a-4f83-aa1e-5536a4c3e091 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358421693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2358421693 |
| Directory | /workspace/8.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_smoke.3826772057 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1417856019 ps |
| CPU time | 12.89 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 12:57:15 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-dbf85541-75dd-4d8c-ac93-4ed34285b492 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826772057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3826772057 |
| Directory | /workspace/8.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.1425557340 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 331621798015 ps |
| CPU time | 6694.94 seconds |
| Started | Feb 21 12:57:01 PM PST 24 |
| Finished | Feb 21 02:48:37 PM PST 24 |
| Peak memory | 377192 kb |
| Host | smart-f5bace32-a87b-4b69-9f5a-68228bae44ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425557340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.1425557340 |
| Directory | /workspace/8.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2842830910 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 20589459913 ps |
| CPU time | 359.84 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 01:03:02 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-347ef50f-1b06-4f37-a0d7-83d0e45689d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842830910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.2842830910 |
| Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2532554739 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 792750716 ps |
| CPU time | 160.98 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 12:59:47 PM PST 24 |
| Peak memory | 355032 kb |
| Host | smart-b0a45c5a-d9a7-482f-aeef-88a47360e5f7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532554739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2532554739 |
| Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3790901881 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5990872744 ps |
| CPU time | 1136.65 seconds |
| Started | Feb 21 12:57:02 PM PST 24 |
| Finished | Feb 21 01:15:59 PM PST 24 |
| Peak memory | 373168 kb |
| Host | smart-9f03cbe9-526c-4294-9e60-77a95f9eadf3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790901881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3790901881 |
| Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.2355877049 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 14948761 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 12:57:12 PM PST 24 |
| Peak memory | 201896 kb |
| Host | smart-2f7fa276-4814-4726-89fd-7715468a17ec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355877049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2355877049 |
| Directory | /workspace/9.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_bijection.2862369820 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 138902957367 ps |
| CPU time | 704.88 seconds |
| Started | Feb 21 12:56:47 PM PST 24 |
| Finished | Feb 21 01:08:33 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-174ea06e-2f46-411f-8ed1-cbd64c92571f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862369820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 2862369820 |
| Directory | /workspace/9.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_executable.352727266 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 24999159860 ps |
| CPU time | 1582.75 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 01:23:30 PM PST 24 |
| Peak memory | 374476 kb |
| Host | smart-10475661-e1df-41ea-bf85-3c99536817d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352727266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable .352727266 |
| Directory | /workspace/9.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.1609291133 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 35294098862 ps |
| CPU time | 192.61 seconds |
| Started | Feb 21 12:57:01 PM PST 24 |
| Finished | Feb 21 01:00:15 PM PST 24 |
| Peak memory | 210584 kb |
| Host | smart-9d27f037-901f-4c9a-899e-d841e4dca4d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609291133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.1609291133 |
| Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.1450450222 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3157548144 ps |
| CPU time | 149.38 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 12:59:37 PM PST 24 |
| Peak memory | 357020 kb |
| Host | smart-60368a43-a682-4a2f-9b19-d90f2504fb94 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450450222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.1450450222 |
| Directory | /workspace/9.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2901781330 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 951160665 ps |
| CPU time | 69.55 seconds |
| Started | Feb 21 12:56:57 PM PST 24 |
| Finished | Feb 21 12:58:07 PM PST 24 |
| Peak memory | 211484 kb |
| Host | smart-bc8ba27f-f002-4536-ba66-48fc8549846b |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901781330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2901781330 |
| Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.1334473714 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 16420804555 ps |
| CPU time | 254.58 seconds |
| Started | Feb 21 12:57:06 PM PST 24 |
| Finished | Feb 21 01:01:21 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-147c3293-1f72-45a3-a72f-4d7418643a58 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334473714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.1334473714 |
| Directory | /workspace/9.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.2517217418 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 9316399802 ps |
| CPU time | 489.02 seconds |
| Started | Feb 21 12:57:05 PM PST 24 |
| Finished | Feb 21 01:05:14 PM PST 24 |
| Peak memory | 338420 kb |
| Host | smart-1e0e661f-7d57-471d-9d1d-ded2c25d1c94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517217418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.2517217418 |
| Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.2379795622 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2867181958 ps |
| CPU time | 48.79 seconds |
| Started | Feb 21 12:56:48 PM PST 24 |
| Finished | Feb 21 12:57:37 PM PST 24 |
| Peak memory | 272232 kb |
| Host | smart-be9bb601-4de3-4768-8764-b5968dbe7c3d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379795622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.2379795622 |
| Directory | /workspace/9.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2739580607 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 92349928536 ps |
| CPU time | 600.88 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 01:07:06 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-8094f072-49ba-442f-bca7-2c2dbd9b03cd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739580607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.2739580607 |
| Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.2991390515 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 357753231 ps |
| CPU time | 6.51 seconds |
| Started | Feb 21 12:57:00 PM PST 24 |
| Finished | Feb 21 12:57:07 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-a7d78b0c-d46b-425e-999d-0976a9174026 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991390515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2991390515 |
| Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_regwen.3342023703 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2445580040 ps |
| CPU time | 74.83 seconds |
| Started | Feb 21 12:57:11 PM PST 24 |
| Finished | Feb 21 12:58:26 PM PST 24 |
| Peak memory | 297248 kb |
| Host | smart-ee10dcdd-8a1c-4e7e-96ec-67692e04c7b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342023703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3342023703 |
| Directory | /workspace/9.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_smoke.3484342933 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1682873126 ps |
| CPU time | 80.79 seconds |
| Started | Feb 21 12:57:04 PM PST 24 |
| Finished | Feb 21 12:58:25 PM PST 24 |
| Peak memory | 332240 kb |
| Host | smart-a72dedc1-65c8-4a6e-8ece-42b339cb5011 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484342933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3484342933 |
| Directory | /workspace/9.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2860872823 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 5250590034 ps |
| CPU time | 175.4 seconds |
| Started | Feb 21 12:56:49 PM PST 24 |
| Finished | Feb 21 12:59:44 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-64436d54-cc1f-42a3-b0c9-542a116bc77b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860872823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.2860872823 |
| Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.619945240 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1618259753 ps |
| CPU time | 161.27 seconds |
| Started | Feb 21 12:57:07 PM PST 24 |
| Finished | Feb 21 12:59:49 PM PST 24 |
| Peak memory | 361204 kb |
| Host | smart-d4383954-641a-414c-aa5f-57baf4080763 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619945240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_throughput_w_partial_write.619945240 |
| Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |