Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	290250506	1			T1	62002		T2	563456		T3	393212
instr_valid_dis	255907436	1			T1	62002		T2	563456		T3	393212
instr_en	28851689	1			T6	14046		T18	92948		T14	210508

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	6255868	1			T6	38916		T16	57774		T14	99160
sram_ifetch_valid_disable	268809104	1			T1	62002		T2	563456		T3	393212
sram_ifetch_enable	15185534	1			T6	201632		T16	24538		T18	5238

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	290250506	1			T1	62002		T2	563456		T3	393212
hw_debug_en_valid_off	263942474	1			T1	62002		T2	563456		T3	393212
hw_debug_en_on	13671608	1			T6	125180		T16	267336		T18	73206

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	268809104	1			T1	62002		T2	563456		T3	393212
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	248613862	1			T1	62002		T2	563456		T3	393212
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	16909831	1			T18	87710		T14	132396		T8	14550
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2779422	1			T14	68344		T8	65490		T104	16844
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1081128	1			T14	3372		T8	65490		T104	58
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1349734	1			T14	64972		T104	16786		T102	16578
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2417064	1			T6	38916		T16	57774		T8	27558
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1196320	1			T16	57774		T8	27558		T105	89774
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1010254	1			T22	3226		T103	21916		T107	116934
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6570464	1			T16	209562		T18	71804		T14	59574
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2227674	1			T16	209562		T14	19806		T8	209906
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3656198	1			T18	71804		T14	14052		T8	14550

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9148818	1			T6	14046		T18	5238		T14	13140
lc_exec_en	4684080	1			T6	86264		T18	1402		T14	20000
valid_exec_dis	257647050	1			T1	62002		T2	563456		T3	393212
invalid_exec_dis	21441402	1			T6	240548		T16	82312		T18	5238