Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 100.00 97.62 100.00 100.00 99.15 99.70 98.33


Total tests in report: 906
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.15 83.15 96.92 96.92 76.47 76.47 89.42 89.42 71.43 71.43 88.17 88.17 95.10 95.10 64.56 64.56 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.760434901
93.20 10.05 99.16 2.24 89.36 12.89 95.53 6.11 100.00 28.57 97.18 9.01 95.10 0.00 76.07 11.50 /workspace/coverage/default/0.sram_ctrl_stress_all.3450763033
95.73 2.53 99.44 0.28 92.16 2.80 96.02 0.50 100.00 0.00 98.03 0.85 96.14 1.04 88.31 12.24 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4276912567
96.67 0.94 99.44 0.00 93.70 1.54 96.16 0.14 100.00 0.00 98.31 0.28 96.88 0.74 92.21 3.90 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1565138130
97.44 0.77 99.63 0.19 95.80 2.10 96.88 0.71 100.00 0.00 99.15 0.85 97.47 0.59 93.14 0.93 /workspace/coverage/default/0.sram_ctrl_sec_cm.2901578802
98.01 0.57 99.63 0.00 96.50 0.70 99.04 2.17 100.00 0.00 99.15 0.00 97.47 0.00 94.25 1.11 /workspace/coverage/default/12.sram_ctrl_executable.1652247370
98.30 0.29 99.63 0.00 96.50 0.00 99.04 0.00 100.00 0.00 99.15 0.00 97.47 0.00 96.29 2.04 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3975442536
98.52 0.22 99.63 0.00 96.78 0.28 99.04 0.00 100.00 0.00 99.15 0.00 98.37 0.89 96.66 0.37 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3966755534
98.71 0.19 99.63 0.00 96.78 0.00 99.04 0.00 100.00 0.00 99.15 0.00 99.70 1.34 96.66 0.00 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1875888205
98.84 0.13 99.72 0.09 96.78 0.00 99.86 0.82 100.00 0.00 99.15 0.00 99.70 0.00 96.66 0.00 /workspace/coverage/default/4.sram_ctrl_ram_cfg.100855432
98.95 0.11 100.00 0.28 97.20 0.42 99.93 0.07 100.00 0.00 99.15 0.00 99.70 0.00 96.66 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.3746036249
99.06 0.11 100.00 0.00 97.20 0.00 99.93 0.00 100.00 0.00 99.15 0.00 99.70 0.00 97.40 0.74 /workspace/coverage/default/9.sram_ctrl_stress_all.3984483640
99.13 0.08 100.00 0.00 97.20 0.00 99.93 0.00 100.00 0.00 99.15 0.00 99.70 0.00 97.96 0.56 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2192645060
99.17 0.03 100.00 0.00 97.34 0.14 100.00 0.07 100.00 0.00 99.15 0.00 99.70 0.00 97.96 0.00 /workspace/coverage/default/44.sram_ctrl_stress_all.3719760953
99.19 0.03 100.00 0.00 97.34 0.00 100.00 0.00 100.00 0.00 99.15 0.00 99.70 0.00 98.14 0.19 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4261712885
99.22 0.03 100.00 0.00 97.34 0.00 100.00 0.00 100.00 0.00 99.15 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.593940567


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3294290605
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1103680096
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1591716854
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4254460451
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.157928134
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4237892719
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1095347556
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.556531776
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1207430441
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2761594025
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2262490975
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3115351142
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2147671630
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3509911814
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2196811745
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3104941638
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4073227538
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3128389190
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.695039047
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1378898080
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2108908074
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3417326217
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1900384322
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3981802387
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1611256352
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2194918871
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.677196644
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2914908480
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1060285043
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1007192017
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1610576556
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1408269722
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1136912133
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1142313518
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1995216682
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1811767809
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.124719228
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3461114838
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3204943884
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2303948936
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4118568933
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4257813544
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3363259873
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3457754630
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2938236297
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4261230645
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.283333062
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3366731832
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1642907483
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.410074964
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3290231019
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1033486264
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3370308617
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1788814336
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.429984644
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1041651343
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1283234807
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.849417033
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.60004240
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3262069369
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1199885329
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2401273025
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2917241501
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.916692549
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4079389141
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4149451113
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1688444039
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4139482071
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.313799552
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3457566943
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3057538176
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.882573627
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2030328381
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3195945107
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1548830355
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2306608780
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3446234393
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.273263955
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2473767025
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1874620372
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1259807342
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1506860505
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2568775244
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2525122875
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.268631192
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.930198097
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3201852571
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1947873596
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3375762382
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.697502705
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3033528195
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2090550235
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4210073719
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1371608676
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.551796810
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.729272144
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2717967444
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4053821452
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3089526780
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3037898198
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.199604125
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3745362283
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2190364763
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1166125098
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.57804128
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.431918958
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4239773565
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2297966708
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2256139663
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1044896258
/workspace/coverage/default/0.sram_ctrl_bijection.1632832126
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2058396948
/workspace/coverage/default/0.sram_ctrl_max_throughput.818962080
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.640976650
/workspace/coverage/default/0.sram_ctrl_mem_walk.2892685054
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1538001400
/workspace/coverage/default/0.sram_ctrl_partial_access.594404848
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.268560834
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3206325377
/workspace/coverage/default/0.sram_ctrl_regwen.1794359796
/workspace/coverage/default/0.sram_ctrl_smoke.2386766730
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4094753438
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3433239635
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2360897844
/workspace/coverage/default/1.sram_ctrl_alert_test.3677671147
/workspace/coverage/default/1.sram_ctrl_bijection.3848639643
/workspace/coverage/default/1.sram_ctrl_executable.1076511735
/workspace/coverage/default/1.sram_ctrl_lc_escalation.946159705
/workspace/coverage/default/1.sram_ctrl_max_throughput.1752534140
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2680416978
/workspace/coverage/default/1.sram_ctrl_mem_walk.1731527024
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2560031256
/workspace/coverage/default/1.sram_ctrl_partial_access.1602427117
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4043807299
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1250018595
/workspace/coverage/default/1.sram_ctrl_regwen.3471403274
/workspace/coverage/default/1.sram_ctrl_sec_cm.3177360687
/workspace/coverage/default/1.sram_ctrl_smoke.2217141340
/workspace/coverage/default/1.sram_ctrl_stress_all.1387412338
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2908307274
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.589945983
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2908045922
/workspace/coverage/default/10.sram_ctrl_alert_test.2229393443
/workspace/coverage/default/10.sram_ctrl_bijection.1025937298
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3369426164
/workspace/coverage/default/10.sram_ctrl_max_throughput.3576228283
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1355965387
/workspace/coverage/default/10.sram_ctrl_mem_walk.3509090083
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2666689366
/workspace/coverage/default/10.sram_ctrl_partial_access.2504554330
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2609772221
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2681241233
/workspace/coverage/default/10.sram_ctrl_regwen.1208020185
/workspace/coverage/default/10.sram_ctrl_smoke.2890653237
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3229060642
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2916986745
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2914638503
/workspace/coverage/default/11.sram_ctrl_alert_test.654988931
/workspace/coverage/default/11.sram_ctrl_bijection.3013905795
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3773987366
/workspace/coverage/default/11.sram_ctrl_max_throughput.4142585605
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4211740597
/workspace/coverage/default/11.sram_ctrl_mem_walk.510671249
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3762894011
/workspace/coverage/default/11.sram_ctrl_partial_access.900431121
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1254488948
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2314435427
/workspace/coverage/default/11.sram_ctrl_regwen.4168124824
/workspace/coverage/default/11.sram_ctrl_smoke.994251174
/workspace/coverage/default/11.sram_ctrl_stress_all.1801324045
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3934353191
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1103810921
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.376192660
/workspace/coverage/default/12.sram_ctrl_alert_test.2602493932
/workspace/coverage/default/12.sram_ctrl_bijection.458623624
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1279249971
/workspace/coverage/default/12.sram_ctrl_max_throughput.3851539710
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1407779287
/workspace/coverage/default/12.sram_ctrl_mem_walk.2466909694
/workspace/coverage/default/12.sram_ctrl_multiple_keys.994120618
/workspace/coverage/default/12.sram_ctrl_partial_access.366525672
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3428510942
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1779842170
/workspace/coverage/default/12.sram_ctrl_regwen.3169799198
/workspace/coverage/default/12.sram_ctrl_smoke.71117341
/workspace/coverage/default/12.sram_ctrl_stress_all.213679558
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.805049988
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1650141517
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1201315617
/workspace/coverage/default/13.sram_ctrl_alert_test.3019996628
/workspace/coverage/default/13.sram_ctrl_bijection.3946755246
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1477976788
/workspace/coverage/default/13.sram_ctrl_max_throughput.11866469
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1587811605
/workspace/coverage/default/13.sram_ctrl_mem_walk.3314336658
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1949205475
/workspace/coverage/default/13.sram_ctrl_partial_access.3833828103
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2359676370
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3012712803
/workspace/coverage/default/13.sram_ctrl_regwen.3958793854
/workspace/coverage/default/13.sram_ctrl_smoke.1349490475
/workspace/coverage/default/13.sram_ctrl_stress_all.2812127741
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.315806119
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2708142138
/workspace/coverage/default/14.sram_ctrl_alert_test.2569960296
/workspace/coverage/default/14.sram_ctrl_bijection.1230313861
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3136986203
/workspace/coverage/default/14.sram_ctrl_max_throughput.3481278027
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.931697316
/workspace/coverage/default/14.sram_ctrl_mem_walk.3913420734
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1445828607
/workspace/coverage/default/14.sram_ctrl_partial_access.1635744925
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3596950433
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1956687775
/workspace/coverage/default/14.sram_ctrl_regwen.128261837
/workspace/coverage/default/14.sram_ctrl_smoke.1864202080
/workspace/coverage/default/14.sram_ctrl_stress_all.426954695
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.837531021
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3124160009
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3719320171
/workspace/coverage/default/15.sram_ctrl_alert_test.3153454093
/workspace/coverage/default/15.sram_ctrl_bijection.2618828462
/workspace/coverage/default/15.sram_ctrl_lc_escalation.867876513
/workspace/coverage/default/15.sram_ctrl_max_throughput.448651454
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/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1190946287
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/workspace/coverage/default/5.sram_ctrl_regwen.1025685670
/workspace/coverage/default/5.sram_ctrl_smoke.268279000
/workspace/coverage/default/5.sram_ctrl_stress_all.4235116010
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1752645418
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.769731533
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2408446437
/workspace/coverage/default/6.sram_ctrl_alert_test.964382260
/workspace/coverage/default/6.sram_ctrl_bijection.3359869060
/workspace/coverage/default/6.sram_ctrl_max_throughput.2454501773
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3902861967
/workspace/coverage/default/6.sram_ctrl_mem_walk.3267947718
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2097172619
/workspace/coverage/default/6.sram_ctrl_partial_access.259832317
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1323251243
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2918896074
/workspace/coverage/default/6.sram_ctrl_regwen.3430965429
/workspace/coverage/default/6.sram_ctrl_smoke.1565041258
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2803942648
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.236190681
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.678485451
/workspace/coverage/default/7.sram_ctrl_alert_test.4192695247
/workspace/coverage/default/7.sram_ctrl_bijection.3286986889
/workspace/coverage/default/7.sram_ctrl_executable.624981005
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3628666651
/workspace/coverage/default/7.sram_ctrl_max_throughput.3434528650
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2811674277
/workspace/coverage/default/7.sram_ctrl_mem_walk.4290516408
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3988783395
/workspace/coverage/default/7.sram_ctrl_partial_access.1884013371
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2067891288
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3812466414
/workspace/coverage/default/7.sram_ctrl_regwen.2684414513
/workspace/coverage/default/7.sram_ctrl_smoke.342653935
/workspace/coverage/default/7.sram_ctrl_stress_all.2546122546
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2039101343
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3483408446
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.26991092
/workspace/coverage/default/8.sram_ctrl_alert_test.982991626
/workspace/coverage/default/8.sram_ctrl_bijection.1893700334
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2301636639
/workspace/coverage/default/8.sram_ctrl_max_throughput.3800966677
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1154687016
/workspace/coverage/default/8.sram_ctrl_mem_walk.1847600226
/workspace/coverage/default/8.sram_ctrl_multiple_keys.330410733
/workspace/coverage/default/8.sram_ctrl_partial_access.654538890
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3160692465
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2619336319
/workspace/coverage/default/8.sram_ctrl_regwen.3768264937
/workspace/coverage/default/8.sram_ctrl_smoke.747429405
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3806011080
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.292544537
/workspace/coverage/default/9.sram_ctrl_alert_test.389394030
/workspace/coverage/default/9.sram_ctrl_bijection.1003789110
/workspace/coverage/default/9.sram_ctrl_executable.638760664
/workspace/coverage/default/9.sram_ctrl_lc_escalation.4205384827
/workspace/coverage/default/9.sram_ctrl_max_throughput.4128360395
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2320405343
/workspace/coverage/default/9.sram_ctrl_mem_walk.1361694535
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1236482496
/workspace/coverage/default/9.sram_ctrl_partial_access.2425392446
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1305394955
/workspace/coverage/default/9.sram_ctrl_ram_cfg.393057134
/workspace/coverage/default/9.sram_ctrl_regwen.818215694
/workspace/coverage/default/9.sram_ctrl_smoke.1635587663
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1346364352
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1224165473




Total test records in report: 906
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1771606404 Feb 25 01:18:37 PM PST 24 Feb 25 01:19:59 PM PST 24 5232562422 ps
T2 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.760434901 Feb 25 01:19:02 PM PST 24 Feb 25 01:25:40 PM PST 24 5572172231 ps
T3 /workspace/coverage/default/47.sram_ctrl_mem_walk.2609211823 Feb 25 01:25:20 PM PST 24 Feb 25 01:30:38 PM PST 24 61722289656 ps
T4 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1752645418 Feb 25 01:18:50 PM PST 24 Feb 25 01:24:23 PM PST 24 9044510798 ps
T9 /workspace/coverage/default/38.sram_ctrl_mem_walk.2792796369 Feb 25 01:23:37 PM PST 24 Feb 25 01:25:42 PM PST 24 2059763649 ps
T5 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2898420064 Feb 25 01:21:05 PM PST 24 Feb 25 01:27:16 PM PST 24 45606962866 ps
T10 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2244716348 Feb 25 01:24:41 PM PST 24 Feb 25 01:26:26 PM PST 24 1514329860 ps
T11 /workspace/coverage/default/49.sram_ctrl_max_throughput.3433105653 Feb 25 01:26:04 PM PST 24 Feb 25 01:26:48 PM PST 24 1430584530 ps
T12 /workspace/coverage/default/16.sram_ctrl_partial_access.2387730052 Feb 25 01:19:40 PM PST 24 Feb 25 01:19:53 PM PST 24 925810133 ps
T13 /workspace/coverage/default/4.sram_ctrl_ram_cfg.100855432 Feb 25 01:18:47 PM PST 24 Feb 25 01:18:53 PM PST 24 588061252 ps
T15 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2177528447 Feb 25 01:24:12 PM PST 24 Feb 25 01:25:59 PM PST 24 796171945 ps
T6 /workspace/coverage/default/44.sram_ctrl_stress_all.3719760953 Feb 25 01:24:43 PM PST 24 Feb 25 01:48:00 PM PST 24 249516019891 ps
T16 /workspace/coverage/default/2.sram_ctrl_regwen.1471572922 Feb 25 01:18:41 PM PST 24 Feb 25 01:38:48 PM PST 24 3405314727 ps
T17 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2959796977 Feb 25 01:23:56 PM PST 24 Feb 25 01:27:57 PM PST 24 5778690015 ps
T93 /workspace/coverage/default/39.sram_ctrl_mem_walk.1728327941 Feb 25 01:23:50 PM PST 24 Feb 25 01:26:22 PM PST 24 8958294505 ps
T111 /workspace/coverage/default/1.sram_ctrl_max_throughput.1752534140 Feb 25 01:18:29 PM PST 24 Feb 25 01:19:04 PM PST 24 715019545 ps
T26 /workspace/coverage/default/11.sram_ctrl_alert_test.654988931 Feb 25 01:19:01 PM PST 24 Feb 25 01:19:02 PM PST 24 22462701 ps
T18 /workspace/coverage/default/6.sram_ctrl_regwen.3430965429 Feb 25 01:18:54 PM PST 24 Feb 25 01:22:28 PM PST 24 28761324385 ps
T67 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3185187193 Feb 25 01:20:16 PM PST 24 Feb 25 01:25:12 PM PST 24 3319242591 ps
T14 /workspace/coverage/default/12.sram_ctrl_executable.1652247370 Feb 25 01:19:19 PM PST 24 Feb 25 01:41:53 PM PST 24 87059276383 ps
T112 /workspace/coverage/default/33.sram_ctrl_max_throughput.2316785633 Feb 25 01:22:29 PM PST 24 Feb 25 01:23:33 PM PST 24 734715628 ps
T7 /workspace/coverage/default/43.sram_ctrl_lc_escalation.2778699990 Feb 25 01:24:33 PM PST 24 Feb 25 01:28:12 PM PST 24 66723996077 ps
T68 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1598431080 Feb 25 01:25:58 PM PST 24 Feb 25 01:27:18 PM PST 24 994990263 ps
T8 /workspace/coverage/default/0.sram_ctrl_stress_all.3450763033 Feb 25 01:18:24 PM PST 24 Feb 25 03:17:00 PM PST 24 340523784256 ps
T89 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2744038984 Feb 25 01:24:12 PM PST 24 Feb 25 01:31:14 PM PST 24 23322151397 ps
T113 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2177658434 Feb 25 01:22:13 PM PST 24 Feb 25 01:24:28 PM PST 24 810179305 ps
T34 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2102947485 Feb 25 01:19:47 PM PST 24 Feb 25 01:19:54 PM PST 24 455810914 ps
T114 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3867397608 Feb 25 01:23:50 PM PST 24 Feb 25 01:25:04 PM PST 24 801318128 ps
T35 /workspace/coverage/default/9.sram_ctrl_ram_cfg.393057134 Feb 25 01:19:04 PM PST 24 Feb 25 01:19:11 PM PST 24 680436460 ps
T115 /workspace/coverage/default/18.sram_ctrl_smoke.463622989 Feb 25 01:19:54 PM PST 24 Feb 25 01:20:59 PM PST 24 8850292215 ps
T90 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.250987997 Feb 25 01:24:45 PM PST 24 Feb 25 01:30:37 PM PST 24 18228007495 ps
T116 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2419794272 Feb 25 01:21:08 PM PST 24 Feb 25 01:22:43 PM PST 24 3354363110 ps
T91 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1440683514 Feb 25 01:24:55 PM PST 24 Feb 25 01:30:39 PM PST 24 7829715087 ps
T117 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2722076026 Feb 25 01:24:12 PM PST 24 Feb 25 01:24:19 PM PST 24 2789525876 ps
T104 /workspace/coverage/default/30.sram_ctrl_executable.92300768 Feb 25 01:22:03 PM PST 24 Feb 25 01:23:45 PM PST 24 6886076555 ps
T118 /workspace/coverage/default/36.sram_ctrl_ram_cfg.1909992144 Feb 25 01:23:12 PM PST 24 Feb 25 01:23:18 PM PST 24 360912407 ps
T102 /workspace/coverage/default/27.sram_ctrl_regwen.3851978569 Feb 25 01:21:35 PM PST 24 Feb 25 01:30:21 PM PST 24 7647025167 ps
T75 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1288816609 Feb 25 01:19:58 PM PST 24 Feb 25 01:21:27 PM PST 24 33302328336 ps
T119 /workspace/coverage/default/47.sram_ctrl_smoke.2307541748 Feb 25 01:25:02 PM PST 24 Feb 25 01:25:14 PM PST 24 734226825 ps
T22 /workspace/coverage/default/9.sram_ctrl_stress_all.3984483640 Feb 25 01:19:01 PM PST 24 Feb 25 02:35:52 PM PST 24 147070865814 ps
T120 /workspace/coverage/default/28.sram_ctrl_mem_walk.2897012089 Feb 25 01:21:41 PM PST 24 Feb 25 01:25:47 PM PST 24 8041113726 ps
T121 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.722352271 Feb 25 01:22:33 PM PST 24 Feb 25 01:23:54 PM PST 24 2963396456 ps
T92 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2908307274 Feb 25 01:18:30 PM PST 24 Feb 25 01:25:08 PM PST 24 52203512157 ps
T122 /workspace/coverage/default/11.sram_ctrl_ram_cfg.2314435427 Feb 25 01:19:22 PM PST 24 Feb 25 01:19:36 PM PST 24 599040698 ps
T123 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3483408446 Feb 25 01:18:49 PM PST 24 Feb 25 01:19:16 PM PST 24 682021562 ps
T124 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2377424140 Feb 25 01:22:55 PM PST 24 Feb 25 01:23:23 PM PST 24 1602344742 ps
T23 /workspace/coverage/default/3.sram_ctrl_sec_cm.3058509204 Feb 25 01:18:40 PM PST 24 Feb 25 01:18:43 PM PST 24 144589741 ps
T38 /workspace/coverage/default/46.sram_ctrl_smoke.1238592120 Feb 25 01:24:53 PM PST 24 Feb 25 01:25:03 PM PST 24 898416674 ps
T39 /workspace/coverage/default/9.sram_ctrl_mem_walk.1361694535 Feb 25 01:19:04 PM PST 24 Feb 25 01:23:09 PM PST 24 15759286773 ps
T40 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1799599202 Feb 25 01:22:56 PM PST 24 Feb 25 01:29:18 PM PST 24 132566603615 ps
T41 /workspace/coverage/default/42.sram_ctrl_bijection.1716502666 Feb 25 01:24:21 PM PST 24 Feb 25 02:01:44 PM PST 24 31802371446 ps
T42 /workspace/coverage/default/49.sram_ctrl_ram_cfg.3277141846 Feb 25 01:26:01 PM PST 24 Feb 25 01:26:15 PM PST 24 1888578846 ps
T43 /workspace/coverage/default/22.sram_ctrl_max_throughput.4025160460 Feb 25 01:20:38 PM PST 24 Feb 25 01:22:04 PM PST 24 2168255407 ps
T44 /workspace/coverage/default/24.sram_ctrl_partial_access.3989925922 Feb 25 01:20:51 PM PST 24 Feb 25 01:21:06 PM PST 24 479659390 ps
T27 /workspace/coverage/default/0.sram_ctrl_alert_test.3746036249 Feb 25 01:18:18 PM PST 24 Feb 25 01:18:18 PM PST 24 51205372 ps
T45 /workspace/coverage/default/12.sram_ctrl_bijection.458623624 Feb 25 01:19:04 PM PST 24 Feb 25 01:54:30 PM PST 24 31812798936 ps
T76 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.824256258 Feb 25 01:23:06 PM PST 24 Feb 25 01:25:36 PM PST 24 4553518301 ps
T125 /workspace/coverage/default/47.sram_ctrl_partial_access.3649409522 Feb 25 01:25:19 PM PST 24 Feb 25 01:25:31 PM PST 24 1898638937 ps
T126 /workspace/coverage/default/7.sram_ctrl_ram_cfg.3812466414 Feb 25 01:18:51 PM PST 24 Feb 25 01:18:58 PM PST 24 346657308 ps
T29 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2559549411 Feb 25 01:18:46 PM PST 24 Feb 25 01:20:57 PM PST 24 12639557052 ps
T127 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.753279544 Feb 25 01:20:52 PM PST 24 Feb 25 01:21:56 PM PST 24 3020714979 ps
T128 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1705128218 Feb 25 01:19:50 PM PST 24 Feb 25 01:23:43 PM PST 24 6379646107 ps
T129 /workspace/coverage/default/4.sram_ctrl_partial_access.1842301170 Feb 25 01:18:44 PM PST 24 Feb 25 01:21:50 PM PST 24 8655796120 ps
T105 /workspace/coverage/default/14.sram_ctrl_stress_all.426954695 Feb 25 01:20:00 PM PST 24 Feb 25 01:48:42 PM PST 24 59292147694 ps
T130 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1626340800 Feb 25 01:19:47 PM PST 24 Feb 25 01:24:34 PM PST 24 3745098480 ps
T108 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1404633099 Feb 25 01:24:47 PM PST 24 Feb 25 01:29:45 PM PST 24 130179045059 ps
T131 /workspace/coverage/default/43.sram_ctrl_regwen.3743603324 Feb 25 01:24:39 PM PST 24 Feb 25 01:44:28 PM PST 24 25219807780 ps
T77 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3799657098 Feb 25 01:19:49 PM PST 24 Feb 25 01:22:35 PM PST 24 5298631109 ps
T132 /workspace/coverage/default/27.sram_ctrl_mem_walk.1882567928 Feb 25 01:21:37 PM PST 24 Feb 25 01:24:07 PM PST 24 17649706911 ps
T133 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3913540410 Feb 25 01:20:32 PM PST 24 Feb 25 01:23:24 PM PST 24 4583976828 ps
T78 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1412035829 Feb 25 01:21:26 PM PST 24 Feb 25 01:22:38 PM PST 24 1872815771 ps
T103 /workspace/coverage/default/17.sram_ctrl_stress_all.970716072 Feb 25 01:19:54 PM PST 24 Feb 25 02:23:13 PM PST 24 106159979703 ps
T134 /workspace/coverage/default/44.sram_ctrl_partial_access.2530623834 Feb 25 01:24:47 PM PST 24 Feb 25 01:25:14 PM PST 24 1007770493 ps
T135 /workspace/coverage/default/17.sram_ctrl_partial_access.3855316626 Feb 25 01:19:52 PM PST 24 Feb 25 01:20:44 PM PST 24 969947436 ps
T79 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1110828348 Feb 25 01:18:40 PM PST 24 Feb 25 01:19:58 PM PST 24 9375301095 ps
T136 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2067891288 Feb 25 01:18:50 PM PST 24 Feb 25 01:24:33 PM PST 24 10447815151 ps
T137 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3433239635 Feb 25 01:18:20 PM PST 24 Feb 25 01:18:51 PM PST 24 3065655588 ps
T138 /workspace/coverage/default/7.sram_ctrl_smoke.342653935 Feb 25 01:18:48 PM PST 24 Feb 25 01:19:05 PM PST 24 742170446 ps
T139 /workspace/coverage/default/45.sram_ctrl_executable.3251735702 Feb 25 01:24:57 PM PST 24 Feb 25 01:26:35 PM PST 24 6379375759 ps
T140 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2916986745 Feb 25 01:19:01 PM PST 24 Feb 25 01:19:31 PM PST 24 4170856284 ps
T19 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3966755534 Feb 25 01:19:37 PM PST 24 Feb 25 01:34:51 PM PST 24 17663656055 ps
T28 /workspace/coverage/default/26.sram_ctrl_alert_test.125631274 Feb 25 01:21:28 PM PST 24 Feb 25 01:21:29 PM PST 24 45674611 ps
T141 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1551715294 Feb 25 01:23:57 PM PST 24 Feb 25 01:26:28 PM PST 24 853706716 ps
T142 /workspace/coverage/default/4.sram_ctrl_mem_walk.2501671538 Feb 25 01:18:40 PM PST 24 Feb 25 01:23:12 PM PST 24 14370711479 ps
T143 /workspace/coverage/default/16.sram_ctrl_mem_walk.1414053828 Feb 25 01:19:48 PM PST 24 Feb 25 01:22:09 PM PST 24 14099130993 ps
T144 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2881266699 Feb 25 01:18:44 PM PST 24 Feb 25 01:18:59 PM PST 24 1350535016 ps
T145 /workspace/coverage/default/30.sram_ctrl_bijection.3550816789 Feb 25 01:22:11 PM PST 24 Feb 25 01:54:30 PM PST 24 111465531971 ps
T107 /workspace/coverage/default/24.sram_ctrl_stress_all.94288300 Feb 25 01:21:06 PM PST 24 Feb 25 03:42:40 PM PST 24 360163931360 ps
T146 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3229060642 Feb 25 01:19:01 PM PST 24 Feb 25 01:23:47 PM PST 24 4167775476 ps
T147 /workspace/coverage/default/6.sram_ctrl_partial_access.259832317 Feb 25 01:18:50 PM PST 24 Feb 25 01:19:27 PM PST 24 671830188 ps
T148 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.315806119 Feb 25 01:19:14 PM PST 24 Feb 25 01:22:15 PM PST 24 9324399715 ps
T149 /workspace/coverage/default/33.sram_ctrl_bijection.613150428 Feb 25 01:22:30 PM PST 24 Feb 25 01:51:18 PM PST 24 402965151428 ps
T106 /workspace/coverage/default/32.sram_ctrl_stress_all.642931887 Feb 25 01:22:20 PM PST 24 Feb 25 03:22:05 PM PST 24 116522707904 ps
T150 /workspace/coverage/default/32.sram_ctrl_regwen.3815447200 Feb 25 01:22:26 PM PST 24 Feb 25 01:36:06 PM PST 24 9109678244 ps
T151 /workspace/coverage/default/28.sram_ctrl_ram_cfg.3803968756 Feb 25 01:21:38 PM PST 24 Feb 25 01:21:45 PM PST 24 1354315383 ps
T110 /workspace/coverage/default/46.sram_ctrl_stress_all.1475156280 Feb 25 01:25:03 PM PST 24 Feb 25 02:32:37 PM PST 24 147440494839 ps
T152 /workspace/coverage/default/29.sram_ctrl_alert_test.1233491369 Feb 25 01:22:13 PM PST 24 Feb 25 01:22:14 PM PST 24 27207535 ps
T153 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.795388405 Feb 25 01:22:31 PM PST 24 Feb 25 01:29:42 PM PST 24 17688324799 ps
T154 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.677443731 Feb 25 01:24:46 PM PST 24 Feb 25 01:26:10 PM PST 24 759278788 ps
T155 /workspace/coverage/default/29.sram_ctrl_executable.3240538230 Feb 25 01:21:53 PM PST 24 Feb 25 01:25:23 PM PST 24 88221123188 ps
T156 /workspace/coverage/default/42.sram_ctrl_max_throughput.594068990 Feb 25 01:24:21 PM PST 24 Feb 25 01:26:22 PM PST 24 781511912 ps
T157 /workspace/coverage/default/1.sram_ctrl_bijection.3848639643 Feb 25 01:18:34 PM PST 24 Feb 25 01:55:16 PM PST 24 63606421300 ps
T158 /workspace/coverage/default/48.sram_ctrl_alert_test.2894892098 Feb 25 01:25:50 PM PST 24 Feb 25 01:25:51 PM PST 24 76673475 ps
T20 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3074604956 Feb 25 01:22:04 PM PST 24 Feb 25 01:31:27 PM PST 24 4074349088 ps
T159 /workspace/coverage/default/15.sram_ctrl_lc_escalation.867876513 Feb 25 01:19:40 PM PST 24 Feb 25 01:25:29 PM PST 24 55223598974 ps
T160 /workspace/coverage/default/49.sram_ctrl_bijection.2764832871 Feb 25 01:26:09 PM PST 24 Feb 25 02:16:00 PM PST 24 689315769539 ps
T21 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.4100083224 Feb 25 01:19:47 PM PST 24 Feb 25 01:35:14 PM PST 24 19844461587 ps
T161 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.292544537 Feb 25 01:18:58 PM PST 24 Feb 25 01:20:52 PM PST 24 1382684400 ps
T162 /workspace/coverage/default/42.sram_ctrl_smoke.548583738 Feb 25 01:24:13 PM PST 24 Feb 25 01:24:39 PM PST 24 1779718191 ps
T163 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.41492788 Feb 25 01:22:18 PM PST 24 Feb 25 01:25:18 PM PST 24 2112808430 ps
T164 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4094753438 Feb 25 01:18:18 PM PST 24 Feb 25 01:22:36 PM PST 24 11605420893 ps
T165 /workspace/coverage/default/35.sram_ctrl_partial_access.2951920956 Feb 25 01:23:03 PM PST 24 Feb 25 01:23:28 PM PST 24 598211836 ps
T166 /workspace/coverage/default/49.sram_ctrl_regwen.2311785663 Feb 25 01:26:01 PM PST 24 Feb 25 01:52:01 PM PST 24 77004693313 ps
T167 /workspace/coverage/default/17.sram_ctrl_multiple_keys.643698217 Feb 25 01:19:47 PM PST 24 Feb 25 01:27:05 PM PST 24 8811319910 ps
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