Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	122923181	1			T1	1581		T2	256179		T3	196606
triple_byte_access	2597431	1			T1	3421		T2	5145		T4	4024
halfword_access	3995267	1			T1	6492		T2	7612		T4	5847
byte_access	5610057	1			T1	12262		T2	10297		T4	7842
zero_access	1719048	1			T1	7245		T2	2495		T4	1959

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67807233

1

T1

15404

T2

140613

T3

65536

auto[1]

69037751

1

T1

15597

T2

141115

T3

131070

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	60744083	1			T1	133		T2	127950		T3	65536
auto[0]	triple_byte_access	1225127	1			T1	640		T2	2498		T4	1988
auto[0]	halfword_access	1937856	1			T1	2205		T2	3773		T4	2952
auto[0]	byte_access	2866138	1			T1	6630		T2	5159		T4	3887
auto[0]	zero_access	1034029	1			T1	5796		T2	1233		T4	993
auto[1]	word_access	62179098	1			T1	1448		T2	128229		T3	131070
auto[1]	triple_byte_access	1372304	1			T1	2781		T2	2647		T4	2036
auto[1]	halfword_access	2057411	1			T1	4287		T2	3839		T4	2895
auto[1]	byte_access	2743919	1			T1	5632		T2	5138		T4	3955
auto[1]	zero_access	685019	1			T1	1449		T2	1262		T4	966