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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 100.00 97.62 100.00 100.00 99.15 99.70 98.33


Total test records in report: 906
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T799 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1191845048 Feb 25 01:23:12 PM PST 24 Feb 25 01:29:57 PM PST 24 61615538402 ps
T800 /workspace/coverage/default/7.sram_ctrl_regwen.2684414513 Feb 25 01:18:51 PM PST 24 Feb 25 01:23:00 PM PST 24 2903672417 ps
T801 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.611777741 Feb 25 01:21:11 PM PST 24 Feb 25 01:25:02 PM PST 24 3060687648 ps
T802 /workspace/coverage/default/12.sram_ctrl_partial_access.366525672 Feb 25 01:19:18 PM PST 24 Feb 25 01:19:39 PM PST 24 4975592350 ps
T803 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2570755598 Feb 25 01:20:51 PM PST 24 Feb 25 01:24:04 PM PST 24 7696241375 ps
T804 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.957952371 Feb 25 01:22:23 PM PST 24 Feb 25 01:37:56 PM PST 24 6421616683 ps
T805 /workspace/coverage/default/43.sram_ctrl_stress_all.691031784 Feb 25 01:24:33 PM PST 24 Feb 25 03:18:41 PM PST 24 266865148758 ps
T806 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1952621709 Feb 25 01:23:39 PM PST 24 Feb 25 01:28:09 PM PST 24 3579000649 ps
T807 /workspace/coverage/default/39.sram_ctrl_max_throughput.3923517527 Feb 25 01:23:52 PM PST 24 Feb 25 01:26:26 PM PST 24 793630920 ps
T808 /workspace/coverage/default/34.sram_ctrl_alert_test.1293578531 Feb 25 01:22:53 PM PST 24 Feb 25 01:22:54 PM PST 24 33409364 ps
T809 /workspace/coverage/default/23.sram_ctrl_partial_access.1042777962 Feb 25 01:20:46 PM PST 24 Feb 25 01:21:00 PM PST 24 727589201 ps
T810 /workspace/coverage/default/19.sram_ctrl_ram_cfg.2259440792 Feb 25 01:20:05 PM PST 24 Feb 25 01:20:12 PM PST 24 1350826153 ps
T811 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1531786872 Feb 25 01:21:57 PM PST 24 Feb 25 01:28:48 PM PST 24 43051042678 ps
T812 /workspace/coverage/default/20.sram_ctrl_smoke.3036549237 Feb 25 01:20:15 PM PST 24 Feb 25 01:21:49 PM PST 24 19409634036 ps
T813 /workspace/coverage/default/23.sram_ctrl_max_throughput.1456664301 Feb 25 01:20:48 PM PST 24 Feb 25 01:21:21 PM PST 24 2980789036 ps
T814 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2703465322 Feb 25 01:22:55 PM PST 24 Feb 25 01:40:26 PM PST 24 52287263840 ps
T815 /workspace/coverage/default/27.sram_ctrl_multiple_keys.3730507904 Feb 25 01:21:26 PM PST 24 Feb 25 01:41:43 PM PST 24 9100559068 ps
T816 /workspace/coverage/default/12.sram_ctrl_multiple_keys.994120618 Feb 25 01:18:59 PM PST 24 Feb 25 01:40:32 PM PST 24 20436286575 ps
T817 /workspace/coverage/default/3.sram_ctrl_alert_test.2263623874 Feb 25 01:18:40 PM PST 24 Feb 25 01:18:41 PM PST 24 161470866 ps
T818 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1525984003 Feb 25 01:21:26 PM PST 24 Feb 25 01:27:25 PM PST 24 8929223597 ps
T819 /workspace/coverage/default/3.sram_ctrl_max_throughput.49975226 Feb 25 01:18:47 PM PST 24 Feb 25 01:20:34 PM PST 24 2747902407 ps
T820 /workspace/coverage/default/45.sram_ctrl_mem_walk.3365620443 Feb 25 01:24:53 PM PST 24 Feb 25 01:29:33 PM PST 24 13918728037 ps
T821 /workspace/coverage/default/24.sram_ctrl_mem_walk.1340158159 Feb 25 01:21:10 PM PST 24 Feb 25 01:26:04 PM PST 24 14176959226 ps
T822 /workspace/coverage/default/16.sram_ctrl_alert_test.507533486 Feb 25 01:20:00 PM PST 24 Feb 25 01:20:01 PM PST 24 37182580 ps
T823 /workspace/coverage/default/2.sram_ctrl_multiple_keys.1882585345 Feb 25 01:18:27 PM PST 24 Feb 25 01:35:43 PM PST 24 50779022851 ps
T824 /workspace/coverage/default/22.sram_ctrl_smoke.2795743862 Feb 25 01:20:21 PM PST 24 Feb 25 01:20:38 PM PST 24 1492852257 ps
T825 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.268560834 Feb 25 01:18:20 PM PST 24 Feb 25 01:22:09 PM PST 24 7757649707 ps
T826 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3343537668 Feb 25 01:20:04 PM PST 24 Feb 25 01:25:37 PM PST 24 55215237244 ps
T827 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1764548455 Feb 25 01:19:49 PM PST 24 Feb 25 01:22:09 PM PST 24 6201455210 ps
T828 /workspace/coverage/default/9.sram_ctrl_regwen.818215694 Feb 25 01:19:00 PM PST 24 Feb 25 01:33:19 PM PST 24 21156160140 ps
T829 /workspace/coverage/default/14.sram_ctrl_mem_walk.3913420734 Feb 25 01:20:00 PM PST 24 Feb 25 01:22:04 PM PST 24 8229107705 ps
T830 /workspace/coverage/default/39.sram_ctrl_stress_all.2247114159 Feb 25 01:23:50 PM PST 24 Feb 25 02:33:34 PM PST 24 739274829765 ps
T831 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1746383840 Feb 25 01:20:00 PM PST 24 Feb 25 01:39:23 PM PST 24 29807399590 ps
T832 /workspace/coverage/default/26.sram_ctrl_bijection.353733116 Feb 25 01:21:14 PM PST 24 Feb 25 01:48:51 PM PST 24 461316468249 ps
T833 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2755627938 Feb 25 01:26:01 PM PST 24 Feb 25 01:32:36 PM PST 24 10529694578 ps
T834 /workspace/coverage/default/24.sram_ctrl_multiple_keys.2830708903 Feb 25 01:20:50 PM PST 24 Feb 25 01:42:10 PM PST 24 18201689102 ps
T835 /workspace/coverage/default/27.sram_ctrl_max_throughput.1835726920 Feb 25 01:21:29 PM PST 24 Feb 25 01:23:22 PM PST 24 783491954 ps
T836 /workspace/coverage/default/34.sram_ctrl_mem_walk.2274863016 Feb 25 01:22:48 PM PST 24 Feb 25 01:26:53 PM PST 24 4108791932 ps
T837 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2382236619 Feb 25 01:19:54 PM PST 24 Feb 25 01:30:12 PM PST 24 17642087647 ps
T37 /workspace/coverage/default/2.sram_ctrl_sec_cm.922705489 Feb 25 01:18:42 PM PST 24 Feb 25 01:18:46 PM PST 24 827887624 ps
T838 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2150180083 Feb 25 01:25:02 PM PST 24 Feb 25 01:38:26 PM PST 24 14249282908 ps
T86 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1947873596 Feb 25 12:33:59 PM PST 24 Feb 25 12:34:00 PM PST 24 30829269 ps
T57 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3981802387 Feb 25 12:32:59 PM PST 24 Feb 25 12:33:00 PM PST 24 109418120 ps
T58 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2262490975 Feb 25 12:32:53 PM PST 24 Feb 25 12:32:54 PM PST 24 20478794 ps
T59 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3195945107 Feb 25 12:32:50 PM PST 24 Feb 25 12:33:47 PM PST 24 3779896417 ps
T30 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4276912567 Feb 25 12:33:03 PM PST 24 Feb 25 12:33:05 PM PST 24 130955824 ps
T87 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4053821452 Feb 25 12:34:00 PM PST 24 Feb 25 12:34:02 PM PST 24 45414343 ps
T31 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3037898198 Feb 25 12:33:05 PM PST 24 Feb 25 12:33:07 PM PST 24 385669703 ps
T88 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1041651343 Feb 25 12:33:10 PM PST 24 Feb 25 12:33:11 PM PST 24 74429938 ps
T60 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4149451113 Feb 25 12:33:08 PM PST 24 Feb 25 12:33:09 PM PST 24 25795931 ps
T61 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1875888205 Feb 25 12:33:11 PM PST 24 Feb 25 12:34:05 PM PST 24 14228716126 ps
T62 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3115351142 Feb 25 12:32:34 PM PST 24 Feb 25 12:32:35 PM PST 24 11874356 ps
T33 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1565138130 Feb 25 12:32:42 PM PST 24 Feb 25 12:32:46 PM PST 24 135713819 ps
T63 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1688444039 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:53 PM PST 24 10858485 ps
T64 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1199885329 Feb 25 12:33:11 PM PST 24 Feb 25 12:33:14 PM PST 24 44374646 ps
T32 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.268631192 Feb 25 12:32:51 PM PST 24 Feb 25 12:32:54 PM PST 24 270348410 ps
T65 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4118568933 Feb 25 12:32:48 PM PST 24 Feb 25 12:35:49 PM PST 24 73643994844 ps
T66 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.313799552 Feb 25 12:33:09 PM PST 24 Feb 25 12:33:11 PM PST 24 56284187 ps
T839 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1788814336 Feb 25 12:34:00 PM PST 24 Feb 25 12:34:01 PM PST 24 19463475 ps
T840 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.695039047 Feb 25 12:33:04 PM PST 24 Feb 25 12:33:05 PM PST 24 44060072 ps
T841 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1207430441 Feb 25 12:32:50 PM PST 24 Feb 25 12:32:51 PM PST 24 23705974 ps
T46 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3204943884 Feb 25 12:32:54 PM PST 24 Feb 25 12:32:56 PM PST 24 410498263 ps
T47 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3363259873 Feb 25 12:33:09 PM PST 24 Feb 25 12:33:12 PM PST 24 55170315 ps
T48 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1611256352 Feb 25 12:34:30 PM PST 24 Feb 25 12:34:35 PM PST 24 192163296 ps
T842 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.60004240 Feb 25 12:33:07 PM PST 24 Feb 25 12:33:08 PM PST 24 18091939 ps
T843 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1408269722 Feb 25 12:32:53 PM PST 24 Feb 25 12:32:54 PM PST 24 12321878 ps
T94 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4210073719 Feb 25 12:33:00 PM PST 24 Feb 25 12:33:02 PM PST 24 78735177 ps
T844 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4261230645 Feb 25 12:33:02 PM PST 24 Feb 25 12:35:06 PM PST 24 7045593696 ps
T95 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3417326217 Feb 25 12:33:13 PM PST 24 Feb 25 12:33:15 PM PST 24 16993051 ps
T49 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2192645060 Feb 25 12:33:02 PM PST 24 Feb 25 12:33:06 PM PST 24 649703229 ps
T845 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.729272144 Feb 25 12:33:07 PM PST 24 Feb 25 12:33:13 PM PST 24 38749876 ps
T846 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.410074964 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:53 PM PST 24 12265667 ps
T56 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.556531776 Feb 25 12:32:55 PM PST 24 Feb 25 12:32:57 PM PST 24 114323417 ps
T50 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.849417033 Feb 25 12:32:56 PM PST 24 Feb 25 12:32:58 PM PST 24 376509246 ps
T69 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2717967444 Feb 25 12:33:05 PM PST 24 Feb 25 12:34:03 PM PST 24 23093103183 ps
T847 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2473767025 Feb 25 12:32:51 PM PST 24 Feb 25 12:32:53 PM PST 24 120115154 ps
T51 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1060285043 Feb 25 12:32:51 PM PST 24 Feb 25 12:32:53 PM PST 24 62062035 ps
T70 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3128389190 Feb 25 12:33:12 PM PST 24 Feb 25 12:35:38 PM PST 24 7378832526 ps
T52 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1095347556 Feb 25 12:32:44 PM PST 24 Feb 25 12:32:47 PM PST 24 86055695 ps
T848 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2761594025 Feb 25 12:32:39 PM PST 24 Feb 25 12:32:40 PM PST 24 52220179 ps
T53 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1371608676 Feb 25 12:32:54 PM PST 24 Feb 25 12:32:57 PM PST 24 38958790 ps
T849 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3262069369 Feb 25 12:33:06 PM PST 24 Feb 25 12:35:07 PM PST 24 55021628008 ps
T850 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.283333062 Feb 25 12:33:03 PM PST 24 Feb 25 12:33:04 PM PST 24 54555768 ps
T851 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1995216682 Feb 25 12:33:03 PM PST 24 Feb 25 12:33:05 PM PST 24 45262610 ps
T852 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.930198097 Feb 25 12:32:35 PM PST 24 Feb 25 12:32:36 PM PST 24 26293089 ps
T853 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4257813544 Feb 25 12:33:08 PM PST 24 Feb 25 12:33:09 PM PST 24 82247629 ps
T54 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3446234393 Feb 25 12:32:56 PM PST 24 Feb 25 12:32:58 PM PST 24 417510709 ps
T854 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.882573627 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:53 PM PST 24 163862344 ps
T855 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1033486264 Feb 25 12:33:03 PM PST 24 Feb 25 12:33:04 PM PST 24 17824951 ps
T856 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2938236297 Feb 25 12:33:08 PM PST 24 Feb 25 12:33:09 PM PST 24 47883528 ps
T55 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2256139663 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:54 PM PST 24 478400355 ps
T857 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4079389141 Feb 25 12:32:42 PM PST 24 Feb 25 12:32:44 PM PST 24 28839941 ps
T858 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2525122875 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:56 PM PST 24 67528753 ps
T859 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1166125098 Feb 25 12:32:38 PM PST 24 Feb 25 12:32:40 PM PST 24 84239072 ps
T860 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.916692549 Feb 25 12:32:51 PM PST 24 Feb 25 12:32:52 PM PST 24 35224593 ps
T861 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3033528195 Feb 25 12:32:55 PM PST 24 Feb 25 12:32:56 PM PST 24 21486048 ps
T862 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3370308617 Feb 25 12:33:10 PM PST 24 Feb 25 12:33:13 PM PST 24 49079616 ps
T101 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.593940567 Feb 25 12:33:00 PM PST 24 Feb 25 12:33:03 PM PST 24 778705112 ps
T863 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.124719228 Feb 25 12:32:50 PM PST 24 Feb 25 12:32:51 PM PST 24 12128257 ps
T864 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2196811745 Feb 25 12:32:53 PM PST 24 Feb 25 12:32:58 PM PST 24 75917913 ps
T71 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.157928134 Feb 25 12:34:31 PM PST 24 Feb 25 12:36:24 PM PST 24 7127981524 ps
T865 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2108908074 Feb 25 12:32:47 PM PST 24 Feb 25 12:32:49 PM PST 24 1954968556 ps
T866 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4073227538 Feb 25 12:32:51 PM PST 24 Feb 25 12:32:52 PM PST 24 24800386 ps
T72 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3201852571 Feb 25 12:34:19 PM PST 24 Feb 25 12:35:18 PM PST 24 5993572067 ps
T867 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1283234807 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:56 PM PST 24 142516690 ps
T73 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.273263955 Feb 25 12:32:53 PM PST 24 Feb 25 12:32:54 PM PST 24 116386880 ps
T868 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1874620372 Feb 25 12:33:03 PM PST 24 Feb 25 12:33:05 PM PST 24 15249150 ps
T869 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2306608780 Feb 25 12:32:43 PM PST 24 Feb 25 12:32:47 PM PST 24 374176912 ps
T74 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.57804128 Feb 25 12:32:46 PM PST 24 Feb 25 12:32:47 PM PST 24 13509482 ps
T84 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.429984644 Feb 25 12:33:11 PM PST 24 Feb 25 12:34:09 PM PST 24 13666386052 ps
T100 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3457754630 Feb 25 12:33:02 PM PST 24 Feb 25 12:33:04 PM PST 24 246994636 ps
T81 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1900384322 Feb 25 12:33:04 PM PST 24 Feb 25 12:37:36 PM PST 24 37049738702 ps
T870 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3104941638 Feb 25 12:32:55 PM PST 24 Feb 25 12:32:58 PM PST 24 710563250 ps
T871 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1506860505 Feb 25 12:32:56 PM PST 24 Feb 25 12:34:56 PM PST 24 7484428995 ps
T872 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1548830355 Feb 25 12:32:45 PM PST 24 Feb 25 12:32:46 PM PST 24 38495055 ps
T873 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2303948936 Feb 25 12:32:53 PM PST 24 Feb 25 12:32:54 PM PST 24 14753455 ps
T874 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1136912133 Feb 25 12:33:29 PM PST 24 Feb 25 12:33:34 PM PST 24 42000407 ps
T875 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2194918871 Feb 25 12:33:07 PM PST 24 Feb 25 12:33:08 PM PST 24 35863305 ps
T876 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.199604125 Feb 25 12:32:58 PM PST 24 Feb 25 12:32:59 PM PST 24 15047832 ps
T877 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4237892719 Feb 25 12:32:40 PM PST 24 Feb 25 12:32:40 PM PST 24 37281533 ps
T878 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3461114838 Feb 25 12:33:04 PM PST 24 Feb 25 12:33:07 PM PST 24 31256451 ps
T879 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4239773565 Feb 25 12:33:02 PM PST 24 Feb 25 12:33:04 PM PST 24 21291745 ps
T96 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1142313518 Feb 25 12:33:09 PM PST 24 Feb 25 12:33:12 PM PST 24 183734495 ps
T880 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3366731832 Feb 25 12:33:09 PM PST 24 Feb 25 12:33:14 PM PST 24 68279422 ps
T881 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2190364763 Feb 25 12:32:48 PM PST 24 Feb 25 12:32:49 PM PST 24 20163814 ps
T82 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3290231019 Feb 25 12:32:53 PM PST 24 Feb 25 12:33:48 PM PST 24 14765637317 ps
T882 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.677196644 Feb 25 12:32:35 PM PST 24 Feb 25 12:33:29 PM PST 24 3826470521 ps
T883 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3745362283 Feb 25 12:32:52 PM PST 24 Feb 25 12:34:56 PM PST 24 15045317704 ps
T85 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1811767809 Feb 25 12:34:23 PM PST 24 Feb 25 12:36:07 PM PST 24 7077287744 ps
T884 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3057538176 Feb 25 12:32:42 PM PST 24 Feb 25 12:32:44 PM PST 24 680438249 ps
T885 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1259807342 Feb 25 12:32:57 PM PST 24 Feb 25 12:32:58 PM PST 24 26031352 ps
T886 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2568775244 Feb 25 12:32:56 PM PST 24 Feb 25 12:32:57 PM PST 24 28058281 ps
T97 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1007192017 Feb 25 12:33:13 PM PST 24 Feb 25 12:33:15 PM PST 24 334574130 ps
T887 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3509911814 Feb 25 12:32:51 PM PST 24 Feb 25 12:32:51 PM PST 24 61622463 ps
T888 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3294290605 Feb 25 12:32:43 PM PST 24 Feb 25 12:32:43 PM PST 24 21547521 ps
T889 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4261712885 Feb 25 12:32:43 PM PST 24 Feb 25 12:32:45 PM PST 24 569652723 ps
T890 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2030328381 Feb 25 12:33:02 PM PST 24 Feb 25 12:33:03 PM PST 24 58725178 ps
T98 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1642907483 Feb 25 12:33:19 PM PST 24 Feb 25 12:33:22 PM PST 24 1454441889 ps
T891 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2917241501 Feb 25 12:33:08 PM PST 24 Feb 25 12:33:11 PM PST 24 795230405 ps
T892 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3375762382 Feb 25 12:32:49 PM PST 24 Feb 25 12:32:52 PM PST 24 26294749 ps
T893 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1103680096 Feb 25 12:32:32 PM PST 24 Feb 25 12:32:34 PM PST 24 467281454 ps
T99 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.551796810 Feb 25 12:32:56 PM PST 24 Feb 25 12:32:59 PM PST 24 318231442 ps
T894 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2297966708 Feb 25 12:33:03 PM PST 24 Feb 25 12:33:07 PM PST 24 43858128 ps
T895 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1591716854 Feb 25 12:32:34 PM PST 24 Feb 25 12:32:35 PM PST 24 20983313 ps
T83 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2147671630 Feb 25 12:32:41 PM PST 24 Feb 25 12:34:47 PM PST 24 7062512947 ps
T896 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2914908480 Feb 25 12:33:06 PM PST 24 Feb 25 12:33:07 PM PST 24 32019419 ps
T897 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1610576556 Feb 25 12:33:16 PM PST 24 Feb 25 12:33:17 PM PST 24 21947325 ps
T898 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4254460451 Feb 25 12:32:42 PM PST 24 Feb 25 12:32:43 PM PST 24 189405399 ps
T899 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.431918958 Feb 25 12:32:58 PM PST 24 Feb 25 12:34:04 PM PST 24 28402547658 ps
T900 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.697502705 Feb 25 12:32:59 PM PST 24 Feb 25 12:33:02 PM PST 24 190210661 ps
T901 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3457566943 Feb 25 12:32:46 PM PST 24 Feb 25 12:32:47 PM PST 24 17608904 ps
T902 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1378898080 Feb 25 12:32:39 PM PST 24 Feb 25 12:32:42 PM PST 24 104354277 ps
T903 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2401273025 Feb 25 12:33:08 PM PST 24 Feb 25 12:33:10 PM PST 24 94438147 ps
T904 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4139482071 Feb 25 12:32:44 PM PST 24 Feb 25 12:35:21 PM PST 24 7703805135 ps
T905 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3089526780 Feb 25 12:33:04 PM PST 24 Feb 25 12:33:06 PM PST 24 516205516 ps
T906 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2090550235 Feb 25 12:33:10 PM PST 24 Feb 25 12:34:14 PM PST 24 3931422726 ps

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.760434901
Short name T2
Test name
Test status
Simulation time 5572172231 ps
CPU time 396.97 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:25:40 PM PST 24
Peak memory 202384 kb
Host smart-9e0d5afc-2c94-478e-9a8d-5012fc9ab5a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760434901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_stress_pipeline.760434901
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.3450763033
Short name T8
Test name
Test status
Simulation time 340523784256 ps
CPU time 7114.55 seconds
Started Feb 25 01:18:24 PM PST 24
Finished Feb 25 03:17:00 PM PST 24
Peak memory 377348 kb
Host smart-508e4fbd-a553-4c2d-8e01-2c24bf7dfec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450763033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.3450763033
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4276912567
Short name T30
Test name
Test status
Simulation time 130955824 ps
CPU time 2.13 seconds
Started Feb 25 12:33:03 PM PST 24
Finished Feb 25 12:33:05 PM PST 24
Peak memory 202452 kb
Host smart-861db724-97c8-4f64-be58-ab1bfc70229c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276912567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.4276912567
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1565138130
Short name T33
Test name
Test status
Simulation time 135713819 ps
CPU time 3.94 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:46 PM PST 24
Peak memory 202508 kb
Host smart-b1ec55e1-6727-415c-a71e-bc5e56477fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565138130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.1565138130
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.2901578802
Short name T24
Test name
Test status
Simulation time 235137928 ps
CPU time 3.3 seconds
Started Feb 25 01:18:19 PM PST 24
Finished Feb 25 01:18:22 PM PST 24
Peak memory 231880 kb
Host smart-c38b802b-5d73-444b-b729-dfd14cc2f1ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901578802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.2901578802
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.1652247370
Short name T14
Test name
Test status
Simulation time 87059276383 ps
CPU time 1354.25 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:41:53 PM PST 24
Peak memory 378308 kb
Host smart-0f5aa143-49ca-4150-a172-84d9852bf2ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652247370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.1652247370
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3975442536
Short name T254
Test name
Test status
Simulation time 11994425207 ps
CPU time 254.53 seconds
Started Feb 25 01:18:29 PM PST 24
Finished Feb 25 01:22:44 PM PST 24
Peak memory 215700 kb
Host smart-edc7ec6b-2074-4889-acf8-aabb8c4427c9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975442536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3975442536
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3966755534
Short name T19
Test name
Test status
Simulation time 17663656055 ps
CPU time 913.89 seconds
Started Feb 25 01:19:37 PM PST 24
Finished Feb 25 01:34:51 PM PST 24
Peak memory 377260 kb
Host smart-55087edd-2123-4b5d-9d72-df4a2540841a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966755534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.3966755534
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1875888205
Short name T61
Test name
Test status
Simulation time 14228716126 ps
CPU time 52.25 seconds
Started Feb 25 12:33:11 PM PST 24
Finished Feb 25 12:34:05 PM PST 24
Peak memory 202692 kb
Host smart-889aefde-4001-4998-ac24-135e410686c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875888205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.1875888205
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.100855432
Short name T13
Test name
Test status
Simulation time 588061252 ps
CPU time 5.68 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:18:53 PM PST 24
Peak memory 202488 kb
Host smart-ca156088-db1a-42c6-8cd4-d147ea55b25f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100855432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.100855432
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.3746036249
Short name T27
Test name
Test status
Simulation time 51205372 ps
CPU time 0.66 seconds
Started Feb 25 01:18:18 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 201932 kb
Host smart-7cb6e553-ae77-4453-bfe0-000cbb13d6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746036249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.3746036249
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.3984483640
Short name T22
Test name
Test status
Simulation time 147070865814 ps
CPU time 4611.37 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 02:35:52 PM PST 24
Peak memory 379312 kb
Host smart-b3d39a8b-d937-4d3d-a716-0a38cbacbbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984483640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.3984483640
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2192645060
Short name T49
Test name
Test status
Simulation time 649703229 ps
CPU time 2.77 seconds
Started Feb 25 12:33:02 PM PST 24
Finished Feb 25 12:33:06 PM PST 24
Peak memory 202504 kb
Host smart-3feb7b1f-8f36-4fab-b385-d051e6b8ffbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192645060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2192645060
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3719760953
Short name T6
Test name
Test status
Simulation time 249516019891 ps
CPU time 1396.21 seconds
Started Feb 25 01:24:43 PM PST 24
Finished Feb 25 01:48:00 PM PST 24
Peak memory 375216 kb
Host smart-8f7674f9-4ddc-4972-adf2-ff28038a04c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719760953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3719760953
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4261712885
Short name T889
Test name
Test status
Simulation time 569652723 ps
CPU time 1.52 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:45 PM PST 24
Peak memory 202664 kb
Host smart-9a0e5a9f-0980-4b49-9c3d-428249ffeb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261712885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.4261712885
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.593940567
Short name T101
Test name
Test status
Simulation time 778705112 ps
CPU time 2.54 seconds
Started Feb 25 12:33:00 PM PST 24
Finished Feb 25 12:33:03 PM PST 24
Peak memory 202472 kb
Host smart-8e4987f0-7c47-43f7-bc63-e5883ba9e7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593940567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.sram_ctrl_tl_intg_err.593940567
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3294290605
Short name T888
Test name
Test status
Simulation time 21547521 ps
CPU time 0.68 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 202144 kb
Host smart-b4001d11-eccf-4d80-b094-b804d30d7850
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294290605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.3294290605
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1103680096
Short name T893
Test name
Test status
Simulation time 467281454 ps
CPU time 2.17 seconds
Started Feb 25 12:32:32 PM PST 24
Finished Feb 25 12:32:34 PM PST 24
Peak memory 202372 kb
Host smart-3451a453-0cb8-4534-8576-10562bd5b852
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103680096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.1103680096
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1591716854
Short name T895
Test name
Test status
Simulation time 20983313 ps
CPU time 0.71 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:35 PM PST 24
Peak memory 202080 kb
Host smart-34cf87e2-a512-44a8-bf63-352ff5194db4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591716854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.1591716854
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4254460451
Short name T898
Test name
Test status
Simulation time 189405399 ps
CPU time 0.67 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 202424 kb
Host smart-71a4c2f9-cafe-4f9d-8b9e-87d36749bd5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254460451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.4254460451
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.157928134
Short name T71
Test name
Test status
Simulation time 7127981524 ps
CPU time 112.46 seconds
Started Feb 25 12:34:31 PM PST 24
Finished Feb 25 12:36:24 PM PST 24
Peak memory 202612 kb
Host smart-a693a0b0-811a-40ba-95fb-84820a0b8783
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157928134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.157928134
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4237892719
Short name T877
Test name
Test status
Simulation time 37281533 ps
CPU time 0.69 seconds
Started Feb 25 12:32:40 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 202080 kb
Host smart-ce415634-85eb-4bec-bf30-241bfd488318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237892719 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.4237892719
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1095347556
Short name T52
Test name
Test status
Simulation time 86055695 ps
CPU time 2.44 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 202720 kb
Host smart-55ec20df-43ca-4ee7-b3cd-806b2c5000c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095347556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.1095347556
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.556531776
Short name T56
Test name
Test status
Simulation time 114323417 ps
CPU time 1.43 seconds
Started Feb 25 12:32:55 PM PST 24
Finished Feb 25 12:32:57 PM PST 24
Peak memory 202424 kb
Host smart-e889781f-68e9-49ea-b6fb-d7ad698b007e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556531776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.sram_ctrl_tl_intg_err.556531776
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1207430441
Short name T841
Test name
Test status
Simulation time 23705974 ps
CPU time 0.71 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:32:51 PM PST 24
Peak memory 202144 kb
Host smart-c5d6f912-8eb5-4f42-bc2b-9217cb68b4bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207430441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.1207430441
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2761594025
Short name T848
Test name
Test status
Simulation time 52220179 ps
CPU time 1.16 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 202296 kb
Host smart-5b1fcc4c-25f2-4be6-8ec2-b2f3febe6d94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761594025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2761594025
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2262490975
Short name T58
Test name
Test status
Simulation time 20478794 ps
CPU time 0.68 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 202096 kb
Host smart-213068d0-5202-48c0-9a58-2a37d1456c74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262490975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.2262490975
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3115351142
Short name T62
Test name
Test status
Simulation time 11874356 ps
CPU time 0.65 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:35 PM PST 24
Peak memory 202176 kb
Host smart-657d0332-2f15-4a3d-a428-f13e92ddcd0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115351142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3115351142
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2147671630
Short name T83
Test name
Test status
Simulation time 7062512947 ps
CPU time 125.08 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:34:47 PM PST 24
Peak memory 202704 kb
Host smart-d3a6a01f-9144-4a30-b79e-9831cdc2cd54
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147671630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.2147671630
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3509911814
Short name T887
Test name
Test status
Simulation time 61622463 ps
CPU time 0.75 seconds
Started Feb 25 12:32:51 PM PST 24
Finished Feb 25 12:32:51 PM PST 24
Peak memory 202196 kb
Host smart-28692d9e-c1c1-4bf7-8238-9f09b5be4c8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509911814 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3509911814
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2196811745
Short name T864
Test name
Test status
Simulation time 75917913 ps
CPU time 4.8 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 202484 kb
Host smart-4321fc07-30c5-49dd-b717-5b2a08b7938d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196811745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2196811745
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3104941638
Short name T870
Test name
Test status
Simulation time 710563250 ps
CPU time 2.55 seconds
Started Feb 25 12:32:55 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 202484 kb
Host smart-70f82ee1-b05b-4b65-a325-13f530458226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104941638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.3104941638
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4073227538
Short name T866
Test name
Test status
Simulation time 24800386 ps
CPU time 0.64 seconds
Started Feb 25 12:32:51 PM PST 24
Finished Feb 25 12:32:52 PM PST 24
Peak memory 202132 kb
Host smart-0c48427d-ef6e-4e53-84ef-ec6b2368c3bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073227538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.4073227538
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3128389190
Short name T70
Test name
Test status
Simulation time 7378832526 ps
CPU time 145.31 seconds
Started Feb 25 12:33:12 PM PST 24
Finished Feb 25 12:35:38 PM PST 24
Peak memory 210924 kb
Host smart-19e4200e-f5bc-46d7-baf2-5647ee85716f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128389190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3128389190
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.695039047
Short name T840
Test name
Test status
Simulation time 44060072 ps
CPU time 0.71 seconds
Started Feb 25 12:33:04 PM PST 24
Finished Feb 25 12:33:05 PM PST 24
Peak memory 202016 kb
Host smart-f288851a-a58e-47aa-8c31-994557491a90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695039047 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.695039047
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1378898080
Short name T902
Test name
Test status
Simulation time 104354277 ps
CPU time 2.28 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:42 PM PST 24
Peak memory 210696 kb
Host smart-04f0c67b-a39f-4af5-a8b4-f03d03c725e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378898080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.1378898080
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2108908074
Short name T865
Test name
Test status
Simulation time 1954968556 ps
CPU time 1.68 seconds
Started Feb 25 12:32:47 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 202428 kb
Host smart-d7cee15f-3629-461d-b43b-0ee3b94d2524
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108908074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2108908074
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3417326217
Short name T95
Test name
Test status
Simulation time 16993051 ps
CPU time 0.7 seconds
Started Feb 25 12:33:13 PM PST 24
Finished Feb 25 12:33:15 PM PST 24
Peak memory 202128 kb
Host smart-ab7acfc8-c037-4346-a5c7-2672260c00da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417326217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.3417326217
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1900384322
Short name T81
Test name
Test status
Simulation time 37049738702 ps
CPU time 271.4 seconds
Started Feb 25 12:33:04 PM PST 24
Finished Feb 25 12:37:36 PM PST 24
Peak memory 202528 kb
Host smart-eb9c6358-6a88-4623-b81f-af98d7e9f0cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900384322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1900384322
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3981802387
Short name T57
Test name
Test status
Simulation time 109418120 ps
CPU time 0.88 seconds
Started Feb 25 12:32:59 PM PST 24
Finished Feb 25 12:33:00 PM PST 24
Peak memory 202236 kb
Host smart-8db029e2-6599-42f8-b364-12cdafc5a1dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981802387 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.3981802387
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1611256352
Short name T48
Test name
Test status
Simulation time 192163296 ps
CPU time 3.93 seconds
Started Feb 25 12:34:30 PM PST 24
Finished Feb 25 12:34:35 PM PST 24
Peak memory 202380 kb
Host smart-a4211e99-19e0-45ab-9c71-7b8a012a46d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611256352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.1611256352
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2194918871
Short name T875
Test name
Test status
Simulation time 35863305 ps
CPU time 0.65 seconds
Started Feb 25 12:33:07 PM PST 24
Finished Feb 25 12:33:08 PM PST 24
Peak memory 202124 kb
Host smart-a021b5b8-d84b-4cb3-ad04-b88032e67042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194918871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2194918871
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.677196644
Short name T882
Test name
Test status
Simulation time 3826470521 ps
CPU time 53.36 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:33:29 PM PST 24
Peak memory 202640 kb
Host smart-94e40999-6cff-41b9-a4d5-26becc9c84dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677196644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.677196644
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2914908480
Short name T896
Test name
Test status
Simulation time 32019419 ps
CPU time 0.69 seconds
Started Feb 25 12:33:06 PM PST 24
Finished Feb 25 12:33:07 PM PST 24
Peak memory 202216 kb
Host smart-d89ecc4f-b70c-4beb-80b9-4b8087f9c5cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914908480 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2914908480
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1060285043
Short name T51
Test name
Test status
Simulation time 62062035 ps
CPU time 1.76 seconds
Started Feb 25 12:32:51 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 202520 kb
Host smart-8823fb2e-23ef-4958-a53c-133571a53a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060285043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.1060285043
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1007192017
Short name T97
Test name
Test status
Simulation time 334574130 ps
CPU time 2.47 seconds
Started Feb 25 12:33:13 PM PST 24
Finished Feb 25 12:33:15 PM PST 24
Peak memory 202456 kb
Host smart-9d990f53-c57b-4fa8-a0de-8e711ace3996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007192017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.1007192017
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1610576556
Short name T897
Test name
Test status
Simulation time 21947325 ps
CPU time 0.63 seconds
Started Feb 25 12:33:16 PM PST 24
Finished Feb 25 12:33:17 PM PST 24
Peak memory 202084 kb
Host smart-d5e81874-d457-4572-a9f9-3d99e530aea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610576556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1610576556
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1408269722
Short name T843
Test name
Test status
Simulation time 12321878 ps
CPU time 0.67 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 202208 kb
Host smart-4fd70f14-d42f-407d-b019-7287427903e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408269722 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1408269722
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1136912133
Short name T874
Test name
Test status
Simulation time 42000407 ps
CPU time 3.79 seconds
Started Feb 25 12:33:29 PM PST 24
Finished Feb 25 12:33:34 PM PST 24
Peak memory 202540 kb
Host smart-6eac959f-ffc1-43f0-8ae5-54e78a610430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136912133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1136912133
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1142313518
Short name T96
Test name
Test status
Simulation time 183734495 ps
CPU time 2.07 seconds
Started Feb 25 12:33:09 PM PST 24
Finished Feb 25 12:33:12 PM PST 24
Peak memory 202484 kb
Host smart-355f5606-1738-4bd6-ad25-33b03561b940
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142313518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.1142313518
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1995216682
Short name T851
Test name
Test status
Simulation time 45262610 ps
CPU time 0.67 seconds
Started Feb 25 12:33:03 PM PST 24
Finished Feb 25 12:33:05 PM PST 24
Peak memory 201608 kb
Host smart-ffba93ad-7c77-46ab-bfe8-2ff9c62da3b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995216682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.1995216682
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1811767809
Short name T85
Test name
Test status
Simulation time 7077287744 ps
CPU time 103.78 seconds
Started Feb 25 12:34:23 PM PST 24
Finished Feb 25 12:36:07 PM PST 24
Peak memory 210816 kb
Host smart-fdfcbc05-a95e-4fd3-96f4-34b85a06f948
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811767809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1811767809
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.124719228
Short name T863
Test name
Test status
Simulation time 12128257 ps
CPU time 0.67 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:32:51 PM PST 24
Peak memory 202208 kb
Host smart-399ffac1-2777-4e98-8fd9-2f702712a9ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124719228 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.124719228
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3461114838
Short name T878
Test name
Test status
Simulation time 31256451 ps
CPU time 2.76 seconds
Started Feb 25 12:33:04 PM PST 24
Finished Feb 25 12:33:07 PM PST 24
Peak memory 202532 kb
Host smart-c8438179-b146-4beb-94c0-7a9331e86459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461114838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.3461114838
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3204943884
Short name T46
Test name
Test status
Simulation time 410498263 ps
CPU time 1.42 seconds
Started Feb 25 12:32:54 PM PST 24
Finished Feb 25 12:32:56 PM PST 24
Peak memory 202432 kb
Host smart-c23d9abf-0513-4d61-bc31-ea9af05e242a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204943884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3204943884
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2303948936
Short name T873
Test name
Test status
Simulation time 14753455 ps
CPU time 0.64 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 202132 kb
Host smart-7d8eb977-6983-4b42-9852-85928610c317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303948936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.2303948936
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4118568933
Short name T65
Test name
Test status
Simulation time 73643994844 ps
CPU time 180.35 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:35:49 PM PST 24
Peak memory 202708 kb
Host smart-c4f47487-63c8-4d49-974b-3dcf3f3f5798
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118568933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.4118568933
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4257813544
Short name T853
Test name
Test status
Simulation time 82247629 ps
CPU time 0.74 seconds
Started Feb 25 12:33:08 PM PST 24
Finished Feb 25 12:33:09 PM PST 24
Peak memory 202232 kb
Host smart-ee44f335-fc2c-4472-bf0f-1bbcb4628a6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257813544 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.4257813544
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3363259873
Short name T47
Test name
Test status
Simulation time 55170315 ps
CPU time 2.23 seconds
Started Feb 25 12:33:09 PM PST 24
Finished Feb 25 12:33:12 PM PST 24
Peak memory 202536 kb
Host smart-7775358c-900b-464e-964a-97840b325ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363259873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.3363259873
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3457754630
Short name T100
Test name
Test status
Simulation time 246994636 ps
CPU time 1.28 seconds
Started Feb 25 12:33:02 PM PST 24
Finished Feb 25 12:33:04 PM PST 24
Peak memory 202428 kb
Host smart-c33a240c-de0e-4fee-a603-5f5de65d086e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457754630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.3457754630
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2938236297
Short name T856
Test name
Test status
Simulation time 47883528 ps
CPU time 0.68 seconds
Started Feb 25 12:33:08 PM PST 24
Finished Feb 25 12:33:09 PM PST 24
Peak memory 202088 kb
Host smart-4e1a6168-69a1-4cd5-9610-e9a5f8610322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938236297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.2938236297
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4261230645
Short name T844
Test name
Test status
Simulation time 7045593696 ps
CPU time 123.57 seconds
Started Feb 25 12:33:02 PM PST 24
Finished Feb 25 12:35:06 PM PST 24
Peak memory 202688 kb
Host smart-301b9903-3625-410d-a160-6b82bf9f6975
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261230645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.4261230645
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.283333062
Short name T850
Test name
Test status
Simulation time 54555768 ps
CPU time 0.76 seconds
Started Feb 25 12:33:03 PM PST 24
Finished Feb 25 12:33:04 PM PST 24
Peak memory 202228 kb
Host smart-755e9a93-16bb-4100-a319-2d0aa73be802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283333062 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.283333062
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3366731832
Short name T880
Test name
Test status
Simulation time 68279422 ps
CPU time 3.32 seconds
Started Feb 25 12:33:09 PM PST 24
Finished Feb 25 12:33:14 PM PST 24
Peak memory 202464 kb
Host smart-c18b5dc4-4304-47bd-9741-631eb9c2bc82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366731832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.3366731832
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1642907483
Short name T98
Test name
Test status
Simulation time 1454441889 ps
CPU time 2.25 seconds
Started Feb 25 12:33:19 PM PST 24
Finished Feb 25 12:33:22 PM PST 24
Peak memory 210688 kb
Host smart-1098a5af-a072-431e-907f-a764a5fb5b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642907483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1642907483
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.410074964
Short name T846
Test name
Test status
Simulation time 12265667 ps
CPU time 0.67 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 202184 kb
Host smart-820e2ca5-1b7b-428a-a928-b9a53d1f1a62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410074964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 17.sram_ctrl_csr_rw.410074964
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3290231019
Short name T82
Test name
Test status
Simulation time 14765637317 ps
CPU time 55.13 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 202700 kb
Host smart-603c1875-c1db-4eaf-99da-faab3e513db6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290231019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3290231019
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1033486264
Short name T855
Test name
Test status
Simulation time 17824951 ps
CPU time 0.76 seconds
Started Feb 25 12:33:03 PM PST 24
Finished Feb 25 12:33:04 PM PST 24
Peak memory 202212 kb
Host smart-c6ff2ca2-22bc-4f87-a808-09a86de32dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033486264 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1033486264
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3370308617
Short name T862
Test name
Test status
Simulation time 49079616 ps
CPU time 1.88 seconds
Started Feb 25 12:33:10 PM PST 24
Finished Feb 25 12:33:13 PM PST 24
Peak memory 202492 kb
Host smart-754094e7-0fbe-4a17-871d-e3bcf480cad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370308617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.3370308617
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1788814336
Short name T839
Test name
Test status
Simulation time 19463475 ps
CPU time 0.72 seconds
Started Feb 25 12:34:00 PM PST 24
Finished Feb 25 12:34:01 PM PST 24
Peak memory 200104 kb
Host smart-b8a6bd97-bab4-40a2-9fdf-fbb79cfcf814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788814336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.1788814336
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.429984644
Short name T84
Test name
Test status
Simulation time 13666386052 ps
CPU time 56.62 seconds
Started Feb 25 12:33:11 PM PST 24
Finished Feb 25 12:34:09 PM PST 24
Peak memory 211920 kb
Host smart-9136269f-f184-4f12-b8c5-d87092047eec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429984644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.429984644
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1041651343
Short name T88
Test name
Test status
Simulation time 74429938 ps
CPU time 0.71 seconds
Started Feb 25 12:33:10 PM PST 24
Finished Feb 25 12:33:11 PM PST 24
Peak memory 202212 kb
Host smart-77e5441e-d520-491c-a185-f6ee53435e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041651343 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1041651343
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1283234807
Short name T867
Test name
Test status
Simulation time 142516690 ps
CPU time 3.34 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:56 PM PST 24
Peak memory 202544 kb
Host smart-7582009c-ced2-4838-9bba-39e9ab275a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283234807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.1283234807
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.849417033
Short name T50
Test name
Test status
Simulation time 376509246 ps
CPU time 2.41 seconds
Started Feb 25 12:32:56 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 202432 kb
Host smart-f122df3f-38da-4de8-9f3e-60d44b4b914a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849417033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.sram_ctrl_tl_intg_err.849417033
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.60004240
Short name T842
Test name
Test status
Simulation time 18091939 ps
CPU time 0.65 seconds
Started Feb 25 12:33:07 PM PST 24
Finished Feb 25 12:33:08 PM PST 24
Peak memory 202172 kb
Host smart-e2b70d9d-0cc5-4fb6-95af-b421d4463f00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60004240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.sram_ctrl_csr_rw.60004240
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3262069369
Short name T849
Test name
Test status
Simulation time 55021628008 ps
CPU time 121.36 seconds
Started Feb 25 12:33:06 PM PST 24
Finished Feb 25 12:35:07 PM PST 24
Peak memory 202768 kb
Host smart-0a3f9838-4433-4bed-ab56-bbac40d00a0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262069369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3262069369
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1199885329
Short name T64
Test name
Test status
Simulation time 44374646 ps
CPU time 0.77 seconds
Started Feb 25 12:33:11 PM PST 24
Finished Feb 25 12:33:14 PM PST 24
Peak memory 202208 kb
Host smart-99569688-7a7f-40fc-8895-e89295456ff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199885329 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1199885329
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2401273025
Short name T903
Test name
Test status
Simulation time 94438147 ps
CPU time 2.35 seconds
Started Feb 25 12:33:08 PM PST 24
Finished Feb 25 12:33:10 PM PST 24
Peak memory 202472 kb
Host smart-39bf7fc8-2dc5-48ee-9ae2-3fd0c5b71889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401273025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.2401273025
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2917241501
Short name T891
Test name
Test status
Simulation time 795230405 ps
CPU time 2.31 seconds
Started Feb 25 12:33:08 PM PST 24
Finished Feb 25 12:33:11 PM PST 24
Peak memory 202432 kb
Host smart-5e645d25-318b-4020-873e-1394d756e28e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917241501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.2917241501
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.916692549
Short name T860
Test name
Test status
Simulation time 35224593 ps
CPU time 0.71 seconds
Started Feb 25 12:32:51 PM PST 24
Finished Feb 25 12:32:52 PM PST 24
Peak memory 202120 kb
Host smart-2133edfb-a19b-4853-adb5-188fe7b6cfb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916692549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_aliasing.916692549
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4079389141
Short name T857
Test name
Test status
Simulation time 28839941 ps
CPU time 1.32 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:44 PM PST 24
Peak memory 202348 kb
Host smart-60da748b-ba7a-4536-a6a9-4e91c9aa18ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079389141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.4079389141
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4149451113
Short name T60
Test name
Test status
Simulation time 25795931 ps
CPU time 0.66 seconds
Started Feb 25 12:33:08 PM PST 24
Finished Feb 25 12:33:09 PM PST 24
Peak memory 202108 kb
Host smart-e1dd805c-4426-4993-85ed-9da2a8efb998
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149451113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.4149451113
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1688444039
Short name T63
Test name
Test status
Simulation time 10858485 ps
CPU time 0.64 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 202160 kb
Host smart-3ea8f5d6-ad0b-43ac-b218-7e5356ae2f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688444039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.1688444039
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4139482071
Short name T904
Test name
Test status
Simulation time 7703805135 ps
CPU time 156.05 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:35:21 PM PST 24
Peak memory 210916 kb
Host smart-004ebd25-7e9a-430c-b2af-0639f2d8dd02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139482071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.4139482071
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.313799552
Short name T66
Test name
Test status
Simulation time 56284187 ps
CPU time 0.8 seconds
Started Feb 25 12:33:09 PM PST 24
Finished Feb 25 12:33:11 PM PST 24
Peak memory 202232 kb
Host smart-ac767bc0-c4da-458c-97a4-6284758ebcaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313799552 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.313799552
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3457566943
Short name T901
Test name
Test status
Simulation time 17608904 ps
CPU time 0.68 seconds
Started Feb 25 12:32:46 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 202076 kb
Host smart-f884ab4e-8753-4bf9-955f-585a43f4d066
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457566943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.3457566943
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3057538176
Short name T884
Test name
Test status
Simulation time 680438249 ps
CPU time 2.47 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:44 PM PST 24
Peak memory 202396 kb
Host smart-782c004b-2eea-414e-9300-27d9230bcd61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057538176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.3057538176
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.882573627
Short name T854
Test name
Test status
Simulation time 163862344 ps
CPU time 0.65 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 202128 kb
Host smart-9046ee02-981b-464f-bbaf-f1921c4efb65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882573627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_hw_reset.882573627
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2030328381
Short name T890
Test name
Test status
Simulation time 58725178 ps
CPU time 0.67 seconds
Started Feb 25 12:33:02 PM PST 24
Finished Feb 25 12:33:03 PM PST 24
Peak memory 202128 kb
Host smart-215cbd03-6327-4db5-9582-5fc80afd16da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030328381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2030328381
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3195945107
Short name T59
Test name
Test status
Simulation time 3779896417 ps
CPU time 56.7 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:33:47 PM PST 24
Peak memory 202692 kb
Host smart-1554e052-e5b7-4e4d-b81f-9876f93b78c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195945107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3195945107
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1548830355
Short name T872
Test name
Test status
Simulation time 38495055 ps
CPU time 0.81 seconds
Started Feb 25 12:32:45 PM PST 24
Finished Feb 25 12:32:46 PM PST 24
Peak memory 202244 kb
Host smart-c8fd65b3-8e7c-4a6e-b8a9-55e69bc35eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548830355 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1548830355
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2306608780
Short name T869
Test name
Test status
Simulation time 374176912 ps
CPU time 3.1 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 202468 kb
Host smart-93f99973-7abe-48ee-81e2-021e0935ad2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306608780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.2306608780
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3446234393
Short name T54
Test name
Test status
Simulation time 417510709 ps
CPU time 2.21 seconds
Started Feb 25 12:32:56 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 202460 kb
Host smart-6783ea24-17ed-46ad-960b-3518a1da3058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446234393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.3446234393
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.273263955
Short name T73
Test name
Test status
Simulation time 116386880 ps
CPU time 0.74 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 202160 kb
Host smart-c26f2a88-974c-4d0a-b429-8c733d2ef32f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273263955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_aliasing.273263955
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2473767025
Short name T847
Test name
Test status
Simulation time 120115154 ps
CPU time 2.14 seconds
Started Feb 25 12:32:51 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 202360 kb
Host smart-c73af9dc-6e19-4f95-a044-d95d2e4c3b83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473767025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.2473767025
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1874620372
Short name T868
Test name
Test status
Simulation time 15249150 ps
CPU time 0.64 seconds
Started Feb 25 12:33:03 PM PST 24
Finished Feb 25 12:33:05 PM PST 24
Peak memory 201552 kb
Host smart-aab16531-1f81-4da1-bebc-5ae923744aea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874620372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.1874620372
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1259807342
Short name T885
Test name
Test status
Simulation time 26031352 ps
CPU time 0.63 seconds
Started Feb 25 12:32:57 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 201628 kb
Host smart-d170fd16-9b99-459c-89ee-86a6eb26f3cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259807342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.1259807342
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1506860505
Short name T871
Test name
Test status
Simulation time 7484428995 ps
CPU time 120.03 seconds
Started Feb 25 12:32:56 PM PST 24
Finished Feb 25 12:34:56 PM PST 24
Peak memory 202660 kb
Host smart-6e0ec47b-7e80-481a-a0b4-103b9ab30822
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506860505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1506860505
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2568775244
Short name T886
Test name
Test status
Simulation time 28058281 ps
CPU time 0.7 seconds
Started Feb 25 12:32:56 PM PST 24
Finished Feb 25 12:32:57 PM PST 24
Peak memory 202188 kb
Host smart-88186a25-5887-4520-9f0f-c49db1615d50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568775244 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2568775244
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2525122875
Short name T858
Test name
Test status
Simulation time 67528753 ps
CPU time 3.87 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:56 PM PST 24
Peak memory 202532 kb
Host smart-0e736978-9f58-42b3-8fb2-e724dfa979e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525122875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2525122875
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.268631192
Short name T32
Test name
Test status
Simulation time 270348410 ps
CPU time 2.57 seconds
Started Feb 25 12:32:51 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 202480 kb
Host smart-e0d91d71-2cb1-48f2-9569-a3d0b66036c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268631192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.sram_ctrl_tl_intg_err.268631192
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.930198097
Short name T852
Test name
Test status
Simulation time 26293089 ps
CPU time 0.64 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 202128 kb
Host smart-591e9c01-6710-4718-9bdb-de3578a992d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930198097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 5.sram_ctrl_csr_rw.930198097
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3201852571
Short name T72
Test name
Test status
Simulation time 5993572067 ps
CPU time 59.46 seconds
Started Feb 25 12:34:19 PM PST 24
Finished Feb 25 12:35:18 PM PST 24
Peak memory 210768 kb
Host smart-fdc620d2-1f91-41ea-aed7-4b7db92cc6f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201852571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3201852571
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1947873596
Short name T86
Test name
Test status
Simulation time 30829269 ps
CPU time 0.78 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:00 PM PST 24
Peak memory 200692 kb
Host smart-e8231f12-e827-4b71-a831-6835adeff9fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947873596 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1947873596
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3375762382
Short name T892
Test name
Test status
Simulation time 26294749 ps
CPU time 2.6 seconds
Started Feb 25 12:32:49 PM PST 24
Finished Feb 25 12:32:52 PM PST 24
Peak memory 202492 kb
Host smart-58152a7c-998c-42ad-a302-34e3ebb7aad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375762382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3375762382
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.697502705
Short name T900
Test name
Test status
Simulation time 190210661 ps
CPU time 2.37 seconds
Started Feb 25 12:32:59 PM PST 24
Finished Feb 25 12:33:02 PM PST 24
Peak memory 202460 kb
Host smart-0df2202d-5ead-43b2-99f7-84183accf07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697502705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.sram_ctrl_tl_intg_err.697502705
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3033528195
Short name T861
Test name
Test status
Simulation time 21486048 ps
CPU time 0.64 seconds
Started Feb 25 12:32:55 PM PST 24
Finished Feb 25 12:32:56 PM PST 24
Peak memory 202188 kb
Host smart-7509a97a-6301-4f2b-9976-afb2e380daf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033528195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3033528195
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2090550235
Short name T906
Test name
Test status
Simulation time 3931422726 ps
CPU time 62.31 seconds
Started Feb 25 12:33:10 PM PST 24
Finished Feb 25 12:34:14 PM PST 24
Peak memory 202628 kb
Host smart-b9956058-c218-401f-87c7-1f7f99ca62f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090550235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2090550235
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4210073719
Short name T94
Test name
Test status
Simulation time 78735177 ps
CPU time 0.79 seconds
Started Feb 25 12:33:00 PM PST 24
Finished Feb 25 12:33:02 PM PST 24
Peak memory 202212 kb
Host smart-fd62b56d-b85e-46fc-bd1e-ebcf37e11c08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210073719 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.4210073719
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1371608676
Short name T53
Test name
Test status
Simulation time 38958790 ps
CPU time 2.76 seconds
Started Feb 25 12:32:54 PM PST 24
Finished Feb 25 12:32:57 PM PST 24
Peak memory 202500 kb
Host smart-b432c3c3-442b-419a-917b-febe2aa2c179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371608676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.1371608676
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.551796810
Short name T99
Test name
Test status
Simulation time 318231442 ps
CPU time 2.43 seconds
Started Feb 25 12:32:56 PM PST 24
Finished Feb 25 12:32:59 PM PST 24
Peak memory 202432 kb
Host smart-9655730f-7ec5-43da-97ae-ad2f8e4f2780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551796810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.sram_ctrl_tl_intg_err.551796810
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.729272144
Short name T845
Test name
Test status
Simulation time 38749876 ps
CPU time 0.63 seconds
Started Feb 25 12:33:07 PM PST 24
Finished Feb 25 12:33:13 PM PST 24
Peak memory 201896 kb
Host smart-dddce5ac-5b4e-4615-8e46-a505ce9d1812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729272144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_csr_rw.729272144
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2717967444
Short name T69
Test name
Test status
Simulation time 23093103183 ps
CPU time 58.03 seconds
Started Feb 25 12:33:05 PM PST 24
Finished Feb 25 12:34:03 PM PST 24
Peak memory 211100 kb
Host smart-057254d1-b586-4177-a920-9b6be109d3e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717967444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2717967444
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4053821452
Short name T87
Test name
Test status
Simulation time 45414343 ps
CPU time 0.7 seconds
Started Feb 25 12:34:00 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 200052 kb
Host smart-349d4d14-25b7-40cc-9e80-1dbcf22cc0db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053821452 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.4053821452
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3089526780
Short name T905
Test name
Test status
Simulation time 516205516 ps
CPU time 2.42 seconds
Started Feb 25 12:33:04 PM PST 24
Finished Feb 25 12:33:06 PM PST 24
Peak memory 202488 kb
Host smart-2aba968d-68d3-4ee9-ae57-8d44412a3353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089526780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.3089526780
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3037898198
Short name T31
Test name
Test status
Simulation time 385669703 ps
CPU time 2.24 seconds
Started Feb 25 12:33:05 PM PST 24
Finished Feb 25 12:33:07 PM PST 24
Peak memory 202476 kb
Host smart-ea7506fb-a40e-44b9-913e-8a30732de23d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037898198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.3037898198
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.199604125
Short name T876
Test name
Test status
Simulation time 15047832 ps
CPU time 0.64 seconds
Started Feb 25 12:32:58 PM PST 24
Finished Feb 25 12:32:59 PM PST 24
Peak memory 202116 kb
Host smart-fe9a9e04-b13f-455e-b4d4-967274c19e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199604125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_csr_rw.199604125
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3745362283
Short name T883
Test name
Test status
Simulation time 15045317704 ps
CPU time 124.05 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:34:56 PM PST 24
Peak memory 211916 kb
Host smart-46ca81df-9907-4ecd-b32e-3bd8a5538ae0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745362283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3745362283
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2190364763
Short name T881
Test name
Test status
Simulation time 20163814 ps
CPU time 0.7 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 202252 kb
Host smart-e114f155-a66c-4656-93db-afc720fc3499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190364763 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2190364763
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1166125098
Short name T859
Test name
Test status
Simulation time 84239072 ps
CPU time 2.05 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 202496 kb
Host smart-f4ce990b-edff-43e5-a373-0fb936956fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166125098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.1166125098
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.57804128
Short name T74
Test name
Test status
Simulation time 13509482 ps
CPU time 0.62 seconds
Started Feb 25 12:32:46 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 202108 kb
Host smart-00b35c9c-1fb9-4759-9a5d-255f009dbb79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57804128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.sram_ctrl_csr_rw.57804128
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.431918958
Short name T899
Test name
Test status
Simulation time 28402547658 ps
CPU time 65.4 seconds
Started Feb 25 12:32:58 PM PST 24
Finished Feb 25 12:34:04 PM PST 24
Peak memory 202700 kb
Host smart-4e1d4fee-702d-4045-a194-9d0b2c3dc506
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431918958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.431918958
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4239773565
Short name T879
Test name
Test status
Simulation time 21291745 ps
CPU time 0.75 seconds
Started Feb 25 12:33:02 PM PST 24
Finished Feb 25 12:33:04 PM PST 24
Peak memory 202200 kb
Host smart-18475813-b72a-4af0-829f-f57d178ce1b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239773565 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.4239773565
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2297966708
Short name T894
Test name
Test status
Simulation time 43858128 ps
CPU time 3.28 seconds
Started Feb 25 12:33:03 PM PST 24
Finished Feb 25 12:33:07 PM PST 24
Peak memory 211232 kb
Host smart-af576f7d-e716-46fc-94a5-ce50185502be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297966708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.2297966708
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2256139663
Short name T55
Test name
Test status
Simulation time 478400355 ps
CPU time 2.03 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 202436 kb
Host smart-33195d3c-851a-49d4-920d-375959a397b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256139663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.2256139663
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1044896258
Short name T689
Test name
Test status
Simulation time 3988421425 ps
CPU time 136.68 seconds
Started Feb 25 01:18:23 PM PST 24
Finished Feb 25 01:20:39 PM PST 24
Peak memory 309088 kb
Host smart-7aa340d5-b901-4470-b8e3-313ef9a83a51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044896258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1044896258
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1632832126
Short name T640
Test name
Test status
Simulation time 216458016027 ps
CPU time 765.5 seconds
Started Feb 25 01:18:17 PM PST 24
Finished Feb 25 01:31:03 PM PST 24
Peak memory 202472 kb
Host smart-2fd36de5-c7a6-4f14-8be0-ffcacc8ddf58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632832126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1632832126
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2058396948
Short name T452
Test name
Test status
Simulation time 121956153593 ps
CPU time 159.07 seconds
Started Feb 25 01:18:24 PM PST 24
Finished Feb 25 01:21:03 PM PST 24
Peak memory 214196 kb
Host smart-1d02d663-e9c0-4c57-bc38-ba694ac9dfdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058396948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2058396948
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.818962080
Short name T405
Test name
Test status
Simulation time 1468273640 ps
CPU time 45.11 seconds
Started Feb 25 01:18:24 PM PST 24
Finished Feb 25 01:19:09 PM PST 24
Peak memory 260828 kb
Host smart-8924ff2e-69da-4a50-bcbb-fdade388c880
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818962080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.sram_ctrl_max_throughput.818962080
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.640976650
Short name T696
Test name
Test status
Simulation time 953522231 ps
CPU time 68.91 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:19:29 PM PST 24
Peak memory 210908 kb
Host smart-be871897-790d-4283-931c-8e95e6089765
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640976650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.640976650
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2892685054
Short name T221
Test name
Test status
Simulation time 7589889404 ps
CPU time 121.68 seconds
Started Feb 25 01:18:22 PM PST 24
Finished Feb 25 01:20:23 PM PST 24
Peak memory 202740 kb
Host smart-c4af56b7-aaca-4ab4-a8a4-baaeb09be0c1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892685054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2892685054
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.1538001400
Short name T424
Test name
Test status
Simulation time 52220831832 ps
CPU time 662.68 seconds
Started Feb 25 01:18:19 PM PST 24
Finished Feb 25 01:29:21 PM PST 24
Peak memory 370076 kb
Host smart-a81ca953-af51-4d8a-bd84-53b89a18248a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538001400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.1538001400
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.594404848
Short name T473
Test name
Test status
Simulation time 3030646649 ps
CPU time 60.03 seconds
Started Feb 25 01:18:18 PM PST 24
Finished Feb 25 01:19:19 PM PST 24
Peak memory 285144 kb
Host smart-687b7c31-ef7a-4263-9eb7-811e4e1d7b4e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594404848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.594404848
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.268560834
Short name T825
Test name
Test status
Simulation time 7757649707 ps
CPU time 229.41 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:22:09 PM PST 24
Peak memory 202440 kb
Host smart-5b5234a8-fed0-4203-8c6b-10a4c90bd64b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268560834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.sram_ctrl_partial_access_b2b.268560834
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.3206325377
Short name T248
Test name
Test status
Simulation time 4212182309 ps
CPU time 14.02 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:18:34 PM PST 24
Peak memory 202716 kb
Host smart-616b15c1-270b-4727-923e-5ae8d14b2a11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206325377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3206325377
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.1794359796
Short name T294
Test name
Test status
Simulation time 34709569941 ps
CPU time 582.39 seconds
Started Feb 25 01:18:19 PM PST 24
Finished Feb 25 01:28:01 PM PST 24
Peak memory 379268 kb
Host smart-a77c6b17-f037-4a91-bd0b-a4dc06f63811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794359796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1794359796
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2386766730
Short name T300
Test name
Test status
Simulation time 2645003125 ps
CPU time 156.03 seconds
Started Feb 25 01:18:16 PM PST 24
Finished Feb 25 01:20:52 PM PST 24
Peak memory 368944 kb
Host smart-b2c34d52-a412-47ac-b0c6-488f481d4017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386766730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2386766730
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4094753438
Short name T164
Test name
Test status
Simulation time 11605420893 ps
CPU time 257.29 seconds
Started Feb 25 01:18:18 PM PST 24
Finished Feb 25 01:22:36 PM PST 24
Peak memory 202556 kb
Host smart-cc3320a1-826e-407c-9ae2-050006397d9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094753438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.4094753438
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3433239635
Short name T137
Test name
Test status
Simulation time 3065655588 ps
CPU time 30.8 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:18:51 PM PST 24
Peak memory 216316 kb
Host smart-fb797c9e-380c-4b5c-aa29-6726adb8d22b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433239635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3433239635
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2360897844
Short name T472
Test name
Test status
Simulation time 17360885158 ps
CPU time 1347.26 seconds
Started Feb 25 01:18:34 PM PST 24
Finished Feb 25 01:41:01 PM PST 24
Peak memory 376232 kb
Host smart-159a06d3-b092-4376-8d39-8cdb563ef651
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360897844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2360897844
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3677671147
Short name T550
Test name
Test status
Simulation time 50240568 ps
CPU time 0.69 seconds
Started Feb 25 01:18:30 PM PST 24
Finished Feb 25 01:18:30 PM PST 24
Peak memory 202200 kb
Host smart-d9d3a37c-010d-4c70-8e9f-dfe434d4984b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677671147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.3677671147
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.3848639643
Short name T157
Test name
Test status
Simulation time 63606421300 ps
CPU time 2202.04 seconds
Started Feb 25 01:18:34 PM PST 24
Finished Feb 25 01:55:16 PM PST 24
Peak memory 202460 kb
Host smart-762fc10e-625c-48b2-9fb3-045f73084bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848639643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
3848639643
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.1076511735
Short name T476
Test name
Test status
Simulation time 55436077135 ps
CPU time 919.36 seconds
Started Feb 25 01:18:31 PM PST 24
Finished Feb 25 01:33:51 PM PST 24
Peak memory 376204 kb
Host smart-226acc74-a2c2-4e6e-8799-46f5710fc3e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076511735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.1076511735
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.946159705
Short name T544
Test name
Test status
Simulation time 11510878410 ps
CPU time 126.29 seconds
Started Feb 25 01:18:29 PM PST 24
Finished Feb 25 01:20:35 PM PST 24
Peak memory 210636 kb
Host smart-ef3a2e0c-e9b5-4c77-a8fe-3b9894a5025f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946159705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca
lation.946159705
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1752534140
Short name T111
Test name
Test status
Simulation time 715019545 ps
CPU time 35.68 seconds
Started Feb 25 01:18:29 PM PST 24
Finished Feb 25 01:19:04 PM PST 24
Peak memory 243408 kb
Host smart-4b7a88b4-6f51-46d2-9855-f0c1bfb16843
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752534140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1752534140
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2680416978
Short name T537
Test name
Test status
Simulation time 4712641681 ps
CPU time 87.8 seconds
Started Feb 25 01:18:34 PM PST 24
Finished Feb 25 01:20:02 PM PST 24
Peak memory 210760 kb
Host smart-e8c007e5-3f29-4b1a-9c0e-c4ed75df4421
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680416978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.2680416978
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.1731527024
Short name T241
Test name
Test status
Simulation time 29487302295 ps
CPU time 158.54 seconds
Started Feb 25 01:18:36 PM PST 24
Finished Feb 25 01:21:14 PM PST 24
Peak memory 202784 kb
Host smart-c3f78536-0c45-4745-8917-791f3dfb5779
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731527024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.1731527024
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2560031256
Short name T555
Test name
Test status
Simulation time 22208786237 ps
CPU time 564.05 seconds
Started Feb 25 01:18:24 PM PST 24
Finished Feb 25 01:27:48 PM PST 24
Peak memory 374632 kb
Host smart-28e57555-8926-49b6-963a-6a729fc8cb56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560031256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2560031256
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.1602427117
Short name T644
Test name
Test status
Simulation time 886199725 ps
CPU time 14.38 seconds
Started Feb 25 01:18:34 PM PST 24
Finished Feb 25 01:18:49 PM PST 24
Peak memory 202296 kb
Host smart-29e1170c-f666-47d5-922a-2899b44d6d06
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602427117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.1602427117
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4043807299
Short name T438
Test name
Test status
Simulation time 105649708748 ps
CPU time 529.22 seconds
Started Feb 25 01:18:29 PM PST 24
Finished Feb 25 01:27:18 PM PST 24
Peak memory 202416 kb
Host smart-718faf3a-c726-4890-90df-a7571f320164
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043807299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.4043807299
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1250018595
Short name T182
Test name
Test status
Simulation time 708199225 ps
CPU time 14.49 seconds
Started Feb 25 01:18:30 PM PST 24
Finished Feb 25 01:18:45 PM PST 24
Peak memory 202544 kb
Host smart-49f4aceb-3acb-49f3-96db-ae62f45d0faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250018595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1250018595
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3471403274
Short name T478
Test name
Test status
Simulation time 34914139859 ps
CPU time 1063.03 seconds
Started Feb 25 01:18:31 PM PST 24
Finished Feb 25 01:36:14 PM PST 24
Peak memory 370052 kb
Host smart-bd9b1e55-c55f-4961-a26c-d15995e50e4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471403274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3471403274
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3177360687
Short name T25
Test name
Test status
Simulation time 261912973 ps
CPU time 3.28 seconds
Started Feb 25 01:18:27 PM PST 24
Finished Feb 25 01:18:30 PM PST 24
Peak memory 221764 kb
Host smart-320f5189-9527-433c-881e-3145853f9eac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177360687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3177360687
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.2217141340
Short name T281
Test name
Test status
Simulation time 446440334 ps
CPU time 8.64 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:18:29 PM PST 24
Peak memory 202368 kb
Host smart-700f52ad-3c73-4432-914b-b955a7e32886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217141340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2217141340
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1387412338
Short name T505
Test name
Test status
Simulation time 84242677331 ps
CPU time 6616.25 seconds
Started Feb 25 01:18:29 PM PST 24
Finished Feb 25 03:08:46 PM PST 24
Peak memory 380328 kb
Host smart-d0e29bcc-0a4e-45fd-9746-0e0c0154fe3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387412338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1387412338
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2908307274
Short name T92
Test name
Test status
Simulation time 52203512157 ps
CPU time 398.65 seconds
Started Feb 25 01:18:30 PM PST 24
Finished Feb 25 01:25:08 PM PST 24
Peak memory 202432 kb
Host smart-4e7af12c-d827-4c1c-a50f-c43a4f054d79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908307274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2908307274
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.589945983
Short name T450
Test name
Test status
Simulation time 1425396212 ps
CPU time 48.19 seconds
Started Feb 25 01:18:35 PM PST 24
Finished Feb 25 01:19:24 PM PST 24
Peak memory 267792 kb
Host smart-d49fae1e-0d19-470b-8e83-f8d9c67650c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589945983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.589945983
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2908045922
Short name T654
Test name
Test status
Simulation time 53941382440 ps
CPU time 1414.99 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:42:38 PM PST 24
Peak memory 378224 kb
Host smart-deeb61cc-4fb5-4c64-ae02-e683a6094376
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908045922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2908045922
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.2229393443
Short name T711
Test name
Test status
Simulation time 22782290 ps
CPU time 0.65 seconds
Started Feb 25 01:19:22 PM PST 24
Finished Feb 25 01:19:23 PM PST 24
Peak memory 201660 kb
Host smart-67786227-4618-489f-9417-842c70b1088b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229393443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.2229393443
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.1025937298
Short name T625
Test name
Test status
Simulation time 210837185447 ps
CPU time 1064.48 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:36:46 PM PST 24
Peak memory 202428 kb
Host smart-8a8de8bd-4465-4d8d-8f74-aea6c443dd7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025937298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.1025937298
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.3369426164
Short name T589
Test name
Test status
Simulation time 14913876095 ps
CPU time 156.29 seconds
Started Feb 25 01:19:00 PM PST 24
Finished Feb 25 01:21:37 PM PST 24
Peak memory 210564 kb
Host smart-11074511-d31a-4012-86f4-ba051e16ece4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369426164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.3369426164
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3576228283
Short name T719
Test name
Test status
Simulation time 759956593 ps
CPU time 127 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:21:08 PM PST 24
Peak memory 350544 kb
Host smart-df2dd182-5158-41e4-8864-3f29179e32ca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576228283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3576228283
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1355965387
Short name T524
Test name
Test status
Simulation time 18172444068 ps
CPU time 149.62 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:21:31 PM PST 24
Peak memory 218748 kb
Host smart-f848ea75-a853-462c-a63c-360d4ca90335
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355965387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.1355965387
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.3509090083
Short name T479
Test name
Test status
Simulation time 6679182579 ps
CPU time 252.73 seconds
Started Feb 25 01:19:09 PM PST 24
Finished Feb 25 01:23:23 PM PST 24
Peak memory 202404 kb
Host smart-db0f3933-af9f-4e5a-bbc7-490bb6459887
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509090083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.3509090083
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.2666689366
Short name T682
Test name
Test status
Simulation time 5435228750 ps
CPU time 309.58 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:24:11 PM PST 24
Peak memory 368192 kb
Host smart-af636474-662b-4897-bb6b-3d1631a408b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666689366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.2666689366
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2504554330
Short name T421
Test name
Test status
Simulation time 3189626461 ps
CPU time 14.92 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:19:17 PM PST 24
Peak memory 202316 kb
Host smart-93819b78-6b06-4552-9455-52f7c1219c06
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504554330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2504554330
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2609772221
Short name T751
Test name
Test status
Simulation time 5242228079 ps
CPU time 330.71 seconds
Started Feb 25 01:19:09 PM PST 24
Finished Feb 25 01:24:40 PM PST 24
Peak memory 202384 kb
Host smart-5965b8f7-e09b-4051-a717-1c8579ea0e2f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609772221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2609772221
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.2681241233
Short name T252
Test name
Test status
Simulation time 348331245 ps
CPU time 13.23 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:19:17 PM PST 24
Peak memory 202640 kb
Host smart-22881635-5e13-428c-8797-4b26004cb927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681241233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2681241233
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1208020185
Short name T570
Test name
Test status
Simulation time 14475647377 ps
CPU time 388.93 seconds
Started Feb 25 01:19:00 PM PST 24
Finished Feb 25 01:25:29 PM PST 24
Peak memory 377276 kb
Host smart-1d05376f-2de0-485f-b8b5-6956579e428e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208020185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1208020185
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.2890653237
Short name T669
Test name
Test status
Simulation time 788621367 ps
CPU time 29.04 seconds
Started Feb 25 01:19:09 PM PST 24
Finished Feb 25 01:19:39 PM PST 24
Peak memory 267736 kb
Host smart-9425357e-8f65-4531-b12c-cc437957819d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890653237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2890653237
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3229060642
Short name T146
Test name
Test status
Simulation time 4167775476 ps
CPU time 285.28 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:23:47 PM PST 24
Peak memory 210648 kb
Host smart-99a3ee4d-a298-456b-bc41-79f2055d261c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229060642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.3229060642
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2916986745
Short name T140
Test name
Test status
Simulation time 4170856284 ps
CPU time 30.04 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:19:31 PM PST 24
Peak memory 210596 kb
Host smart-f7c4d1a3-2f4f-4b1e-92b5-7488dc59ecb7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916986745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2916986745
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2914638503
Short name T675
Test name
Test status
Simulation time 16533982434 ps
CPU time 567.4 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:28:30 PM PST 24
Peak memory 378268 kb
Host smart-a53f25f5-4324-4851-b055-fb9d30537ea6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914638503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.2914638503
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.654988931
Short name T26
Test name
Test status
Simulation time 22462701 ps
CPU time 0.65 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:19:02 PM PST 24
Peak memory 201932 kb
Host smart-ac3202ff-0431-4b17-bba6-a45908222bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654988931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.654988931
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.3013905795
Short name T477
Test name
Test status
Simulation time 55950386745 ps
CPU time 907.66 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:34:12 PM PST 24
Peak memory 202488 kb
Host smart-dfe5e986-9805-4cd6-a597-b5faa5158685
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013905795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.3013905795
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.3773987366
Short name T744
Test name
Test status
Simulation time 20568784718 ps
CPU time 108.36 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:20:50 PM PST 24
Peak memory 210604 kb
Host smart-00d02162-2d48-4d4c-a3ea-195aea57c3c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773987366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.3773987366
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.4142585605
Short name T796
Test name
Test status
Simulation time 800660590 ps
CPU time 150.79 seconds
Started Feb 25 01:19:21 PM PST 24
Finished Feb 25 01:21:52 PM PST 24
Peak memory 366824 kb
Host smart-08c85869-9663-40e6-ba99-017332b1fbe5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142585605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.4142585605
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4211740597
Short name T284
Test name
Test status
Simulation time 7462496880 ps
CPU time 141.77 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:21:23 PM PST 24
Peak memory 214772 kb
Host smart-f2a69891-294d-41f0-9abd-cf9c133eee34
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211740597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.4211740597
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.510671249
Short name T738
Test name
Test status
Simulation time 2062118163 ps
CPU time 124.52 seconds
Started Feb 25 01:19:22 PM PST 24
Finished Feb 25 01:21:27 PM PST 24
Peak memory 201788 kb
Host smart-08930859-31dc-435c-89cb-5bf06994b9b5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510671249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.510671249
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.3762894011
Short name T687
Test name
Test status
Simulation time 132393002557 ps
CPU time 2387.16 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:58:48 PM PST 24
Peak memory 379312 kb
Host smart-dc9e4bbd-24b3-4a0f-ba74-4eaaaed84416
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762894011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.3762894011
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.900431121
Short name T445
Test name
Test status
Simulation time 1910018418 ps
CPU time 40.58 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:19:45 PM PST 24
Peak memory 290492 kb
Host smart-ed95883d-0e1e-4a71-92b5-0ac084db79ee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900431121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s
ram_ctrl_partial_access.900431121
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1254488948
Short name T350
Test name
Test status
Simulation time 25603989329 ps
CPU time 378.92 seconds
Started Feb 25 01:19:22 PM PST 24
Finished Feb 25 01:25:42 PM PST 24
Peak memory 202344 kb
Host smart-0a19ab8f-65c7-48aa-bd44-99ceff53c6dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254488948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.1254488948
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.2314435427
Short name T122
Test name
Test status
Simulation time 599040698 ps
CPU time 13.89 seconds
Started Feb 25 01:19:22 PM PST 24
Finished Feb 25 01:19:36 PM PST 24
Peak memory 202544 kb
Host smart-a93345db-d22b-4afb-8ac1-223b67f66c7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314435427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2314435427
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.4168124824
Short name T770
Test name
Test status
Simulation time 1260840675 ps
CPU time 154.47 seconds
Started Feb 25 01:19:21 PM PST 24
Finished Feb 25 01:21:56 PM PST 24
Peak memory 361036 kb
Host smart-cc267e58-c7f9-4aa2-9cb2-6d1328a4febc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168124824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.4168124824
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.994251174
Short name T356
Test name
Test status
Simulation time 3493138937 ps
CPU time 15.43 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:19:17 PM PST 24
Peak memory 202404 kb
Host smart-55da3355-736e-4843-928c-1bc4a99086d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994251174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.994251174
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.1801324045
Short name T416
Test name
Test status
Simulation time 586866016281 ps
CPU time 3870.7 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 02:23:33 PM PST 24
Peak memory 379284 kb
Host smart-fb7cc9a6-7eda-4584-a27f-db46263c8633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801324045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.1801324045
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3934353191
Short name T632
Test name
Test status
Simulation time 3675598694 ps
CPU time 230.02 seconds
Started Feb 25 01:19:03 PM PST 24
Finished Feb 25 01:22:53 PM PST 24
Peak memory 202384 kb
Host smart-2ccfc414-ee32-4165-9cbe-d0818de9a90a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934353191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.3934353191
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1103810921
Short name T752
Test name
Test status
Simulation time 8274427435 ps
CPU time 90.11 seconds
Started Feb 25 01:19:22 PM PST 24
Finished Feb 25 01:20:53 PM PST 24
Peak memory 315848 kb
Host smart-455952ce-d9e3-4c57-810d-ca72f026276d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103810921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1103810921
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.376192660
Short name T278
Test name
Test status
Simulation time 4579159847 ps
CPU time 67.98 seconds
Started Feb 25 01:19:20 PM PST 24
Finished Feb 25 01:20:29 PM PST 24
Peak memory 263288 kb
Host smart-ea09018c-1621-4bb9-9533-33249318a40f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376192660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_access_during_key_req.376192660
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.2602493932
Short name T395
Test name
Test status
Simulation time 34639155 ps
CPU time 0.62 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:19:18 PM PST 24
Peak memory 202148 kb
Host smart-924e84eb-f2b8-4c1d-b48f-b3b2922f63a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602493932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.2602493932
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.458623624
Short name T45
Test name
Test status
Simulation time 31812798936 ps
CPU time 2125.95 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:54:30 PM PST 24
Peak memory 202512 kb
Host smart-ae5043bf-61d0-40d5-b47d-c30d888e5912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458623624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.
458623624
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.1279249971
Short name T235
Test name
Test status
Simulation time 28952781453 ps
CPU time 91.72 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:20:51 PM PST 24
Peak memory 210516 kb
Host smart-12308230-f9a6-4853-98bb-160a22eff29a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279249971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.1279249971
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.3851539710
Short name T218
Test name
Test status
Simulation time 704737673 ps
CPU time 42.79 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:20:01 PM PST 24
Peak memory 253016 kb
Host smart-2f85b705-a403-4797-89fe-ebd2a32007aa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851539710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.3851539710
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1407779287
Short name T413
Test name
Test status
Simulation time 6199551436 ps
CPU time 150.45 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:21:48 PM PST 24
Peak memory 211472 kb
Host smart-db3a957e-b0b0-4e80-be21-965682b406c5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407779287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.1407779287
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.2466909694
Short name T269
Test name
Test status
Simulation time 4109810279 ps
CPU time 238.49 seconds
Started Feb 25 01:19:20 PM PST 24
Finished Feb 25 01:23:19 PM PST 24
Peak memory 202244 kb
Host smart-8552f8f7-9c72-4a86-ab51-b7d61887167e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466909694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.2466909694
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.994120618
Short name T816
Test name
Test status
Simulation time 20436286575 ps
CPU time 1293 seconds
Started Feb 25 01:18:59 PM PST 24
Finished Feb 25 01:40:32 PM PST 24
Peak memory 380324 kb
Host smart-f6a2fdc4-38d9-4624-a197-b0a395d05bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994120618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multip
le_keys.994120618
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.366525672
Short name T802
Test name
Test status
Simulation time 4975592350 ps
CPU time 21.25 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:19:39 PM PST 24
Peak memory 202344 kb
Host smart-6fce556c-ced1-4766-af32-d38665179bdb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366525672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.s
ram_ctrl_partial_access.366525672
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3428510942
Short name T681
Test name
Test status
Simulation time 3692786570 ps
CPU time 243.06 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:23:23 PM PST 24
Peak memory 202396 kb
Host smart-ef839bac-593a-4bbc-a5d6-a2befa6c7ac3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428510942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.3428510942
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.1779842170
Short name T173
Test name
Test status
Simulation time 2099109904 ps
CPU time 13.81 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:19:33 PM PST 24
Peak memory 202592 kb
Host smart-5153f01d-f756-41fc-993f-7361a546498c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779842170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1779842170
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.3169799198
Short name T605
Test name
Test status
Simulation time 4655999014 ps
CPU time 352.06 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:25:10 PM PST 24
Peak memory 370592 kb
Host smart-311c69ae-9c85-4e29-8a20-7b45a9eb306a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169799198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3169799198
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.71117341
Short name T318
Test name
Test status
Simulation time 1461614508 ps
CPU time 30.06 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:19:31 PM PST 24
Peak memory 202360 kb
Host smart-b7e5eadf-3da2-4637-93fe-9dbf1d01a857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71117341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.71117341
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.213679558
Short name T197
Test name
Test status
Simulation time 169547438406 ps
CPU time 1728.99 seconds
Started Feb 25 01:19:22 PM PST 24
Finished Feb 25 01:48:12 PM PST 24
Peak memory 380120 kb
Host smart-38a4bde5-d8ff-4df3-9fd7-da96cb6f73ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213679558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_stress_all.213679558
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.805049988
Short name T364
Test name
Test status
Simulation time 3293043855 ps
CPU time 234.73 seconds
Started Feb 25 01:19:21 PM PST 24
Finished Feb 25 01:23:16 PM PST 24
Peak memory 202444 kb
Host smart-43c929f7-7246-4b73-b914-1b0c4553b73b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805049988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_stress_pipeline.805049988
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1650141517
Short name T702
Test name
Test status
Simulation time 1442429775 ps
CPU time 30.61 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:19:50 PM PST 24
Peak memory 226840 kb
Host smart-80fe55f4-44fa-4c6f-aeb3-e12c07de2903
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650141517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1650141517
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1201315617
Short name T745
Test name
Test status
Simulation time 6431280471 ps
CPU time 69.79 seconds
Started Feb 25 01:19:45 PM PST 24
Finished Feb 25 01:20:55 PM PST 24
Peak memory 202360 kb
Host smart-1d7df417-9740-42e0-9aa0-f6f430746791
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201315617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.1201315617
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.3019996628
Short name T655
Test name
Test status
Simulation time 14461142 ps
CPU time 0.69 seconds
Started Feb 25 01:19:46 PM PST 24
Finished Feb 25 01:19:47 PM PST 24
Peak memory 202192 kb
Host smart-79cc0f88-409e-450b-a5f8-38d75b7c5588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019996628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.3019996628
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.3946755246
Short name T715
Test name
Test status
Simulation time 258994534648 ps
CPU time 2033.05 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:53:11 PM PST 24
Peak memory 202468 kb
Host smart-f06f93f7-856b-44b0-a9e8-911e66a484d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946755246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.3946755246
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.1477976788
Short name T750
Test name
Test status
Simulation time 2183220240 ps
CPU time 17.36 seconds
Started Feb 25 01:19:21 PM PST 24
Finished Feb 25 01:19:38 PM PST 24
Peak memory 210516 kb
Host smart-c4a8b449-2a00-49a5-be2d-017fb3d3b83f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477976788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.1477976788
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.11866469
Short name T217
Test name
Test status
Simulation time 1487924064 ps
CPU time 89.2 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:20:47 PM PST 24
Peak memory 324636 kb
Host smart-9e49eaab-ced5-45dc-97eb-d4b6727c29b0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11866469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_max_throughput.11866469
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1587811605
Short name T522
Test name
Test status
Simulation time 3259266966 ps
CPU time 72.01 seconds
Started Feb 25 01:19:23 PM PST 24
Finished Feb 25 01:20:35 PM PST 24
Peak memory 211004 kb
Host smart-66b00339-b984-44ae-94f3-ea0efb5b2d14
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587811605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.1587811605
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.3314336658
Short name T482
Test name
Test status
Simulation time 10774532221 ps
CPU time 143.98 seconds
Started Feb 25 01:19:35 PM PST 24
Finished Feb 25 01:21:59 PM PST 24
Peak memory 202448 kb
Host smart-a4af4f13-7f1e-43d4-93df-3ec134f9b4f8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314336658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.3314336658
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.1949205475
Short name T310
Test name
Test status
Simulation time 39283590838 ps
CPU time 1273.91 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:40:33 PM PST 24
Peak memory 379640 kb
Host smart-b67024fe-f0e2-4705-ad85-f66c00cacc68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949205475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.1949205475
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.3833828103
Short name T624
Test name
Test status
Simulation time 545903258 ps
CPU time 6.81 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:19:25 PM PST 24
Peak memory 202296 kb
Host smart-26d4ddfb-69b4-4263-a2a8-82e6f3f23f79
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833828103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.3833828103
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2359676370
Short name T600
Test name
Test status
Simulation time 6754009158 ps
CPU time 405.69 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:26:05 PM PST 24
Peak memory 202428 kb
Host smart-168de840-e1d9-4656-b529-6c506792f509
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359676370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.2359676370
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.3012712803
Short name T328
Test name
Test status
Simulation time 887603312 ps
CPU time 7 seconds
Started Feb 25 01:19:29 PM PST 24
Finished Feb 25 01:19:37 PM PST 24
Peak memory 202508 kb
Host smart-e4e95af1-b720-4f25-a6b2-6b3968fff84e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012712803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3012712803
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.3958793854
Short name T596
Test name
Test status
Simulation time 16248385535 ps
CPU time 1346.59 seconds
Started Feb 25 01:19:44 PM PST 24
Finished Feb 25 01:42:11 PM PST 24
Peak memory 378444 kb
Host smart-0f5a1b8e-dd86-4266-b6ff-fa5a385deabc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958793854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3958793854
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1349490475
Short name T792
Test name
Test status
Simulation time 7804876171 ps
CPU time 23.69 seconds
Started Feb 25 01:19:18 PM PST 24
Finished Feb 25 01:19:42 PM PST 24
Peak memory 202396 kb
Host smart-813f7336-e89a-4ad0-94b3-5126da0e3fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349490475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1349490475
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.2812127741
Short name T535
Test name
Test status
Simulation time 124634727307 ps
CPU time 4304.24 seconds
Started Feb 25 01:19:31 PM PST 24
Finished Feb 25 02:31:16 PM PST 24
Peak memory 381332 kb
Host smart-2d28a527-2522-4575-a0b6-f3f099b06962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812127741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.2812127741
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.315806119
Short name T148
Test name
Test status
Simulation time 9324399715 ps
CPU time 180.59 seconds
Started Feb 25 01:19:14 PM PST 24
Finished Feb 25 01:22:15 PM PST 24
Peak memory 202424 kb
Host smart-b2959476-1b13-4d26-b8f4-61a1c3e6e8d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315806119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_stress_pipeline.315806119
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2708142138
Short name T381
Test name
Test status
Simulation time 775649930 ps
CPU time 108.27 seconds
Started Feb 25 01:19:21 PM PST 24
Finished Feb 25 01:21:10 PM PST 24
Peak memory 333264 kb
Host smart-940b32b6-c281-4e6d-a450-cbe44531370e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708142138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2708142138
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2569960296
Short name T534
Test name
Test status
Simulation time 15718350 ps
CPU time 0.68 seconds
Started Feb 25 01:19:56 PM PST 24
Finished Feb 25 01:19:57 PM PST 24
Peak memory 202224 kb
Host smart-3356a8ad-542b-4733-81a1-4aa3eec93078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569960296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2569960296
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.1230313861
Short name T220
Test name
Test status
Simulation time 82913497455 ps
CPU time 888.49 seconds
Started Feb 25 01:19:20 PM PST 24
Finished Feb 25 01:34:09 PM PST 24
Peak memory 202612 kb
Host smart-65d0a7a7-2eb4-45ed-8796-0b77b3cb8976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230313861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.1230313861
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.3136986203
Short name T653
Test name
Test status
Simulation time 10740842064 ps
CPU time 119.53 seconds
Started Feb 25 01:19:37 PM PST 24
Finished Feb 25 01:21:37 PM PST 24
Peak memory 202480 kb
Host smart-f2ad356a-2296-4197-9177-c8338a5a1a32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136986203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.3136986203
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.3481278027
Short name T225
Test name
Test status
Simulation time 1069732229 ps
CPU time 46.3 seconds
Started Feb 25 01:19:44 PM PST 24
Finished Feb 25 01:20:30 PM PST 24
Peak memory 261700 kb
Host smart-e2a3cd37-946c-4348-8452-bb76163ae139
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481278027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.3481278027
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.931697316
Short name T404
Test name
Test status
Simulation time 19053574939 ps
CPU time 153.8 seconds
Started Feb 25 01:19:39 PM PST 24
Finished Feb 25 01:22:13 PM PST 24
Peak memory 215044 kb
Host smart-9567a379-dfa0-4921-a0ce-3a2b9353f9c0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931697316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_mem_partial_access.931697316
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.3913420734
Short name T829
Test name
Test status
Simulation time 8229107705 ps
CPU time 122.91 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:22:04 PM PST 24
Peak memory 202372 kb
Host smart-cc5ba1b1-d801-41aa-9381-f3b48672663d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913420734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.3913420734
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.1445828607
Short name T427
Test name
Test status
Simulation time 14757833900 ps
CPU time 772.64 seconds
Started Feb 25 01:19:22 PM PST 24
Finished Feb 25 01:32:16 PM PST 24
Peak memory 379236 kb
Host smart-4496d8ee-ff2c-456b-8531-abbeafc7d907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445828607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.1445828607
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.1635744925
Short name T559
Test name
Test status
Simulation time 1140037121 ps
CPU time 82.38 seconds
Started Feb 25 01:19:38 PM PST 24
Finished Feb 25 01:21:01 PM PST 24
Peak memory 313644 kb
Host smart-65c357f6-e095-4193-9527-38d8ee50f065
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635744925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.1635744925
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3596950433
Short name T471
Test name
Test status
Simulation time 21424421903 ps
CPU time 480.41 seconds
Started Feb 25 01:19:43 PM PST 24
Finished Feb 25 01:27:44 PM PST 24
Peak memory 202400 kb
Host smart-1f16a5e5-6ac1-4aa8-b889-3d5bfe117a60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596950433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3596950433
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.1956687775
Short name T444
Test name
Test status
Simulation time 1342875592 ps
CPU time 5.93 seconds
Started Feb 25 01:19:19 PM PST 24
Finished Feb 25 01:19:25 PM PST 24
Peak memory 202588 kb
Host smart-f78ae2a7-710e-4ce0-ab6f-4e5e26ec7167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956687775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1956687775
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.128261837
Short name T588
Test name
Test status
Simulation time 543871367 ps
CPU time 26.37 seconds
Started Feb 25 01:19:29 PM PST 24
Finished Feb 25 01:19:56 PM PST 24
Peak memory 208612 kb
Host smart-ff2e37b6-46e3-445f-93e0-4e4607325a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128261837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.128261837
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.1864202080
Short name T527
Test name
Test status
Simulation time 507741805 ps
CPU time 18.04 seconds
Started Feb 25 01:19:29 PM PST 24
Finished Feb 25 01:19:48 PM PST 24
Peak memory 202372 kb
Host smart-de043da6-c81f-4037-86f8-8002f33ff648
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864202080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1864202080
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.426954695
Short name T105
Test name
Test status
Simulation time 59292147694 ps
CPU time 1721.4 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:48:42 PM PST 24
Peak memory 380540 kb
Host smart-63fd781b-8ec2-43ee-a116-01aa3c43498c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426954695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_stress_all.426954695
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.837531021
Short name T706
Test name
Test status
Simulation time 13795470962 ps
CPU time 294.92 seconds
Started Feb 25 01:19:38 PM PST 24
Finished Feb 25 01:24:34 PM PST 24
Peak memory 202408 kb
Host smart-68d8b4d3-89ee-4ece-a5ff-a9353ff6044e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837531021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_stress_pipeline.837531021
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3124160009
Short name T724
Test name
Test status
Simulation time 2447527137 ps
CPU time 30.86 seconds
Started Feb 25 01:19:32 PM PST 24
Finished Feb 25 01:20:03 PM PST 24
Peak memory 223940 kb
Host smart-bc24d3ad-8f50-4571-9a7f-9c3fda869a8b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124160009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3124160009
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3719320171
Short name T283
Test name
Test status
Simulation time 5729545794 ps
CPU time 896.8 seconds
Started Feb 25 01:19:34 PM PST 24
Finished Feb 25 01:34:31 PM PST 24
Peak memory 368840 kb
Host smart-5d647624-39fb-446e-84ae-80823dbf474b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719320171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3719320171
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.3153454093
Short name T379
Test name
Test status
Simulation time 32297426 ps
CPU time 0.63 seconds
Started Feb 25 01:19:39 PM PST 24
Finished Feb 25 01:19:40 PM PST 24
Peak memory 201880 kb
Host smart-0dd31c19-3c1c-4e3a-9772-9fa532542a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153454093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.3153454093
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.2618828462
Short name T645
Test name
Test status
Simulation time 32781765022 ps
CPU time 768.41 seconds
Started Feb 25 01:19:37 PM PST 24
Finished Feb 25 01:32:25 PM PST 24
Peak memory 202420 kb
Host smart-1c41656b-55f5-44c8-9dbd-952558113be7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618828462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.2618828462
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.867876513
Short name T159
Test name
Test status
Simulation time 55223598974 ps
CPU time 349.1 seconds
Started Feb 25 01:19:40 PM PST 24
Finished Feb 25 01:25:29 PM PST 24
Peak memory 210680 kb
Host smart-0e3a5302-a17d-4f64-8727-1d642fe29f47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867876513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esc
alation.867876513
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.448651454
Short name T685
Test name
Test status
Simulation time 2664700232 ps
CPU time 26.57 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:20:13 PM PST 24
Peak memory 210684 kb
Host smart-77129caa-b765-4d39-9aa1-f25483938d42
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448651454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.sram_ctrl_max_throughput.448651454
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3799657098
Short name T77
Test name
Test status
Simulation time 5298631109 ps
CPU time 166.05 seconds
Started Feb 25 01:19:49 PM PST 24
Finished Feb 25 01:22:35 PM PST 24
Peak memory 214960 kb
Host smart-aabbca58-d1cc-4e33-aafd-92fa6ae8062e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799657098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3799657098
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.3568755935
Short name T399
Test name
Test status
Simulation time 2062904260 ps
CPU time 117.08 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:21:45 PM PST 24
Peak memory 202320 kb
Host smart-08077e03-b0ff-4eef-bdab-4a70abb4f6d6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568755935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.3568755935
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.1538492416
Short name T440
Test name
Test status
Simulation time 59723595458 ps
CPU time 668.84 seconds
Started Feb 25 01:19:44 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 372988 kb
Host smart-9d92c04c-74b9-421b-9d22-d345547c4094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538492416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.1538492416
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.1622787589
Short name T766
Test name
Test status
Simulation time 1076924477 ps
CPU time 20.97 seconds
Started Feb 25 01:19:40 PM PST 24
Finished Feb 25 01:20:01 PM PST 24
Peak memory 250568 kb
Host smart-ba104296-d6a6-4a83-988c-b5ac67d54ae3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622787589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.1622787589
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1692639238
Short name T179
Test name
Test status
Simulation time 16750666795 ps
CPU time 191.3 seconds
Started Feb 25 01:20:03 PM PST 24
Finished Feb 25 01:23:15 PM PST 24
Peak memory 202420 kb
Host smart-29879036-b746-4fa8-8530-0790821270c4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692639238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.1692639238
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.2102947485
Short name T34
Test name
Test status
Simulation time 455810914 ps
CPU time 6.58 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:19:54 PM PST 24
Peak memory 202588 kb
Host smart-8807e026-bdaf-4c60-9cd3-b54d0cfc7180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102947485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2102947485
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.3800807835
Short name T498
Test name
Test status
Simulation time 11320408834 ps
CPU time 793.44 seconds
Started Feb 25 01:19:55 PM PST 24
Finished Feb 25 01:33:08 PM PST 24
Peak memory 369920 kb
Host smart-b4b193af-bef3-43c8-8b59-27944ba0922a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800807835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3800807835
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.481675
Short name T714
Test name
Test status
Simulation time 1830404212 ps
CPU time 110.85 seconds
Started Feb 25 01:19:52 PM PST 24
Finished Feb 25 01:21:43 PM PST 24
Peak memory 343416 kb
Host smart-4046da6b-0aa1-49b7-ae2c-dd2ecab7d299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.481675
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1626340800
Short name T130
Test name
Test status
Simulation time 3745098480 ps
CPU time 286.5 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:24:34 PM PST 24
Peak memory 202424 kb
Host smart-0fa0ad9e-9e4e-4804-a017-0dd3ed3ca836
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626340800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.1626340800
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2610875164
Short name T638
Test name
Test status
Simulation time 8480711239 ps
CPU time 32.32 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:20:19 PM PST 24
Peak memory 225944 kb
Host smart-686e66a4-7961-4088-ba58-875f37420bf9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610875164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2610875164
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2067933046
Short name T385
Test name
Test status
Simulation time 10273247533 ps
CPU time 1879.78 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:51:07 PM PST 24
Peak memory 379280 kb
Host smart-93a2e65e-0610-4ebb-8a0c-561250aed685
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067933046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.2067933046
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.507533486
Short name T822
Test name
Test status
Simulation time 37182580 ps
CPU time 0.61 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:20:01 PM PST 24
Peak memory 201836 kb
Host smart-da2eefd6-f76f-4703-b156-bc6b3d79a101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507533486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.507533486
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.4141775083
Short name T660
Test name
Test status
Simulation time 312956023293 ps
CPU time 1792.67 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:49:53 PM PST 24
Peak memory 202388 kb
Host smart-7ed32835-3ae2-4ed2-99d6-5810a288cdff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141775083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.4141775083
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.261755153
Short name T388
Test name
Test status
Simulation time 10645907138 ps
CPU time 56.04 seconds
Started Feb 25 01:19:38 PM PST 24
Finished Feb 25 01:20:34 PM PST 24
Peak memory 210564 kb
Host smart-1dc31694-7379-4320-bf6f-35005379c076
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261755153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc
alation.261755153
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1426480440
Short name T562
Test name
Test status
Simulation time 5992613859 ps
CPU time 66.3 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:20:54 PM PST 24
Peak memory 292880 kb
Host smart-64d6f768-927a-4704-885e-106725f383d1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426480440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1426480440
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3996448450
Short name T192
Test name
Test status
Simulation time 2624641628 ps
CPU time 70.19 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:20:58 PM PST 24
Peak memory 211560 kb
Host smart-b8f029f3-2ea8-412f-bad3-fb36ec919e2d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996448450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.3996448450
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.1414053828
Short name T143
Test name
Test status
Simulation time 14099130993 ps
CPU time 140.72 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:22:09 PM PST 24
Peak memory 202604 kb
Host smart-e5c4fa76-514a-4f66-9d21-a30f54d6cee1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414053828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.1414053828
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.3550093952
Short name T400
Test name
Test status
Simulation time 16677261240 ps
CPU time 822.13 seconds
Started Feb 25 01:19:38 PM PST 24
Finished Feb 25 01:33:20 PM PST 24
Peak memory 369060 kb
Host smart-b9635530-65e9-420c-be23-6ee265c12a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550093952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.3550093952
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2387730052
Short name T12
Test name
Test status
Simulation time 925810133 ps
CPU time 13.61 seconds
Started Feb 25 01:19:40 PM PST 24
Finished Feb 25 01:19:53 PM PST 24
Peak memory 209352 kb
Host smart-bd0a7728-b5d4-4d28-88b1-1a5aa612869f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387730052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2387730052
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.174671030
Short name T339
Test name
Test status
Simulation time 40446209409 ps
CPU time 344.12 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:25:32 PM PST 24
Peak memory 202336 kb
Host smart-502ef6bc-6255-4e75-85eb-a6cb969722c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174671030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.sram_ctrl_partial_access_b2b.174671030
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3187828933
Short name T783
Test name
Test status
Simulation time 347345015 ps
CPU time 6.09 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:19:54 PM PST 24
Peak memory 202564 kb
Host smart-d0c5c926-656c-444a-bcf6-558ad52397ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187828933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3187828933
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.851475745
Short name T630
Test name
Test status
Simulation time 13667167250 ps
CPU time 1168.95 seconds
Started Feb 25 01:19:49 PM PST 24
Finished Feb 25 01:39:18 PM PST 24
Peak memory 378312 kb
Host smart-296dab68-4390-4bbb-9320-91aa17c3ac8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851475745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.851475745
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.2780540289
Short name T264
Test name
Test status
Simulation time 5198698248 ps
CPU time 126.47 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:21:54 PM PST 24
Peak memory 351680 kb
Host smart-1170d9bd-af70-47b6-b463-4238fafdd780
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780540289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2780540289
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.4263187469
Short name T491
Test name
Test status
Simulation time 6288807112 ps
CPU time 461.62 seconds
Started Feb 25 01:19:46 PM PST 24
Finished Feb 25 01:27:28 PM PST 24
Peak memory 202368 kb
Host smart-14874756-79d0-4862-9c6e-4b87769c3b97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263187469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.4263187469
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2323838386
Short name T499
Test name
Test status
Simulation time 2836137252 ps
CPU time 28.88 seconds
Started Feb 25 01:19:56 PM PST 24
Finished Feb 25 01:20:25 PM PST 24
Peak memory 223540 kb
Host smart-1fbe3086-dc3b-44da-87df-13d02fb59012
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323838386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2323838386
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.4100083224
Short name T21
Test name
Test status
Simulation time 19844461587 ps
CPU time 926.5 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:35:14 PM PST 24
Peak memory 376256 kb
Host smart-5b3cbf9a-f89e-43a9-8227-bdb61f88e3ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100083224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.4100083224
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.2835090488
Short name T633
Test name
Test status
Simulation time 11666956 ps
CPU time 0.7 seconds
Started Feb 25 01:19:49 PM PST 24
Finished Feb 25 01:19:50 PM PST 24
Peak memory 201888 kb
Host smart-5ab9fa6e-6f6e-4def-9a81-223b2968ff2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835090488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.2835090488
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.3482657888
Short name T789
Test name
Test status
Simulation time 523363981477 ps
CPU time 2285.97 seconds
Started Feb 25 01:19:53 PM PST 24
Finished Feb 25 01:57:59 PM PST 24
Peak memory 210592 kb
Host smart-5da74ce6-2b30-44a3-b2cf-ad825101058d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482657888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.3482657888
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.1823619339
Short name T196
Test name
Test status
Simulation time 3774266848 ps
CPU time 38.12 seconds
Started Feb 25 01:19:51 PM PST 24
Finished Feb 25 01:20:29 PM PST 24
Peak memory 210560 kb
Host smart-dc3decc2-5841-410c-9f8a-1b998b6e5c99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823619339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.1823619339
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.1378454109
Short name T784
Test name
Test status
Simulation time 1515901752 ps
CPU time 65.17 seconds
Started Feb 25 01:19:51 PM PST 24
Finished Feb 25 01:20:56 PM PST 24
Peak memory 301564 kb
Host smart-f56ab20b-9abe-44a9-8f47-04f5bab987b8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378454109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.1378454109
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.543463156
Short name T725
Test name
Test status
Simulation time 25508346861 ps
CPU time 160.74 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:22:28 PM PST 24
Peak memory 210844 kb
Host smart-3fd7fb77-6bb5-4785-8477-c6f2698f568e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543463156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.543463156
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2869663924
Short name T358
Test name
Test status
Simulation time 15758834747 ps
CPU time 252.04 seconds
Started Feb 25 01:19:58 PM PST 24
Finished Feb 25 01:24:10 PM PST 24
Peak memory 202484 kb
Host smart-e278c2df-ab50-4469-81bc-46339fcc1c07
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869663924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2869663924
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.643698217
Short name T167
Test name
Test status
Simulation time 8811319910 ps
CPU time 437.89 seconds
Started Feb 25 01:19:47 PM PST 24
Finished Feb 25 01:27:05 PM PST 24
Peak memory 339580 kb
Host smart-f8fd466e-0571-4ce9-b320-ca537aa3e892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643698217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip
le_keys.643698217
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.3855316626
Short name T135
Test name
Test status
Simulation time 969947436 ps
CPU time 51.85 seconds
Started Feb 25 01:19:52 PM PST 24
Finished Feb 25 01:20:44 PM PST 24
Peak memory 307344 kb
Host smart-68126880-fe39-4ba4-9031-16e97bb94f90
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855316626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.3855316626
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2944434624
Short name T187
Test name
Test status
Simulation time 35918829569 ps
CPU time 362.57 seconds
Started Feb 25 01:19:55 PM PST 24
Finished Feb 25 01:25:57 PM PST 24
Peak memory 202432 kb
Host smart-c045a381-593e-4b1f-ba52-dd78dd6f4d26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944434624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2944434624
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.189016619
Short name T677
Test name
Test status
Simulation time 693289242 ps
CPU time 5.78 seconds
Started Feb 25 01:19:59 PM PST 24
Finished Feb 25 01:20:05 PM PST 24
Peak memory 202500 kb
Host smart-62093b6c-5830-446e-a759-16b9dc879dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189016619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.189016619
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.1637513686
Short name T720
Test name
Test status
Simulation time 39776920390 ps
CPU time 1140.09 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:38:48 PM PST 24
Peak memory 364980 kb
Host smart-b45b363d-2446-4fcf-815e-67e9a9f3dfaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637513686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1637513686
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.4230425359
Short name T610
Test name
Test status
Simulation time 2392909357 ps
CPU time 28.47 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:20:17 PM PST 24
Peak memory 203476 kb
Host smart-1a9a6e54-ca97-4668-8c52-8449ab6b119a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230425359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4230425359
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.970716072
Short name T103
Test name
Test status
Simulation time 106159979703 ps
CPU time 3797.84 seconds
Started Feb 25 01:19:54 PM PST 24
Finished Feb 25 02:23:13 PM PST 24
Peak memory 380368 kb
Host smart-10b7ff37-84cd-4e63-b0c2-67ee4e200ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970716072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_stress_all.970716072
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.646115278
Short name T759
Test name
Test status
Simulation time 3898031554 ps
CPU time 301.19 seconds
Started Feb 25 01:19:50 PM PST 24
Finished Feb 25 01:24:52 PM PST 24
Peak memory 202384 kb
Host smart-91454a1e-c2a0-4f25-a6af-ee29f4850fe5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646115278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_stress_pipeline.646115278
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4056202503
Short name T708
Test name
Test status
Simulation time 2706716732 ps
CPU time 40.42 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:20:29 PM PST 24
Peak memory 253808 kb
Host smart-69172496-73d6-4ee6-84db-266f3caa22bd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056202503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.4056202503
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2382236619
Short name T837
Test name
Test status
Simulation time 17642087647 ps
CPU time 618.05 seconds
Started Feb 25 01:19:54 PM PST 24
Finished Feb 25 01:30:12 PM PST 24
Peak memory 374796 kb
Host smart-4593de8a-0ea6-4d7d-a237-18ffb5f27035
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382236619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.2382236619
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.1112863783
Short name T349
Test name
Test status
Simulation time 17886063 ps
CPU time 0.64 seconds
Started Feb 25 01:19:52 PM PST 24
Finished Feb 25 01:19:53 PM PST 24
Peak memory 202220 kb
Host smart-d728f43e-4751-4310-b379-e32c8239b0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112863783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.1112863783
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.2434112010
Short name T513
Test name
Test status
Simulation time 19853395543 ps
CPU time 1436.12 seconds
Started Feb 25 01:19:49 PM PST 24
Finished Feb 25 01:43:46 PM PST 24
Peak memory 375200 kb
Host smart-97e3521d-551d-4fd7-8352-5a6a30988dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434112010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.2434112010
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.1493841757
Short name T722
Test name
Test status
Simulation time 42373701650 ps
CPU time 121.31 seconds
Started Feb 25 01:19:48 PM PST 24
Finished Feb 25 01:21:49 PM PST 24
Peak memory 210520 kb
Host smart-bd24c85f-f364-49f3-8b87-01c170a4c81f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493841757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.1493841757
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.1102870577
Short name T546
Test name
Test status
Simulation time 2963145995 ps
CPU time 31.98 seconds
Started Feb 25 01:19:55 PM PST 24
Finished Feb 25 01:20:27 PM PST 24
Peak memory 234192 kb
Host smart-efb52535-0c5b-43ac-af48-4586a3bfe240
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102870577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.1102870577
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1764548455
Short name T827
Test name
Test status
Simulation time 6201455210 ps
CPU time 139.55 seconds
Started Feb 25 01:19:49 PM PST 24
Finished Feb 25 01:22:09 PM PST 24
Peak memory 215048 kb
Host smart-55f06eff-cd0a-4636-ac8d-95c36901a269
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764548455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1764548455
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.746881288
Short name T316
Test name
Test status
Simulation time 4117753621 ps
CPU time 117.42 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:21:58 PM PST 24
Peak memory 202296 kb
Host smart-fba3aed8-a887-40da-a845-732e77adcbe0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746881288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.746881288
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.3878819804
Short name T315
Test name
Test status
Simulation time 36033840642 ps
CPU time 847.15 seconds
Started Feb 25 01:19:50 PM PST 24
Finished Feb 25 01:33:57 PM PST 24
Peak memory 373192 kb
Host smart-c8c372c9-2f59-4797-9d26-251e69a9b98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878819804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.3878819804
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.3316213523
Short name T683
Test name
Test status
Simulation time 2121898018 ps
CPU time 14.48 seconds
Started Feb 25 01:19:58 PM PST 24
Finished Feb 25 01:20:13 PM PST 24
Peak memory 235472 kb
Host smart-badc5315-6e9f-4b22-9f3b-b4b14b71225a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316213523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.3316213523
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1783480776
Short name T198
Test name
Test status
Simulation time 7260178672 ps
CPU time 475.66 seconds
Started Feb 25 01:19:58 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 202300 kb
Host smart-4d738427-f246-4c3e-931b-b9c30f1b3c82
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783480776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.1783480776
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.2735849981
Short name T500
Test name
Test status
Simulation time 684470679 ps
CPU time 6.02 seconds
Started Feb 25 01:19:57 PM PST 24
Finished Feb 25 01:20:03 PM PST 24
Peak memory 202580 kb
Host smart-c87b62e0-78d1-42a4-a2a1-be0b7f6dc30e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735849981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2735849981
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.2291265680
Short name T229
Test name
Test status
Simulation time 137397653101 ps
CPU time 683.09 seconds
Started Feb 25 01:19:59 PM PST 24
Finished Feb 25 01:31:23 PM PST 24
Peak memory 376104 kb
Host smart-87bef542-ce0c-497c-aab8-4e44dfbb67b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291265680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2291265680
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.463622989
Short name T115
Test name
Test status
Simulation time 8850292215 ps
CPU time 64.57 seconds
Started Feb 25 01:19:54 PM PST 24
Finished Feb 25 01:20:59 PM PST 24
Peak memory 336332 kb
Host smart-c29114d3-deeb-4d51-8ac9-67979fe983ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463622989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.463622989
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.169444548
Short name T749
Test name
Test status
Simulation time 618185873210 ps
CPU time 6467.92 seconds
Started Feb 25 01:19:55 PM PST 24
Finished Feb 25 03:07:43 PM PST 24
Peak memory 378448 kb
Host smart-38b22a04-eae7-4be7-8675-9addd4915895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169444548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_stress_all.169444548
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1705128218
Short name T128
Test name
Test status
Simulation time 6379646107 ps
CPU time 233.1 seconds
Started Feb 25 01:19:50 PM PST 24
Finished Feb 25 01:23:43 PM PST 24
Peak memory 202428 kb
Host smart-1930a0e7-2aad-4ad3-85fc-a8af8b3287bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705128218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.1705128218
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1556611973
Short name T171
Test name
Test status
Simulation time 802308874 ps
CPU time 105.57 seconds
Started Feb 25 01:19:55 PM PST 24
Finished Feb 25 01:21:40 PM PST 24
Peak memory 352948 kb
Host smart-74552a37-948a-45c7-9a75-5f7a26567860
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556611973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1556611973
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1746383840
Short name T831
Test name
Test status
Simulation time 29807399590 ps
CPU time 1163.07 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:39:23 PM PST 24
Peak memory 373140 kb
Host smart-c6ce64e2-d20f-4ab6-94c4-2331e339dd33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746383840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.1746383840
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.359148266
Short name T366
Test name
Test status
Simulation time 22782037 ps
CPU time 0.64 seconds
Started Feb 25 01:20:09 PM PST 24
Finished Feb 25 01:20:10 PM PST 24
Peak memory 201932 kb
Host smart-a7b955e7-30b7-48e2-ad31-f5aa8d1e0ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359148266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.359148266
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.1829221473
Short name T764
Test name
Test status
Simulation time 136443918308 ps
CPU time 1114.7 seconds
Started Feb 25 01:19:58 PM PST 24
Finished Feb 25 01:38:33 PM PST 24
Peak memory 202488 kb
Host smart-d4d4f2ec-7ed9-41eb-bf3f-6d7ef7e886fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829221473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.1829221473
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.131728966
Short name T504
Test name
Test status
Simulation time 30203502803 ps
CPU time 157.82 seconds
Started Feb 25 01:19:59 PM PST 24
Finished Feb 25 01:22:37 PM PST 24
Peak memory 202384 kb
Host smart-f5d7c7eb-40e9-49cb-bb8f-39f12fddc238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131728966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esc
alation.131728966
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.80716670
Short name T296
Test name
Test status
Simulation time 3246467547 ps
CPU time 46.72 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:20:47 PM PST 24
Peak memory 267524 kb
Host smart-8e1c977d-8e3c-40c6-a4c4-99b302cdd77f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80716670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_max_throughput.80716670
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1288816609
Short name T75
Test name
Test status
Simulation time 33302328336 ps
CPU time 88.25 seconds
Started Feb 25 01:19:58 PM PST 24
Finished Feb 25 01:21:27 PM PST 24
Peak memory 218752 kb
Host smart-56303bd3-81b7-4617-bb64-4147d98dd626
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288816609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.1288816609
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.115133945
Short name T668
Test name
Test status
Simulation time 4032670553 ps
CPU time 120.05 seconds
Started Feb 25 01:20:08 PM PST 24
Finished Feb 25 01:22:08 PM PST 24
Peak memory 202300 kb
Host smart-f0115ef5-d751-4f70-8d1b-cfaa79632962
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115133945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl
_mem_walk.115133945
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.3087043912
Short name T670
Test name
Test status
Simulation time 27118343897 ps
CPU time 903.62 seconds
Started Feb 25 01:19:59 PM PST 24
Finished Feb 25 01:35:03 PM PST 24
Peak memory 378856 kb
Host smart-727ff27e-7e6d-4d51-88cc-4dc3adf2e443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087043912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.3087043912
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.3222641899
Short name T273
Test name
Test status
Simulation time 1205743351 ps
CPU time 92.43 seconds
Started Feb 25 01:20:00 PM PST 24
Finished Feb 25 01:21:33 PM PST 24
Peak memory 329000 kb
Host smart-7935fec1-e656-41a6-bffa-6007aaabda50
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222641899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.3222641899
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3343537668
Short name T826
Test name
Test status
Simulation time 55215237244 ps
CPU time 332.52 seconds
Started Feb 25 01:20:04 PM PST 24
Finished Feb 25 01:25:37 PM PST 24
Peak memory 202400 kb
Host smart-3f6ba086-d14f-4285-84c6-97d36b3378db
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343537668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.3343537668
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.2259440792
Short name T810
Test name
Test status
Simulation time 1350826153 ps
CPU time 6.63 seconds
Started Feb 25 01:20:05 PM PST 24
Finished Feb 25 01:20:12 PM PST 24
Peak memory 202520 kb
Host smart-b0a365dc-a4bb-4126-9e04-d29708c2329c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259440792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2259440792
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2359483832
Short name T761
Test name
Test status
Simulation time 7855851666 ps
CPU time 657.08 seconds
Started Feb 25 01:20:11 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 374252 kb
Host smart-b68a4034-1d0f-4ff5-98ed-9680143bde08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359483832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2359483832
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.3828272038
Short name T586
Test name
Test status
Simulation time 1406494415 ps
CPU time 38.84 seconds
Started Feb 25 01:20:08 PM PST 24
Finished Feb 25 01:20:47 PM PST 24
Peak memory 281984 kb
Host smart-f1a84948-3bae-4029-ba1f-7b7b59595adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828272038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3828272038
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3865323222
Short name T560
Test name
Test status
Simulation time 16339736221 ps
CPU time 299.26 seconds
Started Feb 25 01:19:57 PM PST 24
Finished Feb 25 01:24:57 PM PST 24
Peak memory 202336 kb
Host smart-b65c4059-82aa-4242-b743-a8b396531c58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865323222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.3865323222
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2508847195
Short name T490
Test name
Test status
Simulation time 787200957 ps
CPU time 154.64 seconds
Started Feb 25 01:20:03 PM PST 24
Finished Feb 25 01:22:38 PM PST 24
Peak memory 364932 kb
Host smart-90ee9d6d-073f-45fe-bfa2-4b5ec6a435f9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508847195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.2508847195
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3006693195
Short name T460
Test name
Test status
Simulation time 6482777881 ps
CPU time 602.71 seconds
Started Feb 25 01:18:42 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 377736 kb
Host smart-419b5222-df21-4ddf-a50e-07a78a10ffb0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006693195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.3006693195
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.664647247
Short name T731
Test name
Test status
Simulation time 12184150 ps
CPU time 0.65 seconds
Started Feb 25 01:18:41 PM PST 24
Finished Feb 25 01:18:42 PM PST 24
Peak memory 202116 kb
Host smart-fba52b32-f48b-4cb8-b83b-518fe40a8a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664647247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.664647247
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.4227319775
Short name T352
Test name
Test status
Simulation time 124834325058 ps
CPU time 1872.08 seconds
Started Feb 25 01:18:33 PM PST 24
Finished Feb 25 01:49:45 PM PST 24
Peak memory 202472 kb
Host smart-c87092aa-f2e2-4e49-8b57-4569c9b57e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227319775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
4227319775
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.1536041108
Short name T411
Test name
Test status
Simulation time 52278575133 ps
CPU time 1137.65 seconds
Started Feb 25 01:18:44 PM PST 24
Finished Feb 25 01:37:42 PM PST 24
Peak memory 373160 kb
Host smart-2130ef1f-2973-4d12-9a73-805a693669ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536041108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.1536041108
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.1207235621
Short name T236
Test name
Test status
Simulation time 52951497599 ps
CPU time 128.05 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:20:55 PM PST 24
Peak memory 210528 kb
Host smart-e57fd281-30ca-493f-bb43-ff178e19ea6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207235621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.1207235621
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.2317014162
Short name T227
Test name
Test status
Simulation time 3052435777 ps
CPU time 66.7 seconds
Started Feb 25 01:18:28 PM PST 24
Finished Feb 25 01:19:35 PM PST 24
Peak memory 312764 kb
Host smart-56d3ae8b-9b44-4c4f-b8de-3e1a42044a7d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317014162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.2317014162
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2206899307
Short name T234
Test name
Test status
Simulation time 10195581582 ps
CPU time 89.44 seconds
Started Feb 25 01:18:37 PM PST 24
Finished Feb 25 01:20:06 PM PST 24
Peak memory 211504 kb
Host smart-71a3c57f-d7f7-44bd-876f-2abedb11b92d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206899307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.2206899307
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.3478534164
Short name T322
Test name
Test status
Simulation time 55115202073 ps
CPU time 314.92 seconds
Started Feb 25 01:18:37 PM PST 24
Finished Feb 25 01:23:52 PM PST 24
Peak memory 202596 kb
Host smart-4b99cc9f-e345-43bb-a3e9-8703f177fae6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478534164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.3478534164
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.1882585345
Short name T823
Test name
Test status
Simulation time 50779022851 ps
CPU time 1036.14 seconds
Started Feb 25 01:18:27 PM PST 24
Finished Feb 25 01:35:43 PM PST 24
Peak memory 370100 kb
Host smart-39b0ad85-68b1-4883-8ee5-f5e02335caa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882585345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.1882585345
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.2285194942
Short name T503
Test name
Test status
Simulation time 4676298203 ps
CPU time 20.97 seconds
Started Feb 25 01:18:29 PM PST 24
Finished Feb 25 01:18:50 PM PST 24
Peak memory 202272 kb
Host smart-a2ba49c9-3c2d-4b2d-9d71-6fd9a0b52675
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285194942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.2285194942
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.2881266699
Short name T144
Test name
Test status
Simulation time 1350535016 ps
CPU time 14.61 seconds
Started Feb 25 01:18:44 PM PST 24
Finished Feb 25 01:18:59 PM PST 24
Peak memory 202632 kb
Host smart-3815ad0e-85bf-4fe3-86a1-97128bfbc135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881266699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2881266699
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.1471572922
Short name T16
Test name
Test status
Simulation time 3405314727 ps
CPU time 1206.23 seconds
Started Feb 25 01:18:41 PM PST 24
Finished Feb 25 01:38:48 PM PST 24
Peak memory 376960 kb
Host smart-ef740b5d-040c-4cf3-85ff-91dd72378708
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471572922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1471572922
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.922705489
Short name T37
Test name
Test status
Simulation time 827887624 ps
CPU time 3.28 seconds
Started Feb 25 01:18:42 PM PST 24
Finished Feb 25 01:18:46 PM PST 24
Peak memory 220940 kb
Host smart-b58d253e-e1d0-4140-b85e-5a8b61714f80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922705489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_sec_cm.922705489
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.3294694234
Short name T232
Test name
Test status
Simulation time 4234599761 ps
CPU time 52.18 seconds
Started Feb 25 01:18:27 PM PST 24
Finished Feb 25 01:19:19 PM PST 24
Peak memory 296436 kb
Host smart-b6234ff9-95a0-45df-9241-7b9f75e95a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294694234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3294694234
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.165366418
Short name T580
Test name
Test status
Simulation time 395156646032 ps
CPU time 5586.21 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 02:51:54 PM PST 24
Peak memory 379320 kb
Host smart-4e8acdda-1ea0-414e-8ef6-907dc4d7bc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165366418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_stress_all.165366418
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1176671456
Short name T448
Test name
Test status
Simulation time 3955856359 ps
CPU time 264.6 seconds
Started Feb 25 01:18:32 PM PST 24
Finished Feb 25 01:22:56 PM PST 24
Peak memory 202412 kb
Host smart-f258f28d-7953-47e0-a9f3-0e4e84858ff2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176671456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1176671456
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.4098374515
Short name T287
Test name
Test status
Simulation time 2683230816 ps
CPU time 48.5 seconds
Started Feb 25 01:18:29 PM PST 24
Finished Feb 25 01:19:18 PM PST 24
Peak memory 275100 kb
Host smart-e7602db2-16f8-4377-9b81-4164dd3b717d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098374515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.4098374515
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1015141096
Short name T429
Test name
Test status
Simulation time 6423246353 ps
CPU time 886.83 seconds
Started Feb 25 01:20:11 PM PST 24
Finished Feb 25 01:34:58 PM PST 24
Peak memory 378268 kb
Host smart-29947671-dc89-49d5-8634-7becc392567c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015141096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.1015141096
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.2834503744
Short name T454
Test name
Test status
Simulation time 15371922 ps
CPU time 0.67 seconds
Started Feb 25 01:20:30 PM PST 24
Finished Feb 25 01:20:31 PM PST 24
Peak memory 202196 kb
Host smart-f5ee8245-a275-4b4d-b7c6-60047c97b23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834503744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.2834503744
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.3408848623
Short name T599
Test name
Test status
Simulation time 40556799533 ps
CPU time 230.72 seconds
Started Feb 25 01:20:09 PM PST 24
Finished Feb 25 01:24:00 PM PST 24
Peak memory 354880 kb
Host smart-08840468-5f0b-4dc7-a4eb-db7bf837db28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408848623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.3408848623
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.3799556822
Short name T259
Test name
Test status
Simulation time 3010962088 ps
CPU time 76.31 seconds
Started Feb 25 01:20:09 PM PST 24
Finished Feb 25 01:21:25 PM PST 24
Peak memory 300620 kb
Host smart-693f0067-3165-489d-a38a-7868355f8263
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799556822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.3799556822
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2547771251
Short name T717
Test name
Test status
Simulation time 4880875393 ps
CPU time 79.02 seconds
Started Feb 25 01:20:10 PM PST 24
Finished Feb 25 01:21:29 PM PST 24
Peak memory 211376 kb
Host smart-2616f274-6fa5-4515-8fef-023b114a7576
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547771251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2547771251
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.2411247347
Short name T239
Test name
Test status
Simulation time 8232740666 ps
CPU time 127.92 seconds
Started Feb 25 01:20:08 PM PST 24
Finished Feb 25 01:22:16 PM PST 24
Peak memory 202480 kb
Host smart-24f84c51-5833-4454-8171-9d04ed7802a0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411247347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.2411247347
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.1819303004
Short name T353
Test name
Test status
Simulation time 19452068327 ps
CPU time 1642.52 seconds
Started Feb 25 01:20:13 PM PST 24
Finished Feb 25 01:47:36 PM PST 24
Peak memory 377448 kb
Host smart-8c51c44f-3aea-4e1e-80e0-803922ae3d61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819303004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.1819303004
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.677122921
Short name T185
Test name
Test status
Simulation time 6822381375 ps
CPU time 98.8 seconds
Started Feb 25 01:20:10 PM PST 24
Finished Feb 25 01:21:49 PM PST 24
Peak memory 371932 kb
Host smart-f27c531e-0a53-45fb-876c-9b908b44c8ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677122921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s
ram_ctrl_partial_access.677122921
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2521057617
Short name T741
Test name
Test status
Simulation time 42366939744 ps
CPU time 523.83 seconds
Started Feb 25 01:20:09 PM PST 24
Finished Feb 25 01:28:53 PM PST 24
Peak memory 202280 kb
Host smart-813e1fb7-d95d-4e06-9d19-8e3b78a8ec4b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521057617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2521057617
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.4108915830
Short name T575
Test name
Test status
Simulation time 692554370 ps
CPU time 6.53 seconds
Started Feb 25 01:20:10 PM PST 24
Finished Feb 25 01:20:17 PM PST 24
Peak memory 202468 kb
Host smart-4f86f507-6b27-4fa9-a7ff-d14c1c2d85f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108915830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.4108915830
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.2794045690
Short name T594
Test name
Test status
Simulation time 10561331738 ps
CPU time 250.33 seconds
Started Feb 25 01:20:11 PM PST 24
Finished Feb 25 01:24:21 PM PST 24
Peak memory 373032 kb
Host smart-df7877d7-8959-4027-91f1-0fed3a082a6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794045690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2794045690
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.3036549237
Short name T812
Test name
Test status
Simulation time 19409634036 ps
CPU time 93.56 seconds
Started Feb 25 01:20:15 PM PST 24
Finished Feb 25 01:21:49 PM PST 24
Peak memory 338800 kb
Host smart-cb15dbca-8411-4af7-b603-9bc01d113c67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036549237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3036549237
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.981035994
Short name T224
Test name
Test status
Simulation time 37979509323 ps
CPU time 2773.01 seconds
Started Feb 25 01:20:09 PM PST 24
Finished Feb 25 02:06:22 PM PST 24
Peak memory 380328 kb
Host smart-33386553-a6a9-43f6-bd50-015b438ed564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981035994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_stress_all.981035994
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3185187193
Short name T67
Test name
Test status
Simulation time 3319242591 ps
CPU time 296.14 seconds
Started Feb 25 01:20:16 PM PST 24
Finished Feb 25 01:25:12 PM PST 24
Peak memory 202448 kb
Host smart-2c0ad6c2-b1cb-4538-972a-122037eb9c1d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185187193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.3185187193
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3590755177
Short name T357
Test name
Test status
Simulation time 1384319752 ps
CPU time 27.95 seconds
Started Feb 25 01:20:09 PM PST 24
Finished Feb 25 01:20:37 PM PST 24
Peak memory 214668 kb
Host smart-4fc3dfd3-c1e5-430c-96ce-ddc3a32ad16f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590755177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3590755177
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3008217963
Short name T732
Test name
Test status
Simulation time 4193624931 ps
CPU time 382.95 seconds
Started Feb 25 01:20:31 PM PST 24
Finished Feb 25 01:26:54 PM PST 24
Peak memory 376192 kb
Host smart-22aabbdb-a72a-4748-9e17-aff9679d9cc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008217963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.3008217963
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.936714580
Short name T275
Test name
Test status
Simulation time 42572733 ps
CPU time 0.63 seconds
Started Feb 25 01:20:22 PM PST 24
Finished Feb 25 01:20:23 PM PST 24
Peak memory 202276 kb
Host smart-1d3e7e00-f07d-493a-a625-e3c9787b702e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936714580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.936714580
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1607801809
Short name T267
Test name
Test status
Simulation time 133673784243 ps
CPU time 2270.6 seconds
Started Feb 25 01:20:13 PM PST 24
Finished Feb 25 01:58:04 PM PST 24
Peak memory 202488 kb
Host smart-3dc10c01-cbad-4aaf-9cfc-07bd93d3facd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607801809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1607801809
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.3997481438
Short name T289
Test name
Test status
Simulation time 34087903449 ps
CPU time 217.74 seconds
Started Feb 25 01:20:21 PM PST 24
Finished Feb 25 01:23:59 PM PST 24
Peak memory 210688 kb
Host smart-bd1e20e0-1894-42d9-8677-e54f4a5ac2f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997481438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.3997481438
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.3116331255
Short name T768
Test name
Test status
Simulation time 4148057296 ps
CPU time 28.18 seconds
Started Feb 25 01:20:31 PM PST 24
Finished Feb 25 01:20:59 PM PST 24
Peak memory 210684 kb
Host smart-2c20fbf9-3cf4-4d08-8ebb-cfa01dc4d674
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116331255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.3116331255
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3404727361
Short name T462
Test name
Test status
Simulation time 6262595053 ps
CPU time 148.54 seconds
Started Feb 25 01:20:32 PM PST 24
Finished Feb 25 01:23:01 PM PST 24
Peak memory 210984 kb
Host smart-2ccbb791-2ac2-4cc6-a0be-7ef7423de44e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404727361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.3404727361
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.2589041851
Short name T201
Test name
Test status
Simulation time 8041821668 ps
CPU time 249.48 seconds
Started Feb 25 01:20:31 PM PST 24
Finished Feb 25 01:24:41 PM PST 24
Peak memory 202440 kb
Host smart-98c73034-21d2-45dc-8465-0ca22f5ed35e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589041851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.2589041851
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.1595196034
Short name T194
Test name
Test status
Simulation time 5636542223 ps
CPU time 693.39 seconds
Started Feb 25 01:20:21 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 377124 kb
Host smart-afe71213-bc8e-4b7d-955b-cb7cbc38f031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595196034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.1595196034
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.3181132058
Short name T754
Test name
Test status
Simulation time 4379511244 ps
CPU time 39.87 seconds
Started Feb 25 01:20:20 PM PST 24
Finished Feb 25 01:21:01 PM PST 24
Peak memory 282128 kb
Host smart-cea1cd96-a9c4-4498-acd3-9a602b7ec9a3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181132058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.3181132058
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1885617595
Short name T659
Test name
Test status
Simulation time 229778730932 ps
CPU time 489.67 seconds
Started Feb 25 01:20:21 PM PST 24
Finished Feb 25 01:28:31 PM PST 24
Peak memory 202352 kb
Host smart-7db473f3-daf5-4f4b-9833-1e957d605747
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885617595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1885617595
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3589146470
Short name T760
Test name
Test status
Simulation time 697673571 ps
CPU time 14.01 seconds
Started Feb 25 01:20:23 PM PST 24
Finished Feb 25 01:20:37 PM PST 24
Peak memory 202592 kb
Host smart-a406a543-65f0-406a-9fd7-75d31c954806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589146470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3589146470
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3716902175
Short name T461
Test name
Test status
Simulation time 481070742 ps
CPU time 22.8 seconds
Started Feb 25 01:20:23 PM PST 24
Finished Feb 25 01:20:46 PM PST 24
Peak memory 202372 kb
Host smart-4647ade1-0314-424d-ad74-d182a5ecf34d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716902175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3716902175
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1145496655
Short name T343
Test name
Test status
Simulation time 5154600058 ps
CPU time 242.77 seconds
Started Feb 25 01:20:31 PM PST 24
Finished Feb 25 01:24:34 PM PST 24
Peak memory 210584 kb
Host smart-e281cb94-69f2-4e0b-8951-e8576be4f22e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145496655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.1145496655
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3913540410
Short name T133
Test name
Test status
Simulation time 4583976828 ps
CPU time 171.77 seconds
Started Feb 25 01:20:32 PM PST 24
Finished Feb 25 01:23:24 PM PST 24
Peak memory 366216 kb
Host smart-573be2a6-e290-4bb3-b84e-ec092c9402d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913540410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3913540410
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.785130584
Short name T609
Test name
Test status
Simulation time 15739089525 ps
CPU time 577.42 seconds
Started Feb 25 01:20:31 PM PST 24
Finished Feb 25 01:30:09 PM PST 24
Peak memory 363880 kb
Host smart-95f1dd6a-dffd-4999-9bc1-a479a6d04be1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785130584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.sram_ctrl_access_during_key_req.785130584
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.219440359
Short name T569
Test name
Test status
Simulation time 63080297 ps
CPU time 0.67 seconds
Started Feb 25 01:20:46 PM PST 24
Finished Feb 25 01:20:47 PM PST 24
Peak memory 202248 kb
Host smart-8a37c201-a15a-440d-aece-fa979fa64363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219440359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.219440359
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.1380114547
Short name T174
Test name
Test status
Simulation time 87327318810 ps
CPU time 1343.16 seconds
Started Feb 25 01:20:32 PM PST 24
Finished Feb 25 01:42:55 PM PST 24
Peak memory 202440 kb
Host smart-a86770fd-a41d-4761-97ce-33455fb8b28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380114547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.1380114547
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.2784496850
Short name T387
Test name
Test status
Simulation time 8767625179 ps
CPU time 91.3 seconds
Started Feb 25 01:20:33 PM PST 24
Finished Feb 25 01:22:05 PM PST 24
Peak memory 210620 kb
Host smart-12f81b71-24e8-4efc-b02e-8d9020685f83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784496850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.2784496850
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.4025160460
Short name T43
Test name
Test status
Simulation time 2168255407 ps
CPU time 85.78 seconds
Started Feb 25 01:20:38 PM PST 24
Finished Feb 25 01:22:04 PM PST 24
Peak memory 321040 kb
Host smart-d5a3041a-b057-4525-8a00-42fbb5218f69
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025160460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.4025160460
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2415758202
Short name T716
Test name
Test status
Simulation time 2505620118 ps
CPU time 81.27 seconds
Started Feb 25 01:20:46 PM PST 24
Finished Feb 25 01:22:08 PM PST 24
Peak memory 211844 kb
Host smart-91fc37b2-71af-4688-a055-d2e62ce705d4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415758202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.2415758202
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.1016505663
Short name T403
Test name
Test status
Simulation time 1978562034 ps
CPU time 132.19 seconds
Started Feb 25 01:20:32 PM PST 24
Finished Feb 25 01:22:44 PM PST 24
Peak memory 202248 kb
Host smart-40e15831-af9b-4f85-a501-4d36b70ec09e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016505663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.1016505663
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.3709065801
Short name T486
Test name
Test status
Simulation time 31508472490 ps
CPU time 749.09 seconds
Started Feb 25 01:20:23 PM PST 24
Finished Feb 25 01:32:52 PM PST 24
Peak memory 358912 kb
Host smart-f539e385-5885-4b1b-8a40-2628c4f5b073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709065801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.3709065801
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.2531268746
Short name T373
Test name
Test status
Simulation time 1050589527 ps
CPU time 42.54 seconds
Started Feb 25 01:20:38 PM PST 24
Finished Feb 25 01:21:21 PM PST 24
Peak memory 285792 kb
Host smart-a2d5ae3a-7a04-4eb1-bfbe-ba728864e7b1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531268746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.2531268746
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2875947788
Short name T603
Test name
Test status
Simulation time 35349462885 ps
CPU time 440.38 seconds
Started Feb 25 01:20:34 PM PST 24
Finished Feb 25 01:27:55 PM PST 24
Peak memory 202388 kb
Host smart-800de2a0-8c57-4495-a820-645f4ce3a4ea
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875947788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.2875947788
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.1758092057
Short name T781
Test name
Test status
Simulation time 710469796 ps
CPU time 14.27 seconds
Started Feb 25 01:20:31 PM PST 24
Finished Feb 25 01:20:46 PM PST 24
Peak memory 202616 kb
Host smart-c38d3709-875c-4edd-b254-f7b176910597
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758092057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1758092057
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.525122874
Short name T279
Test name
Test status
Simulation time 1234980962 ps
CPU time 215.12 seconds
Started Feb 25 01:20:40 PM PST 24
Finished Feb 25 01:24:15 PM PST 24
Peak memory 351168 kb
Host smart-42a8d6b5-0227-4280-aa84-c9fa408f7906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525122874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.525122874
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.2795743862
Short name T824
Test name
Test status
Simulation time 1492852257 ps
CPU time 17.78 seconds
Started Feb 25 01:20:21 PM PST 24
Finished Feb 25 01:20:38 PM PST 24
Peak memory 202404 kb
Host smart-ea7774ed-198a-4b7c-a3c3-d6d9f928a399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795743862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2795743862
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.1812536948
Short name T631
Test name
Test status
Simulation time 136354503097 ps
CPU time 1859.72 seconds
Started Feb 25 01:20:44 PM PST 24
Finished Feb 25 01:51:44 PM PST 24
Peak memory 375428 kb
Host smart-5d88ec7a-3e24-4d0d-aad5-6237e66a2925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812536948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.1812536948
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1590733261
Short name T362
Test name
Test status
Simulation time 5204334700 ps
CPU time 202.48 seconds
Started Feb 25 01:20:36 PM PST 24
Finished Feb 25 01:23:59 PM PST 24
Peak memory 202380 kb
Host smart-f6ee0519-8f32-4fda-bba8-e7453c71aff9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590733261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.1590733261
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.575638180
Short name T601
Test name
Test status
Simulation time 805225159 ps
CPU time 106.35 seconds
Started Feb 25 01:20:38 PM PST 24
Finished Feb 25 01:22:25 PM PST 24
Peak memory 344764 kb
Host smart-5fc48c43-2cb4-422e-b4ae-11be8e363732
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575638180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.575638180
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3284812661
Short name T255
Test name
Test status
Simulation time 7886233420 ps
CPU time 1248.64 seconds
Started Feb 25 01:20:45 PM PST 24
Finished Feb 25 01:41:34 PM PST 24
Peak memory 379312 kb
Host smart-634b90e6-d599-47b2-a663-585814591b68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284812661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.3284812661
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1127753099
Short name T787
Test name
Test status
Simulation time 33734405 ps
CPU time 0.63 seconds
Started Feb 25 01:20:47 PM PST 24
Finished Feb 25 01:20:48 PM PST 24
Peak memory 201884 kb
Host smart-ce192f8d-bf98-40cc-aea8-4089d3e4ac57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127753099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1127753099
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.3209937905
Short name T697
Test name
Test status
Simulation time 50862320763 ps
CPU time 1147.7 seconds
Started Feb 25 01:20:49 PM PST 24
Finished Feb 25 01:39:57 PM PST 24
Peak memory 202348 kb
Host smart-ef2a2db0-9b34-4fcb-8d7b-02059a977c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209937905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.3209937905
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.2795181827
Short name T309
Test name
Test status
Simulation time 17487518335 ps
CPU time 758.12 seconds
Started Feb 25 01:20:45 PM PST 24
Finished Feb 25 01:33:24 PM PST 24
Peak memory 374608 kb
Host smart-5eb68847-58c9-4681-88e4-b078a73b9b2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795181827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.2795181827
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1456664301
Short name T813
Test name
Test status
Simulation time 2980789036 ps
CPU time 32.17 seconds
Started Feb 25 01:20:48 PM PST 24
Finished Feb 25 01:21:21 PM PST 24
Peak memory 235208 kb
Host smart-88e411f4-6747-457f-9688-fa2211cdfdb7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456664301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1456664301
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.811187443
Short name T628
Test name
Test status
Simulation time 2896103556 ps
CPU time 79.67 seconds
Started Feb 25 01:20:52 PM PST 24
Finished Feb 25 01:22:12 PM PST 24
Peak memory 211500 kb
Host smart-bd044e40-64cd-4866-bfd1-4ffb4a6dd743
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811187443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.sram_ctrl_mem_partial_access.811187443
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2412882342
Short name T637
Test name
Test status
Simulation time 6899711880 ps
CPU time 134.86 seconds
Started Feb 25 01:20:45 PM PST 24
Finished Feb 25 01:23:00 PM PST 24
Peak memory 202488 kb
Host smart-a08dccac-aae0-47f2-bfd7-0c2acf124957
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412882342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2412882342
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.3459173848
Short name T688
Test name
Test status
Simulation time 8068013664 ps
CPU time 204.15 seconds
Started Feb 25 01:20:46 PM PST 24
Finished Feb 25 01:24:11 PM PST 24
Peak memory 374140 kb
Host smart-27c711b4-6f9b-4778-8787-00dae0891f23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459173848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.3459173848
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.1042777962
Short name T809
Test name
Test status
Simulation time 727589201 ps
CPU time 13.92 seconds
Started Feb 25 01:20:46 PM PST 24
Finished Feb 25 01:21:00 PM PST 24
Peak memory 205320 kb
Host smart-f2cd465d-c4ad-4341-be61-bbea022331dc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042777962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.1042777962
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.802994960
Short name T518
Test name
Test status
Simulation time 48947869385 ps
CPU time 507.64 seconds
Started Feb 25 01:20:46 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 202348 kb
Host smart-9de376bd-8506-4fd0-95f0-88590840cd5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802994960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.sram_ctrl_partial_access_b2b.802994960
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.1542084289
Short name T430
Test name
Test status
Simulation time 444656754 ps
CPU time 5.89 seconds
Started Feb 25 01:20:48 PM PST 24
Finished Feb 25 01:20:54 PM PST 24
Peak memory 202568 kb
Host smart-c8afe810-b1b9-475b-aa17-c51ce3e1724b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542084289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1542084289
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.682002921
Short name T658
Test name
Test status
Simulation time 11860979390 ps
CPU time 762.47 seconds
Started Feb 25 01:20:47 PM PST 24
Finished Feb 25 01:33:30 PM PST 24
Peak memory 376244 kb
Host smart-430104db-914d-45ca-a5de-87d3888b0d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682002921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.682002921
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.3248582375
Short name T247
Test name
Test status
Simulation time 490741988 ps
CPU time 15.23 seconds
Started Feb 25 01:20:45 PM PST 24
Finished Feb 25 01:21:00 PM PST 24
Peak memory 202396 kb
Host smart-693f512c-7611-4b81-88cd-7fc1e41cccee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248582375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3248582375
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.2722654233
Short name T730
Test name
Test status
Simulation time 216756914263 ps
CPU time 7116.37 seconds
Started Feb 25 01:20:44 PM PST 24
Finished Feb 25 03:19:21 PM PST 24
Peak memory 380388 kb
Host smart-febab6b2-8c56-4244-986e-851e2da00328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722654233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.2722654233
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1179302506
Short name T250
Test name
Test status
Simulation time 4136833697 ps
CPU time 294.59 seconds
Started Feb 25 01:20:44 PM PST 24
Finished Feb 25 01:25:39 PM PST 24
Peak memory 202428 kb
Host smart-92f09199-342e-4d00-865b-c76bbda482e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179302506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.1179302506
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.184003099
Short name T439
Test name
Test status
Simulation time 9762374541 ps
CPU time 190.16 seconds
Started Feb 25 01:20:47 PM PST 24
Finished Feb 25 01:23:57 PM PST 24
Peak memory 368020 kb
Host smart-9a893044-5d8a-42e1-9181-e66f7f24732c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184003099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.184003099
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1278549782
Short name T517
Test name
Test status
Simulation time 6487161313 ps
CPU time 537.09 seconds
Started Feb 25 01:20:56 PM PST 24
Finished Feb 25 01:29:54 PM PST 24
Peak memory 372008 kb
Host smart-b30ea307-7adf-4e69-aa05-b447c2982850
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278549782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.1278549782
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.1908232073
Short name T718
Test name
Test status
Simulation time 16133732 ps
CPU time 0.65 seconds
Started Feb 25 01:21:08 PM PST 24
Finished Feb 25 01:21:08 PM PST 24
Peak memory 202268 kb
Host smart-21893b28-0662-4aa7-ad90-c6090f6d1471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908232073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.1908232073
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.1583469109
Short name T320
Test name
Test status
Simulation time 301585813891 ps
CPU time 1852.31 seconds
Started Feb 25 01:20:50 PM PST 24
Finished Feb 25 01:51:43 PM PST 24
Peak memory 210616 kb
Host smart-2a8bebd9-4828-4ae7-ad71-ec50674079b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583469109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.1583469109
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.3874514241
Short name T762
Test name
Test status
Simulation time 15988434306 ps
CPU time 41.23 seconds
Started Feb 25 01:20:49 PM PST 24
Finished Feb 25 01:21:31 PM PST 24
Peak memory 213840 kb
Host smart-7005ef74-f699-4554-9ff4-42039b89ed04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874514241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.3874514241
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.3588878949
Short name T433
Test name
Test status
Simulation time 1508438309 ps
CPU time 62.82 seconds
Started Feb 25 01:20:56 PM PST 24
Finished Feb 25 01:21:59 PM PST 24
Peak memory 300296 kb
Host smart-c7e91186-95e7-49bf-bece-337292179e5f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588878949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.3588878949
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.906630443
Short name T226
Test name
Test status
Simulation time 31136874677 ps
CPU time 158.98 seconds
Started Feb 25 01:21:05 PM PST 24
Finished Feb 25 01:23:44 PM PST 24
Peak memory 211820 kb
Host smart-2f8986fc-a230-4b00-bcba-72525e428f63
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906630443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_mem_partial_access.906630443
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.1340158159
Short name T821
Test name
Test status
Simulation time 14176959226 ps
CPU time 293.58 seconds
Started Feb 25 01:21:10 PM PST 24
Finished Feb 25 01:26:04 PM PST 24
Peak memory 202456 kb
Host smart-91c3f274-8952-4735-8178-46d56220a0a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340158159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.1340158159
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.2830708903
Short name T834
Test name
Test status
Simulation time 18201689102 ps
CPU time 1279.9 seconds
Started Feb 25 01:20:50 PM PST 24
Finished Feb 25 01:42:10 PM PST 24
Peak memory 378292 kb
Host smart-2fb422e3-03ea-4401-b149-f5541c9422f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830708903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.2830708903
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3989925922
Short name T44
Test name
Test status
Simulation time 479659390 ps
CPU time 14.01 seconds
Started Feb 25 01:20:51 PM PST 24
Finished Feb 25 01:21:06 PM PST 24
Peak memory 230696 kb
Host smart-079584c2-1350-4219-b6ec-103bd3fa3c12
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989925922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3989925922
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2570755598
Short name T803
Test name
Test status
Simulation time 7696241375 ps
CPU time 192.76 seconds
Started Feb 25 01:20:51 PM PST 24
Finished Feb 25 01:24:04 PM PST 24
Peak memory 202428 kb
Host smart-f2abd001-90ae-489d-8a61-0252ab9df6c1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570755598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.2570755598
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.3642827965
Short name T333
Test name
Test status
Simulation time 359020638 ps
CPU time 5.54 seconds
Started Feb 25 01:20:51 PM PST 24
Finished Feb 25 01:20:57 PM PST 24
Peak memory 202524 kb
Host smart-a0d128fa-2b62-4f4b-b3ef-02f2e7962c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642827965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3642827965
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.2377351703
Short name T474
Test name
Test status
Simulation time 8551470406 ps
CPU time 777.89 seconds
Started Feb 25 01:20:53 PM PST 24
Finished Feb 25 01:33:51 PM PST 24
Peak memory 373248 kb
Host smart-a3a7a3c1-ab47-4a60-8b6f-047d2200aaa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377351703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2377351703
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.2983972486
Short name T272
Test name
Test status
Simulation time 6353191976 ps
CPU time 31.98 seconds
Started Feb 25 01:20:51 PM PST 24
Finished Feb 25 01:21:23 PM PST 24
Peak memory 202348 kb
Host smart-b2466ad8-7025-46ea-8689-28b1a723450c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983972486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2983972486
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.94288300
Short name T107
Test name
Test status
Simulation time 360163931360 ps
CPU time 8493.01 seconds
Started Feb 25 01:21:06 PM PST 24
Finished Feb 25 03:42:40 PM PST 24
Peak memory 379416 kb
Host smart-56ce3b47-0d1b-4e27-a2b7-6863af40eb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94288300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.sram_ctrl_stress_all.94288300
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.9331436
Short name T778
Test name
Test status
Simulation time 15173163518 ps
CPU time 325.67 seconds
Started Feb 25 01:20:50 PM PST 24
Finished Feb 25 01:26:16 PM PST 24
Peak memory 202428 kb
Host smart-060e04cd-e881-43f3-9434-5a4ae955edfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9331436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s
ram_ctrl_stress_pipeline.9331436
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.753279544
Short name T127
Test name
Test status
Simulation time 3020714979 ps
CPU time 64.25 seconds
Started Feb 25 01:20:52 PM PST 24
Finished Feb 25 01:21:56 PM PST 24
Peak memory 284220 kb
Host smart-5a4d2c03-1b54-4eeb-833d-350bb0320120
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753279544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_throughput_w_partial_write.753279544
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3429370960
Short name T519
Test name
Test status
Simulation time 34077108259 ps
CPU time 1208.94 seconds
Started Feb 25 01:21:07 PM PST 24
Finished Feb 25 01:41:16 PM PST 24
Peak memory 378124 kb
Host smart-f96de5ba-7041-472e-8522-a7cbe1db173b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429370960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.3429370960
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.2756905380
Short name T528
Test name
Test status
Simulation time 21482975 ps
CPU time 0.62 seconds
Started Feb 25 01:21:12 PM PST 24
Finished Feb 25 01:21:12 PM PST 24
Peak memory 201928 kb
Host smart-782a61be-b916-457f-9203-62d5cde0f81c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756905380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.2756905380
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.3708827028
Short name T401
Test name
Test status
Simulation time 66640933755 ps
CPU time 525.3 seconds
Started Feb 25 01:21:07 PM PST 24
Finished Feb 25 01:29:53 PM PST 24
Peak memory 202324 kb
Host smart-48949518-72e8-4355-8f65-b16a7de8669a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708827028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.3708827028
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.2373128673
Short name T436
Test name
Test status
Simulation time 16868731896 ps
CPU time 232.57 seconds
Started Feb 25 01:21:06 PM PST 24
Finished Feb 25 01:24:59 PM PST 24
Peak memory 368932 kb
Host smart-e5dbcb6b-c231-4339-af0d-e7bea9811866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373128673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.2373128673
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.608474454
Short name T443
Test name
Test status
Simulation time 833087254 ps
CPU time 187.07 seconds
Started Feb 25 01:21:06 PM PST 24
Finished Feb 25 01:24:13 PM PST 24
Peak memory 369068 kb
Host smart-15818e69-78fb-4914-be03-56297ea0555d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608474454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sram_ctrl_max_throughput.608474454
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2652446885
Short name T515
Test name
Test status
Simulation time 4338468660 ps
CPU time 149.06 seconds
Started Feb 25 01:21:12 PM PST 24
Finished Feb 25 01:23:41 PM PST 24
Peak memory 214892 kb
Host smart-ca678e88-3c86-4695-b67a-ea5377e90569
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652446885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2652446885
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3896659022
Short name T188
Test name
Test status
Simulation time 8215339513 ps
CPU time 239.9 seconds
Started Feb 25 01:21:18 PM PST 24
Finished Feb 25 01:25:18 PM PST 24
Peak memory 202416 kb
Host smart-bd2a113f-70a2-4184-aa0a-f884d87de3cf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896659022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.3896659022
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.2816531070
Short name T501
Test name
Test status
Simulation time 23420161823 ps
CPU time 517.88 seconds
Started Feb 25 01:21:06 PM PST 24
Finished Feb 25 01:29:44 PM PST 24
Peak memory 373824 kb
Host smart-31e96d95-4974-48ed-95ae-1e69af7fba0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816531070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.2816531070
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.601831169
Short name T679
Test name
Test status
Simulation time 673679398 ps
CPU time 10.51 seconds
Started Feb 25 01:21:05 PM PST 24
Finished Feb 25 01:21:16 PM PST 24
Peak memory 202304 kb
Host smart-c48c6701-8dd5-432e-90a5-954f06e64f4b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601831169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s
ram_ctrl_partial_access.601831169
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.291086570
Short name T755
Test name
Test status
Simulation time 11660425631 ps
CPU time 364.2 seconds
Started Feb 25 01:21:06 PM PST 24
Finished Feb 25 01:27:10 PM PST 24
Peak memory 202440 kb
Host smart-1e6f7e8d-e749-4051-b19e-cd592d4e6e8e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291086570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.sram_ctrl_partial_access_b2b.291086570
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.1539873865
Short name T314
Test name
Test status
Simulation time 1349909298 ps
CPU time 5.7 seconds
Started Feb 25 01:21:11 PM PST 24
Finished Feb 25 01:21:17 PM PST 24
Peak memory 202560 kb
Host smart-13f64f31-80c4-4a24-a0f4-b0d8ece4a5a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539873865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1539873865
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.1934182329
Short name T649
Test name
Test status
Simulation time 45311117216 ps
CPU time 890.23 seconds
Started Feb 25 01:21:11 PM PST 24
Finished Feb 25 01:36:01 PM PST 24
Peak memory 376192 kb
Host smart-53ce9d33-6765-41f1-8afd-8ce37dc0fd90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934182329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1934182329
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1778326563
Short name T629
Test name
Test status
Simulation time 722408495 ps
CPU time 10.5 seconds
Started Feb 25 01:21:07 PM PST 24
Finished Feb 25 01:21:17 PM PST 24
Peak memory 202348 kb
Host smart-d2f255f0-b06f-4f56-b8a9-5528ce10e843
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778326563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1778326563
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.1245938791
Short name T206
Test name
Test status
Simulation time 1681137921439 ps
CPU time 4760.25 seconds
Started Feb 25 01:21:14 PM PST 24
Finished Feb 25 02:40:35 PM PST 24
Peak memory 380372 kb
Host smart-dfb67324-8e3c-4a3c-9293-36b4f8e65182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245938791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.1245938791
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2898420064
Short name T5
Test name
Test status
Simulation time 45606962866 ps
CPU time 370.85 seconds
Started Feb 25 01:21:05 PM PST 24
Finished Feb 25 01:27:16 PM PST 24
Peak memory 202380 kb
Host smart-b3cf6b35-294d-449e-9b40-8b68dc20f7a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898420064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.2898420064
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2419794272
Short name T116
Test name
Test status
Simulation time 3354363110 ps
CPU time 94.97 seconds
Started Feb 25 01:21:08 PM PST 24
Finished Feb 25 01:22:43 PM PST 24
Peak memory 309236 kb
Host smart-09c07ecc-04b4-40e8-80ba-4e19ad2d9907
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419794272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2419794272
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3147172718
Short name T446
Test name
Test status
Simulation time 5928829721 ps
CPU time 860.08 seconds
Started Feb 25 01:21:13 PM PST 24
Finished Feb 25 01:35:33 PM PST 24
Peak memory 378248 kb
Host smart-b5b5743d-3e27-4708-ba69-49888d3a63c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147172718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.3147172718
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.125631274
Short name T28
Test name
Test status
Simulation time 45674611 ps
CPU time 0.65 seconds
Started Feb 25 01:21:28 PM PST 24
Finished Feb 25 01:21:29 PM PST 24
Peak memory 202228 kb
Host smart-05c961f0-dfdf-49e5-af35-f1cf01b9fefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125631274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.125631274
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.353733116
Short name T832
Test name
Test status
Simulation time 461316468249 ps
CPU time 1656.85 seconds
Started Feb 25 01:21:14 PM PST 24
Finished Feb 25 01:48:51 PM PST 24
Peak memory 202344 kb
Host smart-df8769b2-c278-4d11-93df-bed922495f94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353733116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.
353733116
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.653729628
Short name T578
Test name
Test status
Simulation time 767345946 ps
CPU time 61.54 seconds
Started Feb 25 01:21:19 PM PST 24
Finished Feb 25 01:22:21 PM PST 24
Peak memory 315836 kb
Host smart-abb40a29-f77e-4a9c-a41d-cb3f522b5c9b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653729628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.sram_ctrl_max_throughput.653729628
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1412035829
Short name T78
Test name
Test status
Simulation time 1872815771 ps
CPU time 71.12 seconds
Started Feb 25 01:21:26 PM PST 24
Finished Feb 25 01:22:38 PM PST 24
Peak memory 210932 kb
Host smart-fba36d2d-97ec-4480-babc-b8f59d2107e0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412035829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1412035829
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2011509060
Short name T223
Test name
Test status
Simulation time 15765708113 ps
CPU time 235.84 seconds
Started Feb 25 01:21:27 PM PST 24
Finished Feb 25 01:25:23 PM PST 24
Peak memory 202368 kb
Host smart-42334b3a-d14f-4356-addd-c843a0b6c291
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011509060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2011509060
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.2161255259
Short name T375
Test name
Test status
Simulation time 131468869936 ps
CPU time 882.15 seconds
Started Feb 25 01:21:12 PM PST 24
Finished Feb 25 01:35:55 PM PST 24
Peak memory 371024 kb
Host smart-4ef2d440-6643-41bd-8b11-a5a76cb43516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161255259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.2161255259
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.2401624259
Short name T705
Test name
Test status
Simulation time 872413905 ps
CPU time 158.73 seconds
Started Feb 25 01:21:14 PM PST 24
Finished Feb 25 01:23:53 PM PST 24
Peak memory 363868 kb
Host smart-8f136e30-4947-48da-8ac8-6c191eab8cc3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401624259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.2401624259
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.4160513130
Short name T295
Test name
Test status
Simulation time 39945204841 ps
CPU time 249.63 seconds
Started Feb 25 01:21:14 PM PST 24
Finished Feb 25 01:25:24 PM PST 24
Peak memory 202408 kb
Host smart-bb368af2-a1e6-497f-bdde-3243379d6fc6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160513130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.4160513130
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.1628383725
Short name T408
Test name
Test status
Simulation time 3349748482 ps
CPU time 6.72 seconds
Started Feb 25 01:21:27 PM PST 24
Finished Feb 25 01:21:35 PM PST 24
Peak memory 202580 kb
Host smart-0e0d5221-3ee8-4c30-966d-884ffe61b6ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628383725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1628383725
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.3684646933
Short name T175
Test name
Test status
Simulation time 72528528247 ps
CPU time 695.43 seconds
Started Feb 25 01:21:18 PM PST 24
Finished Feb 25 01:32:53 PM PST 24
Peak memory 377292 kb
Host smart-d46c35f1-1373-41bf-8c40-c6aab65ed76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684646933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3684646933
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3159411996
Short name T304
Test name
Test status
Simulation time 393647076 ps
CPU time 7.24 seconds
Started Feb 25 01:21:13 PM PST 24
Finished Feb 25 01:21:20 PM PST 24
Peak memory 206372 kb
Host smart-99f894d2-92cc-4f14-aecb-c482c9aba09d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159411996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3159411996
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.611777741
Short name T801
Test name
Test status
Simulation time 3060687648 ps
CPU time 230.81 seconds
Started Feb 25 01:21:11 PM PST 24
Finished Feb 25 01:25:02 PM PST 24
Peak memory 202296 kb
Host smart-bad3e5b6-879f-490c-b5b9-aacf4cc27990
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611777741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_stress_pipeline.611777741
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.743686178
Short name T183
Test name
Test status
Simulation time 3594718837 ps
CPU time 124.06 seconds
Started Feb 25 01:21:12 PM PST 24
Finished Feb 25 01:23:16 PM PST 24
Peak memory 368116 kb
Host smart-474dc884-72aa-4e88-a65c-cb9fdf7b9103
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743686178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.743686178
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2221244152
Short name T742
Test name
Test status
Simulation time 5124725619 ps
CPU time 470.19 seconds
Started Feb 25 01:21:39 PM PST 24
Finished Feb 25 01:29:30 PM PST 24
Peak memory 374064 kb
Host smart-2a342bdf-ad4c-4bb3-89f2-c0e88a87f4af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221244152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.2221244152
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.785898947
Short name T573
Test name
Test status
Simulation time 13052355 ps
CPU time 0.66 seconds
Started Feb 25 01:21:36 PM PST 24
Finished Feb 25 01:21:36 PM PST 24
Peak memory 202180 kb
Host smart-0f8c260f-0fa9-4f40-9c38-3845644c1076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785898947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.785898947
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.2501748570
Short name T276
Test name
Test status
Simulation time 158321375833 ps
CPU time 1802.6 seconds
Started Feb 25 01:21:27 PM PST 24
Finished Feb 25 01:51:31 PM PST 24
Peak memory 202556 kb
Host smart-be65a429-9ece-4865-a6fd-e5996160c9e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501748570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.2501748570
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.3580970867
Short name T684
Test name
Test status
Simulation time 58276427841 ps
CPU time 158.29 seconds
Started Feb 25 01:21:30 PM PST 24
Finished Feb 25 01:24:08 PM PST 24
Peak memory 214280 kb
Host smart-93d87254-2ea9-4d8c-99b2-aaf19bd01f43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580970867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.3580970867
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.1835726920
Short name T835
Test name
Test status
Simulation time 783491954 ps
CPU time 113.34 seconds
Started Feb 25 01:21:29 PM PST 24
Finished Feb 25 01:23:22 PM PST 24
Peak memory 339352 kb
Host smart-ae7b85f7-e1b1-42a2-9934-251d3a5a00a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835726920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.1835726920
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1972908878
Short name T672
Test name
Test status
Simulation time 9506575397 ps
CPU time 75.38 seconds
Started Feb 25 01:21:35 PM PST 24
Finished Feb 25 01:22:50 PM PST 24
Peak memory 218780 kb
Host smart-40165240-b00d-4781-b6b6-a6677ca57bfc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972908878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.1972908878
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1882567928
Short name T132
Test name
Test status
Simulation time 17649706911 ps
CPU time 149.36 seconds
Started Feb 25 01:21:37 PM PST 24
Finished Feb 25 01:24:07 PM PST 24
Peak memory 202364 kb
Host smart-93c6f010-eb3a-4344-9911-72c6132f8943
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882567928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1882567928
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.3730507904
Short name T815
Test name
Test status
Simulation time 9100559068 ps
CPU time 1217.09 seconds
Started Feb 25 01:21:26 PM PST 24
Finished Feb 25 01:41:43 PM PST 24
Peak memory 368116 kb
Host smart-d61f126c-d4dd-41b0-acf8-843319b584ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730507904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.3730507904
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1090104735
Short name T290
Test name
Test status
Simulation time 764150857 ps
CPU time 31.43 seconds
Started Feb 25 01:21:27 PM PST 24
Finished Feb 25 01:21:58 PM PST 24
Peak memory 202332 kb
Host smart-2dae45e5-2f9b-4398-9bbe-838c080d3ce9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090104735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1090104735
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3251306790
Short name T466
Test name
Test status
Simulation time 17085528969 ps
CPU time 445.18 seconds
Started Feb 25 01:21:28 PM PST 24
Finished Feb 25 01:28:54 PM PST 24
Peak memory 202400 kb
Host smart-9a0adf0f-ed98-45b2-b6b6-adbf722e29fe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251306790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.3251306790
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.3163129203
Short name T584
Test name
Test status
Simulation time 347484277 ps
CPU time 5.98 seconds
Started Feb 25 01:21:41 PM PST 24
Finished Feb 25 01:21:47 PM PST 24
Peak memory 202572 kb
Host smart-d6d7dac7-ee17-4ebe-95c1-2c412a2f23ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163129203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3163129203
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.3851978569
Short name T102
Test name
Test status
Simulation time 7647025167 ps
CPU time 526.27 seconds
Started Feb 25 01:21:35 PM PST 24
Finished Feb 25 01:30:21 PM PST 24
Peak memory 375268 kb
Host smart-5a984e2a-9e20-4556-8fd0-501428d66434
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851978569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3851978569
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1532009702
Short name T746
Test name
Test status
Simulation time 987596839 ps
CPU time 13.83 seconds
Started Feb 25 01:21:27 PM PST 24
Finished Feb 25 01:21:41 PM PST 24
Peak memory 238460 kb
Host smart-56307ae8-4a8d-4d15-b8a6-221d9ed5686d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532009702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1532009702
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.3512262496
Short name T509
Test name
Test status
Simulation time 134167582166 ps
CPU time 3210.91 seconds
Started Feb 25 01:21:41 PM PST 24
Finished Feb 25 02:15:12 PM PST 24
Peak memory 366928 kb
Host smart-72ee3758-e3b0-4088-9b5f-a7ba77f7acbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512262496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.3512262496
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1525984003
Short name T818
Test name
Test status
Simulation time 8929223597 ps
CPU time 358.2 seconds
Started Feb 25 01:21:26 PM PST 24
Finished Feb 25 01:27:25 PM PST 24
Peak memory 202384 kb
Host smart-9b8dddef-ac35-43d4-9b2d-17762ad0604d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525984003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.1525984003
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.94800937
Short name T635
Test name
Test status
Simulation time 738029092 ps
CPU time 72.65 seconds
Started Feb 25 01:21:28 PM PST 24
Finished Feb 25 01:22:41 PM PST 24
Peak memory 300460 kb
Host smart-b13fb282-34a6-423e-a2f0-b8eb0bccaac3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94800937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.sram_ctrl_throughput_w_partial_write.94800937
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3973862723
Short name T771
Test name
Test status
Simulation time 7216300710 ps
CPU time 140.5 seconds
Started Feb 25 01:21:41 PM PST 24
Finished Feb 25 01:24:01 PM PST 24
Peak memory 310252 kb
Host smart-053ac5f5-59da-42ac-80e5-b9477b61c77a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973862723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.3973862723
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.3495099422
Short name T256
Test name
Test status
Simulation time 31994413 ps
CPU time 0.64 seconds
Started Feb 25 01:21:41 PM PST 24
Finished Feb 25 01:21:42 PM PST 24
Peak memory 202248 kb
Host smart-1ca6f40e-a1d4-4b29-b736-6a9ccccf27b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495099422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.3495099422
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.3263144702
Short name T457
Test name
Test status
Simulation time 132185981511 ps
CPU time 2024.35 seconds
Started Feb 25 01:21:38 PM PST 24
Finished Feb 25 01:55:23 PM PST 24
Peak memory 202400 kb
Host smart-c98b994c-75b9-438b-b2bd-2b1a714a704f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263144702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.3263144702
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.1829317681
Short name T726
Test name
Test status
Simulation time 102084105527 ps
CPU time 97.25 seconds
Started Feb 25 01:21:36 PM PST 24
Finished Feb 25 01:23:13 PM PST 24
Peak memory 210600 kb
Host smart-b3f8a42f-56e2-41c0-9dbd-10d71eae7a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829317681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.1829317681
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.156450523
Short name T451
Test name
Test status
Simulation time 792895499 ps
CPU time 155.76 seconds
Started Feb 25 01:21:38 PM PST 24
Finished Feb 25 01:24:14 PM PST 24
Peak memory 372232 kb
Host smart-9f8b9e44-150e-441b-bd55-58f5f725dd46
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156450523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_max_throughput.156450523
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.141386609
Short name T80
Test name
Test status
Simulation time 5545242678 ps
CPU time 137.32 seconds
Started Feb 25 01:21:35 PM PST 24
Finished Feb 25 01:23:53 PM PST 24
Peak memory 214976 kb
Host smart-79cdaef9-b71f-44ee-aefc-e56af4417f3d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141386609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.141386609
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.2897012089
Short name T120
Test name
Test status
Simulation time 8041113726 ps
CPU time 245.58 seconds
Started Feb 25 01:21:41 PM PST 24
Finished Feb 25 01:25:47 PM PST 24
Peak memory 202600 kb
Host smart-d12e3d0e-800a-4824-b322-8cec24621eb0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897012089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.2897012089
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.2240608600
Short name T308
Test name
Test status
Simulation time 12367330466 ps
CPU time 415.9 seconds
Started Feb 25 01:21:36 PM PST 24
Finished Feb 25 01:28:32 PM PST 24
Peak memory 355836 kb
Host smart-715601b9-2519-4ca3-aa55-6d91101a2c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240608600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.2240608600
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.108824218
Short name T360
Test name
Test status
Simulation time 1390866120 ps
CPU time 173.72 seconds
Started Feb 25 01:21:41 PM PST 24
Finished Feb 25 01:24:34 PM PST 24
Peak memory 369904 kb
Host smart-7ccce435-4da9-4114-ac13-0b156517279a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108824218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s
ram_ctrl_partial_access.108824218
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1769550032
Short name T426
Test name
Test status
Simulation time 25375130079 ps
CPU time 294.72 seconds
Started Feb 25 01:21:35 PM PST 24
Finished Feb 25 01:26:30 PM PST 24
Peak memory 210612 kb
Host smart-c72eb601-37db-48ee-b1cd-222f4c8cf7e6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769550032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1769550032
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.3803968756
Short name T151
Test name
Test status
Simulation time 1354315383 ps
CPU time 6.71 seconds
Started Feb 25 01:21:38 PM PST 24
Finished Feb 25 01:21:45 PM PST 24
Peak memory 202508 kb
Host smart-e18efad0-ad9e-43b1-aa95-162117d8532a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803968756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3803968756
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.1425084825
Short name T692
Test name
Test status
Simulation time 4481387442 ps
CPU time 1252.76 seconds
Started Feb 25 01:21:37 PM PST 24
Finished Feb 25 01:42:30 PM PST 24
Peak memory 379436 kb
Host smart-d631d5af-5436-462a-b21d-6578a3d54d4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425084825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1425084825
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.1755591633
Short name T613
Test name
Test status
Simulation time 1786694058 ps
CPU time 115.33 seconds
Started Feb 25 01:21:39 PM PST 24
Finished Feb 25 01:23:34 PM PST 24
Peak memory 344452 kb
Host smart-817182fa-3e44-4f35-b367-4d5f9b56c6b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755591633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1755591633
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3097023502
Short name T323
Test name
Test status
Simulation time 17338080836 ps
CPU time 339.54 seconds
Started Feb 25 01:21:35 PM PST 24
Finished Feb 25 01:27:15 PM PST 24
Peak memory 202344 kb
Host smart-f3f7c52a-49c5-4526-9b86-1f1a6d69563b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097023502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3097023502
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2258888606
Short name T177
Test name
Test status
Simulation time 1961644193 ps
CPU time 63.3 seconds
Started Feb 25 01:21:38 PM PST 24
Finished Feb 25 01:22:42 PM PST 24
Peak memory 284204 kb
Host smart-6db3fe66-e4fd-4e93-81bf-27b28259dd1e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258888606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2258888606
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1686418692
Short name T520
Test name
Test status
Simulation time 4432442138 ps
CPU time 824.13 seconds
Started Feb 25 01:21:54 PM PST 24
Finished Feb 25 01:35:39 PM PST 24
Peak memory 377276 kb
Host smart-494c2d9c-435c-4d49-b3ec-bcf16ab3c7f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686418692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.1686418692
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.1233491369
Short name T152
Test name
Test status
Simulation time 27207535 ps
CPU time 0.71 seconds
Started Feb 25 01:22:13 PM PST 24
Finished Feb 25 01:22:14 PM PST 24
Peak memory 201876 kb
Host smart-4331b989-8f67-4e99-a60b-15c64b90f10a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233491369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.1233491369
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.2804833745
Short name T734
Test name
Test status
Simulation time 33179435714 ps
CPU time 2203 seconds
Started Feb 25 01:21:55 PM PST 24
Finished Feb 25 01:58:38 PM PST 24
Peak memory 202468 kb
Host smart-8833c83c-251b-44e1-926d-24e6231eb45d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804833745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.2804833745
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.3240538230
Short name T155
Test name
Test status
Simulation time 88221123188 ps
CPU time 209.8 seconds
Started Feb 25 01:21:53 PM PST 24
Finished Feb 25 01:25:23 PM PST 24
Peak memory 294264 kb
Host smart-c96fbd3a-f8da-4c82-9cf1-5015a6c6170a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240538230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.3240538230
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1300661902
Short name T325
Test name
Test status
Simulation time 750970587 ps
CPU time 82.26 seconds
Started Feb 25 01:21:55 PM PST 24
Finished Feb 25 01:23:19 PM PST 24
Peak memory 300512 kb
Host smart-bdc5ab68-a63c-4d6d-a32e-9d41ad93151a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300661902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1300661902
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.4207255218
Short name T678
Test name
Test status
Simulation time 4139316949 ps
CPU time 75.44 seconds
Started Feb 25 01:21:52 PM PST 24
Finished Feb 25 01:23:07 PM PST 24
Peak memory 218764 kb
Host smart-9e67164f-17bf-4ed0-9530-5da884ca6812
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207255218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.4207255218
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.707167450
Short name T553
Test name
Test status
Simulation time 229441366612 ps
CPU time 390.16 seconds
Started Feb 25 01:21:53 PM PST 24
Finished Feb 25 01:28:23 PM PST 24
Peak memory 202456 kb
Host smart-81ac49d5-6e6d-4d9b-8340-948c9cf8e31f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707167450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl
_mem_walk.707167450
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.1338105237
Short name T592
Test name
Test status
Simulation time 108057127164 ps
CPU time 1309.23 seconds
Started Feb 25 01:21:51 PM PST 24
Finished Feb 25 01:43:41 PM PST 24
Peak memory 365060 kb
Host smart-fedee0d4-b88b-48b1-b318-4c3fae3969d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338105237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.1338105237
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.709768129
Short name T277
Test name
Test status
Simulation time 459613732 ps
CPU time 56.14 seconds
Started Feb 25 01:21:49 PM PST 24
Finished Feb 25 01:22:46 PM PST 24
Peak memory 284376 kb
Host smart-38a97a76-aa82-4d3c-a669-b560056e8b2d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709768129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s
ram_ctrl_partial_access.709768129
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.68747429
Short name T282
Test name
Test status
Simulation time 13783075266 ps
CPU time 362.58 seconds
Started Feb 25 01:21:51 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 202352 kb
Host smart-271e4e7b-144a-489f-9ef6-f5f87592ac14
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68747429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_partial_access_b2b.68747429
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.344902184
Short name T776
Test name
Test status
Simulation time 1422333147 ps
CPU time 6.3 seconds
Started Feb 25 01:22:00 PM PST 24
Finished Feb 25 01:22:06 PM PST 24
Peak memory 202560 kb
Host smart-b9c0b7b4-f639-4c5a-b799-8cd98f8eabe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344902184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.344902184
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.629747054
Short name T564
Test name
Test status
Simulation time 6256749357 ps
CPU time 1077.54 seconds
Started Feb 25 01:21:59 PM PST 24
Finished Feb 25 01:39:57 PM PST 24
Peak memory 373096 kb
Host smart-428267d6-87e4-4c5b-ac67-1943c109efc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629747054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.629747054
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3953014969
Short name T747
Test name
Test status
Simulation time 2346377582 ps
CPU time 12.16 seconds
Started Feb 25 01:21:51 PM PST 24
Finished Feb 25 01:22:03 PM PST 24
Peak memory 202428 kb
Host smart-9090320d-e09b-4f45-b207-939360edd1b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953014969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3953014969
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1531786872
Short name T811
Test name
Test status
Simulation time 43051042678 ps
CPU time 411.09 seconds
Started Feb 25 01:21:57 PM PST 24
Finished Feb 25 01:28:48 PM PST 24
Peak memory 202388 kb
Host smart-0966e78f-d765-4216-b267-afd94d4ecb66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531786872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.1531786872
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.911160999
Short name T355
Test name
Test status
Simulation time 1586312830 ps
CPU time 169.09 seconds
Started Feb 25 01:21:52 PM PST 24
Finished Feb 25 01:24:42 PM PST 24
Peak memory 357716 kb
Host smart-9c798abc-7f37-434b-a26e-15a6d5a2e63f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911160999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.911160999
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.4028947802
Short name T593
Test name
Test status
Simulation time 3439684088 ps
CPU time 116.34 seconds
Started Feb 25 01:18:40 PM PST 24
Finished Feb 25 01:20:36 PM PST 24
Peak memory 353568 kb
Host smart-f393d994-d876-4492-a8df-5535651d28ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028947802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.4028947802
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.2263623874
Short name T817
Test name
Test status
Simulation time 161470866 ps
CPU time 0.75 seconds
Started Feb 25 01:18:40 PM PST 24
Finished Feb 25 01:18:41 PM PST 24
Peak memory 201932 kb
Host smart-9e9f6add-b9da-4adf-816c-61cca587e056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263623874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.2263623874
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.3254808183
Short name T207
Test name
Test status
Simulation time 397474224567 ps
CPU time 2279.07 seconds
Started Feb 25 01:18:44 PM PST 24
Finished Feb 25 01:56:43 PM PST 24
Peak memory 202468 kb
Host smart-de3e5b07-8d56-4367-8c5e-3f27357c38b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254808183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
3254808183
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.979106888
Short name T484
Test name
Test status
Simulation time 86653460458 ps
CPU time 660.67 seconds
Started Feb 25 01:18:43 PM PST 24
Finished Feb 25 01:29:44 PM PST 24
Peak memory 374160 kb
Host smart-280b9896-95ca-473e-bbb6-d593f6ed122c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979106888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable
.979106888
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.634642695
Short name T521
Test name
Test status
Simulation time 16130126758 ps
CPU time 101.62 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:20:28 PM PST 24
Peak memory 202360 kb
Host smart-29e7f26f-c50c-4c01-9dae-f92996aa5987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634642695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca
lation.634642695
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.49975226
Short name T819
Test name
Test status
Simulation time 2747902407 ps
CPU time 106.9 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:20:34 PM PST 24
Peak memory 336332 kb
Host smart-47b52eb2-5180-4f45-aeae-ec0e9e2774c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49975226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_max_throughput.49975226
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1771606404
Short name T1
Test name
Test status
Simulation time 5232562422 ps
CPU time 81.68 seconds
Started Feb 25 01:18:37 PM PST 24
Finished Feb 25 01:19:59 PM PST 24
Peak memory 210860 kb
Host smart-339aad67-900b-4285-9b65-cb7c13005f2f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771606404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1771606404
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.3609650412
Short name T757
Test name
Test status
Simulation time 2019762223 ps
CPU time 121.11 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:20:48 PM PST 24
Peak memory 202336 kb
Host smart-d2009d6e-379f-4b75-9827-e2a7cb70eceb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609650412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.3609650412
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.250045988
Short name T459
Test name
Test status
Simulation time 52354003725 ps
CPU time 695.17 seconds
Started Feb 25 01:18:45 PM PST 24
Finished Feb 25 01:30:21 PM PST 24
Peak memory 372144 kb
Host smart-763d80be-f1b6-4d66-a60e-326f14898ba8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250045988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl
e_keys.250045988
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3609637527
Short name T199
Test name
Test status
Simulation time 1933425041 ps
CPU time 70.83 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:19:58 PM PST 24
Peak memory 318756 kb
Host smart-987c62a1-dc14-44a2-ba73-51a2ecf3f63f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609637527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3609637527
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1353082535
Short name T614
Test name
Test status
Simulation time 14293292973 ps
CPU time 252.68 seconds
Started Feb 25 01:18:37 PM PST 24
Finished Feb 25 01:22:50 PM PST 24
Peak memory 202384 kb
Host smart-449e2952-5c94-434d-a1d9-0002006e0fb2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353082535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.1353082535
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.2186483845
Short name T419
Test name
Test status
Simulation time 453015421 ps
CPU time 6.31 seconds
Started Feb 25 01:18:44 PM PST 24
Finished Feb 25 01:18:51 PM PST 24
Peak memory 202564 kb
Host smart-43eabb0e-8580-42ca-91a8-c6cc06de726d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186483845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2186483845
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.3019959414
Short name T280
Test name
Test status
Simulation time 26080957116 ps
CPU time 887.17 seconds
Started Feb 25 01:18:36 PM PST 24
Finished Feb 25 01:33:23 PM PST 24
Peak memory 377256 kb
Host smart-01a985c0-a0ee-4d7d-a7bb-2206eefedfd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019959414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3019959414
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.3058509204
Short name T23
Test name
Test status
Simulation time 144589741 ps
CPU time 2 seconds
Started Feb 25 01:18:40 PM PST 24
Finished Feb 25 01:18:43 PM PST 24
Peak memory 223628 kb
Host smart-e0374903-c890-41d3-a205-de65079c3877
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058509204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.3058509204
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2042310429
Short name T378
Test name
Test status
Simulation time 1601070549 ps
CPU time 14.16 seconds
Started Feb 25 01:18:39 PM PST 24
Finished Feb 25 01:18:53 PM PST 24
Peak memory 202304 kb
Host smart-07dbcf48-ffc4-47bf-ac27-b0d96e313cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042310429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2042310429
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1734192016
Short name T587
Test name
Test status
Simulation time 4905619545 ps
CPU time 215.51 seconds
Started Feb 25 01:18:40 PM PST 24
Finished Feb 25 01:22:16 PM PST 24
Peak memory 202428 kb
Host smart-7bccab20-3701-477d-aae8-5bc95952c3bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734192016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.1734192016
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4188551628
Short name T753
Test name
Test status
Simulation time 1225187078 ps
CPU time 156.31 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:21:24 PM PST 24
Peak memory 347360 kb
Host smart-325b1cc1-ee67-43c1-a6a3-37c783f305bc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188551628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.4188551628
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3074604956
Short name T20
Test name
Test status
Simulation time 4074349088 ps
CPU time 562.35 seconds
Started Feb 25 01:22:04 PM PST 24
Finished Feb 25 01:31:27 PM PST 24
Peak memory 371104 kb
Host smart-3dea9b83-11ae-4e0b-aec9-0903ac20fd43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074604956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.3074604956
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.2981398928
Short name T496
Test name
Test status
Simulation time 27543911 ps
CPU time 0.62 seconds
Started Feb 25 01:22:08 PM PST 24
Finished Feb 25 01:22:08 PM PST 24
Peak memory 202196 kb
Host smart-61ef4c52-7b5b-49b0-9027-9a1044ff7a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981398928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.2981398928
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.3550816789
Short name T145
Test name
Test status
Simulation time 111465531971 ps
CPU time 1938.29 seconds
Started Feb 25 01:22:11 PM PST 24
Finished Feb 25 01:54:30 PM PST 24
Peak memory 202476 kb
Host smart-354a2e41-bf59-483d-b3ef-62ecce7b85f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550816789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.3550816789
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.92300768
Short name T104
Test name
Test status
Simulation time 6886076555 ps
CPU time 100.75 seconds
Started Feb 25 01:22:03 PM PST 24
Finished Feb 25 01:23:45 PM PST 24
Peak memory 290856 kb
Host smart-d6ed997f-27b5-4bd4-a630-3990e2bf649d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92300768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable
.92300768
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.375012171
Short name T565
Test name
Test status
Simulation time 781233269 ps
CPU time 135.72 seconds
Started Feb 25 01:22:09 PM PST 24
Finished Feb 25 01:24:25 PM PST 24
Peak memory 342448 kb
Host smart-14b638f9-9a1f-4d8c-b838-5a05d7fee0b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375012171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.sram_ctrl_max_throughput.375012171
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.772828553
Short name T514
Test name
Test status
Simulation time 17404741002 ps
CPU time 171.52 seconds
Started Feb 25 01:22:03 PM PST 24
Finished Feb 25 01:24:55 PM PST 24
Peak memory 214964 kb
Host smart-eca005e4-4ce5-4074-ba00-c6d0d12c5915
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772828553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.sram_ctrl_mem_partial_access.772828553
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.3313865654
Short name T794
Test name
Test status
Simulation time 2059367812 ps
CPU time 120.89 seconds
Started Feb 25 01:22:09 PM PST 24
Finished Feb 25 01:24:10 PM PST 24
Peak memory 202312 kb
Host smart-cdd2dd81-4bdb-4bcb-9dc7-8a57b7ff592d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313865654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.3313865654
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.2721149236
Short name T557
Test name
Test status
Simulation time 5575355213 ps
CPU time 180.2 seconds
Started Feb 25 01:22:08 PM PST 24
Finished Feb 25 01:25:08 PM PST 24
Peak memory 282148 kb
Host smart-65bd79c1-91c7-4e4f-ac4f-3ccd06d5f279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721149236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.2721149236
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.944820855
Short name T288
Test name
Test status
Simulation time 1584836287 ps
CPU time 32.95 seconds
Started Feb 25 01:22:09 PM PST 24
Finished Feb 25 01:22:42 PM PST 24
Peak memory 202312 kb
Host smart-e72ea7bc-58e3-4cbc-b4d1-6a1c5d2a9aac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944820855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.s
ram_ctrl_partial_access.944820855
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2191842390
Short name T650
Test name
Test status
Simulation time 22973289776 ps
CPU time 509.9 seconds
Started Feb 25 01:22:07 PM PST 24
Finished Feb 25 01:30:37 PM PST 24
Peak memory 202404 kb
Host smart-8752a7ff-7f95-4348-867c-dfd5dfd8365f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191842390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.2191842390
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.2797303252
Short name T222
Test name
Test status
Simulation time 361082580 ps
CPU time 13.34 seconds
Started Feb 25 01:22:07 PM PST 24
Finished Feb 25 01:22:20 PM PST 24
Peak memory 202588 kb
Host smart-84721847-9a1a-4ab7-a952-d0e49d161429
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797303252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2797303252
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.975825033
Short name T779
Test name
Test status
Simulation time 25063397146 ps
CPU time 511.89 seconds
Started Feb 25 01:22:05 PM PST 24
Finished Feb 25 01:30:37 PM PST 24
Peak memory 364912 kb
Host smart-df99f23c-5472-4ee8-ab12-4cbf12af5896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975825033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.975825033
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.3322289413
Short name T797
Test name
Test status
Simulation time 1169315926 ps
CPU time 30.91 seconds
Started Feb 25 01:22:03 PM PST 24
Finished Feb 25 01:22:35 PM PST 24
Peak memory 210564 kb
Host smart-2a76f26e-24ff-488a-a9bd-a799d0a99c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322289413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3322289413
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.179832854
Short name T193
Test name
Test status
Simulation time 16583396663 ps
CPU time 318.77 seconds
Started Feb 25 01:22:07 PM PST 24
Finished Feb 25 01:27:26 PM PST 24
Peak memory 202336 kb
Host smart-5d415007-d524-4864-af52-50dff09fd797
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179832854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.sram_ctrl_stress_pipeline.179832854
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2177658434
Short name T113
Test name
Test status
Simulation time 810179305 ps
CPU time 134.89 seconds
Started Feb 25 01:22:13 PM PST 24
Finished Feb 25 01:24:28 PM PST 24
Peak memory 350580 kb
Host smart-5be05442-160a-409d-951b-0b93db7ece69
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177658434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2177658434
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.547749916
Short name T790
Test name
Test status
Simulation time 15831154623 ps
CPU time 920.71 seconds
Started Feb 25 01:22:17 PM PST 24
Finished Feb 25 01:37:38 PM PST 24
Peak memory 366896 kb
Host smart-202fc140-9498-4c85-ba95-b4129a898446
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547749916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.sram_ctrl_access_during_key_req.547749916
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.789444957
Short name T481
Test name
Test status
Simulation time 20905966 ps
CPU time 0.64 seconds
Started Feb 25 01:22:15 PM PST 24
Finished Feb 25 01:22:16 PM PST 24
Peak memory 202232 kb
Host smart-62e08549-0472-4926-bcb1-de4f2f756dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789444957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.789444957
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.1407717364
Short name T257
Test name
Test status
Simulation time 184387160009 ps
CPU time 1708.44 seconds
Started Feb 25 01:22:05 PM PST 24
Finished Feb 25 01:50:34 PM PST 24
Peak memory 202484 kb
Host smart-edff09db-9ed0-4aaf-9195-0e08127465dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407717364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.1407717364
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.3423101296
Short name T208
Test name
Test status
Simulation time 13621425141 ps
CPU time 79.57 seconds
Started Feb 25 01:22:10 PM PST 24
Finished Feb 25 01:23:30 PM PST 24
Peak memory 210600 kb
Host smart-f1c52a61-de4c-4ffa-82fe-d7a7565b3057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423101296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.3423101296
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.2528954348
Short name T626
Test name
Test status
Simulation time 5674665846 ps
CPU time 114.39 seconds
Started Feb 25 01:22:20 PM PST 24
Finished Feb 25 01:24:15 PM PST 24
Peak memory 329972 kb
Host smart-b45b7661-acf8-42c2-b78c-88094cbf2466
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528954348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.2528954348
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1431581786
Short name T767
Test name
Test status
Simulation time 5018555594 ps
CPU time 80.01 seconds
Started Feb 25 01:22:19 PM PST 24
Finished Feb 25 01:23:39 PM PST 24
Peak memory 218776 kb
Host smart-569a399a-a0fd-45ec-85f5-040b341be965
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431581786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.1431581786
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.1859333050
Short name T598
Test name
Test status
Simulation time 21899339564 ps
CPU time 253.93 seconds
Started Feb 25 01:22:11 PM PST 24
Finished Feb 25 01:26:26 PM PST 24
Peak memory 202800 kb
Host smart-325fbb4b-a0aa-48ad-8de8-9b1bb5612563
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859333050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.1859333050
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.1747857218
Short name T335
Test name
Test status
Simulation time 845836413 ps
CPU time 34.69 seconds
Started Feb 25 01:22:07 PM PST 24
Finished Feb 25 01:22:42 PM PST 24
Peak memory 202296 kb
Host smart-05cb524f-86ab-440f-8ef0-c05375922380
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747857218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.1747857218
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1695357089
Short name T242
Test name
Test status
Simulation time 43674145450 ps
CPU time 371.91 seconds
Started Feb 25 01:22:16 PM PST 24
Finished Feb 25 01:28:28 PM PST 24
Peak memory 202404 kb
Host smart-0e58c7ec-965e-4549-94bb-1d14878ffcec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695357089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.1695357089
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.504533044
Short name T238
Test name
Test status
Simulation time 343684022 ps
CPU time 6.04 seconds
Started Feb 25 01:22:21 PM PST 24
Finished Feb 25 01:22:27 PM PST 24
Peak memory 202512 kb
Host smart-2f005352-ef07-43e1-8636-cd038736614c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504533044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.504533044
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2271949595
Short name T774
Test name
Test status
Simulation time 5270047087 ps
CPU time 617.44 seconds
Started Feb 25 01:22:21 PM PST 24
Finished Feb 25 01:32:39 PM PST 24
Peak memory 370156 kb
Host smart-9a3ad799-2d46-4172-acf5-24561385e43f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271949595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2271949595
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3027815170
Short name T231
Test name
Test status
Simulation time 762782732 ps
CPU time 30.13 seconds
Started Feb 25 01:22:04 PM PST 24
Finished Feb 25 01:22:34 PM PST 24
Peak memory 210548 kb
Host smart-c7efba7d-1af2-4caf-8d6a-6f836fc0038f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027815170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3027815170
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.1583972532
Short name T531
Test name
Test status
Simulation time 814665476541 ps
CPU time 9022.14 seconds
Started Feb 25 01:22:16 PM PST 24
Finished Feb 25 03:52:40 PM PST 24
Peak memory 379324 kb
Host smart-881404b0-868e-4e8a-8eba-c51eb660c994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583972532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.1583972532
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.113093313
Short name T371
Test name
Test status
Simulation time 11900336028 ps
CPU time 445.87 seconds
Started Feb 25 01:22:08 PM PST 24
Finished Feb 25 01:29:34 PM PST 24
Peak memory 202432 kb
Host smart-c6bf98a5-1111-4b9a-9012-81df03a85a5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113093313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.sram_ctrl_stress_pipeline.113093313
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2555739540
Short name T585
Test name
Test status
Simulation time 9201354042 ps
CPU time 60.4 seconds
Started Feb 25 01:22:16 PM PST 24
Finished Feb 25 01:23:17 PM PST 24
Peak memory 303612 kb
Host smart-09b14574-5a1e-4005-9c47-ea8c7a964f75
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555739540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2555739540
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.957952371
Short name T804
Test name
Test status
Simulation time 6421616683 ps
CPU time 933.18 seconds
Started Feb 25 01:22:23 PM PST 24
Finished Feb 25 01:37:56 PM PST 24
Peak memory 378188 kb
Host smart-c7d090c5-dd09-447a-a9b3-32cb64d0f063
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957952371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.sram_ctrl_access_during_key_req.957952371
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.2233584574
Short name T324
Test name
Test status
Simulation time 64942002 ps
CPU time 0.66 seconds
Started Feb 25 01:22:27 PM PST 24
Finished Feb 25 01:22:28 PM PST 24
Peak memory 202156 kb
Host smart-509a6fbd-9a9c-43d8-9934-b52c445c737f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233584574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.2233584574
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.3043968459
Short name T543
Test name
Test status
Simulation time 6903387259 ps
CPU time 485.93 seconds
Started Feb 25 01:22:21 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 202552 kb
Host smart-125e4986-ab6e-4778-bd5d-840b88969131
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043968459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.3043968459
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.488587223
Short name T686
Test name
Test status
Simulation time 10573486817 ps
CPU time 232.09 seconds
Started Feb 25 01:22:20 PM PST 24
Finished Feb 25 01:26:12 PM PST 24
Peak memory 210636 kb
Host smart-34691fcb-14ee-49c1-94de-c097b654aca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488587223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc
alation.488587223
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1194444297
Short name T415
Test name
Test status
Simulation time 808033125 ps
CPU time 163.01 seconds
Started Feb 25 01:22:29 PM PST 24
Finished Feb 25 01:25:12 PM PST 24
Peak memory 360832 kb
Host smart-24b760a6-3a7f-43f1-8cf7-ee282de1a414
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194444297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1194444297
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3781951413
Short name T211
Test name
Test status
Simulation time 1939032518 ps
CPU time 72.7 seconds
Started Feb 25 01:22:20 PM PST 24
Finished Feb 25 01:23:33 PM PST 24
Peak memory 211316 kb
Host smart-9e84b7e3-f47d-4347-a1e2-43ba3d51e000
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781951413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3781951413
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.4093303688
Short name T441
Test name
Test status
Simulation time 4109023222 ps
CPU time 250.85 seconds
Started Feb 25 01:22:21 PM PST 24
Finished Feb 25 01:26:32 PM PST 24
Peak memory 202360 kb
Host smart-e6d8da3c-0cfb-4064-a0c5-005f0eb50a67
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093303688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.4093303688
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.403102114
Short name T215
Test name
Test status
Simulation time 29158719448 ps
CPU time 864.8 seconds
Started Feb 25 01:22:11 PM PST 24
Finished Feb 25 01:36:36 PM PST 24
Peak memory 376136 kb
Host smart-2c2a6ec9-13b4-47ca-ac1b-bacbb0addf7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403102114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip
le_keys.403102114
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1759044900
Short name T612
Test name
Test status
Simulation time 4458368735 ps
CPU time 19.86 seconds
Started Feb 25 01:22:15 PM PST 24
Finished Feb 25 01:22:35 PM PST 24
Peak memory 202316 kb
Host smart-d0f2c4c8-384a-410b-9536-7f67b039fc8d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759044900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1759044900
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3772069809
Short name T561
Test name
Test status
Simulation time 23815211742 ps
CPU time 529.56 seconds
Started Feb 25 01:22:27 PM PST 24
Finished Feb 25 01:31:17 PM PST 24
Peak memory 202356 kb
Host smart-247f0bc5-3ba7-47c2-91e4-41b7c6a937aa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772069809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.3772069809
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2356273356
Short name T595
Test name
Test status
Simulation time 1412360452 ps
CPU time 6.82 seconds
Started Feb 25 01:22:26 PM PST 24
Finished Feb 25 01:22:34 PM PST 24
Peak memory 202476 kb
Host smart-1b3a8ec3-052d-4089-8947-dd4bde8e3403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356273356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2356273356
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.3815447200
Short name T150
Test name
Test status
Simulation time 9109678244 ps
CPU time 819.09 seconds
Started Feb 25 01:22:26 PM PST 24
Finished Feb 25 01:36:06 PM PST 24
Peak memory 379244 kb
Host smart-debf8f61-4204-43b8-96aa-4933ff1ccc35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815447200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3815447200
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.2777928433
Short name T306
Test name
Test status
Simulation time 1923772066 ps
CPU time 124.83 seconds
Started Feb 25 01:22:21 PM PST 24
Finished Feb 25 01:24:26 PM PST 24
Peak memory 358900 kb
Host smart-e9c1a46c-a585-435c-b527-dedcd950bb49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777928433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2777928433
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.642931887
Short name T106
Test name
Test status
Simulation time 116522707904 ps
CPU time 7184.26 seconds
Started Feb 25 01:22:20 PM PST 24
Finished Feb 25 03:22:05 PM PST 24
Peak memory 380492 kb
Host smart-79f81d81-dac5-4349-b2d9-a6605781e908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642931887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_stress_all.642931887
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.41492788
Short name T163
Test name
Test status
Simulation time 2112808430 ps
CPU time 179.47 seconds
Started Feb 25 01:22:18 PM PST 24
Finished Feb 25 01:25:18 PM PST 24
Peak memory 202376 kb
Host smart-e32b3029-1b74-4a46-bbe6-ab08611d9b73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41492788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_stress_pipeline.41492788
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1605143638
Short name T691
Test name
Test status
Simulation time 719712792 ps
CPU time 43.75 seconds
Started Feb 25 01:22:27 PM PST 24
Finished Feb 25 01:23:11 PM PST 24
Peak memory 259984 kb
Host smart-ec436b9b-d71c-4d75-9f67-5fe9b8d25cc6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605143638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1605143638
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.14299265
Short name T523
Test name
Test status
Simulation time 37543697292 ps
CPU time 953.79 seconds
Started Feb 25 01:22:39 PM PST 24
Finished Feb 25 01:38:33 PM PST 24
Peak memory 375624 kb
Host smart-2e060283-aa27-4bb9-9090-5f928e6c697f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14299265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.sram_ctrl_access_during_key_req.14299265
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.3247373051
Short name T615
Test name
Test status
Simulation time 38353143 ps
CPU time 0.64 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:22:49 PM PST 24
Peak memory 202056 kb
Host smart-90eed683-b255-4009-af78-4b9061e11992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247373051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.3247373051
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.613150428
Short name T149
Test name
Test status
Simulation time 402965151428 ps
CPU time 1727.28 seconds
Started Feb 25 01:22:30 PM PST 24
Finished Feb 25 01:51:18 PM PST 24
Peak memory 202616 kb
Host smart-71aaf536-b6e8-44f6-b40c-0a767fada7a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613150428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
613150428
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.394468279
Short name T769
Test name
Test status
Simulation time 19878598786 ps
CPU time 107.73 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:24:36 PM PST 24
Peak memory 210548 kb
Host smart-0242bf93-0d1a-45d4-829a-5512d96510e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394468279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc
alation.394468279
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2316785633
Short name T112
Test name
Test status
Simulation time 734715628 ps
CPU time 63.49 seconds
Started Feb 25 01:22:29 PM PST 24
Finished Feb 25 01:23:33 PM PST 24
Peak memory 300540 kb
Host smart-5708c393-bb7c-4851-a0e3-e7e9ecc3e68a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316785633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2316785633
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.4258651728
Short name T488
Test name
Test status
Simulation time 18095573439 ps
CPU time 76.06 seconds
Started Feb 25 01:22:32 PM PST 24
Finished Feb 25 01:23:49 PM PST 24
Peak memory 211788 kb
Host smart-8f4a18d8-a2cd-4752-b28b-1ef6591f40cc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258651728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.4258651728
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.3042290406
Short name T396
Test name
Test status
Simulation time 27571546497 ps
CPU time 291.03 seconds
Started Feb 25 01:22:39 PM PST 24
Finished Feb 25 01:27:30 PM PST 24
Peak memory 202464 kb
Host smart-a3422840-e97a-4fd3-9814-f910fff5c310
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042290406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.3042290406
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1897829186
Short name T307
Test name
Test status
Simulation time 19930078649 ps
CPU time 1254.93 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:43:44 PM PST 24
Peak memory 378196 kb
Host smart-72f298b2-d698-426a-be82-3b8a9a7740fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897829186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1897829186
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.296214993
Short name T786
Test name
Test status
Simulation time 576458311 ps
CPU time 27.21 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:23:15 PM PST 24
Peak memory 202292 kb
Host smart-00645181-6106-4e63-8925-e270b001a8fe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296214993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s
ram_ctrl_partial_access.296214993
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.795388405
Short name T153
Test name
Test status
Simulation time 17688324799 ps
CPU time 430.97 seconds
Started Feb 25 01:22:31 PM PST 24
Finished Feb 25 01:29:42 PM PST 24
Peak memory 202412 kb
Host smart-f4ebcabc-0eb9-436f-9dd9-1249be4631cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795388405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_partial_access_b2b.795388405
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.589993283
Short name T698
Test name
Test status
Simulation time 1411725841 ps
CPU time 7 seconds
Started Feb 25 01:22:32 PM PST 24
Finished Feb 25 01:22:39 PM PST 24
Peak memory 202560 kb
Host smart-f787757d-9d36-4aed-ac8e-918a8e18635c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589993283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.589993283
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.923129532
Short name T237
Test name
Test status
Simulation time 68872250022 ps
CPU time 1050.06 seconds
Started Feb 25 01:22:32 PM PST 24
Finished Feb 25 01:40:02 PM PST 24
Peak memory 378276 kb
Host smart-11f52f82-2ad6-4233-9f50-37d73d1c74c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923129532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.923129532
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.4064480268
Short name T332
Test name
Test status
Simulation time 1586812143 ps
CPU time 14.3 seconds
Started Feb 25 01:22:34 PM PST 24
Finished Feb 25 01:22:48 PM PST 24
Peak memory 210560 kb
Host smart-7b896e11-9911-4178-b3fc-51731744bd85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064480268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.4064480268
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.980987041
Short name T258
Test name
Test status
Simulation time 236577650388 ps
CPU time 3908.66 seconds
Started Feb 25 01:22:32 PM PST 24
Finished Feb 25 02:27:42 PM PST 24
Peak memory 380348 kb
Host smart-09747875-0262-430e-a1c0-e4ee0740e4d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980987041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_stress_all.980987041
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1689561904
Short name T664
Test name
Test status
Simulation time 4306256660 ps
CPU time 336.5 seconds
Started Feb 25 01:22:32 PM PST 24
Finished Feb 25 01:28:09 PM PST 24
Peak memory 202376 kb
Host smart-29c732dc-a9d3-46de-bdc9-698ddac0697a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689561904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.1689561904
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.722352271
Short name T121
Test name
Test status
Simulation time 2963396456 ps
CPU time 80.61 seconds
Started Feb 25 01:22:33 PM PST 24
Finished Feb 25 01:23:54 PM PST 24
Peak memory 313532 kb
Host smart-d3d76164-249d-42dd-90b4-975f294a8d0c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722352271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.722352271
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3001955867
Short name T729
Test name
Test status
Simulation time 51220944601 ps
CPU time 1620.06 seconds
Started Feb 25 01:22:47 PM PST 24
Finished Feb 25 01:49:47 PM PST 24
Peak memory 362248 kb
Host smart-21063141-aa24-4ed7-985e-66855f023c54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001955867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.3001955867
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.1293578531
Short name T808
Test name
Test status
Simulation time 33409364 ps
CPU time 0.64 seconds
Started Feb 25 01:22:53 PM PST 24
Finished Feb 25 01:22:54 PM PST 24
Peak memory 202260 kb
Host smart-d59156b6-bc2d-49c8-96ac-9322dec51040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293578531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.1293578531
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.2544886003
Short name T602
Test name
Test status
Simulation time 19268512598 ps
CPU time 1341.4 seconds
Started Feb 25 01:22:47 PM PST 24
Finished Feb 25 01:45:08 PM PST 24
Peak memory 202472 kb
Host smart-8adc2e74-ee8b-4594-856c-bf766a5a268f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544886003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.2544886003
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.3589597971
Short name T579
Test name
Test status
Simulation time 27085624483 ps
CPU time 321.18 seconds
Started Feb 25 01:22:46 PM PST 24
Finished Feb 25 01:28:08 PM PST 24
Peak memory 373828 kb
Host smart-05f5a6a4-62ec-466c-a141-3dc695b5580e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589597971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.3589597971
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.3991631953
Short name T412
Test name
Test status
Simulation time 7568283119 ps
CPU time 51.53 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:23:40 PM PST 24
Peak memory 202424 kb
Host smart-a9674003-e255-4e8b-9d5d-773984cd9a31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991631953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.3991631953
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.2461324384
Short name T671
Test name
Test status
Simulation time 4328890747 ps
CPU time 38.14 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:23:26 PM PST 24
Peak memory 251432 kb
Host smart-3fdf7013-2451-4d10-a31a-8b82e4fc7a74
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461324384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.2461324384
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2598602146
Short name T216
Test name
Test status
Simulation time 7763760066 ps
CPU time 128.4 seconds
Started Feb 25 01:23:03 PM PST 24
Finished Feb 25 01:25:12 PM PST 24
Peak memory 214904 kb
Host smart-ce29514f-d93f-4838-ae64-2c98c00f9cff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598602146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.2598602146
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2274863016
Short name T836
Test name
Test status
Simulation time 4108791932 ps
CPU time 244.76 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:26:53 PM PST 24
Peak memory 202300 kb
Host smart-eff391fb-8748-45b4-89ea-9340f4a0a919
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274863016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2274863016
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.968576324
Short name T674
Test name
Test status
Simulation time 39039235296 ps
CPU time 791.99 seconds
Started Feb 25 01:22:48 PM PST 24
Finished Feb 25 01:36:00 PM PST 24
Peak memory 373084 kb
Host smart-cd97d996-1b50-4a39-bd75-5e44201157b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968576324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip
le_keys.968576324
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.929789060
Short name T634
Test name
Test status
Simulation time 2054168181 ps
CPU time 24.67 seconds
Started Feb 25 01:22:46 PM PST 24
Finished Feb 25 01:23:11 PM PST 24
Peak memory 202316 kb
Host smart-fab52214-d5d7-47eb-b03f-abd5f86f38bf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929789060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.s
ram_ctrl_partial_access.929789060
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1799599202
Short name T40
Test name
Test status
Simulation time 132566603615 ps
CPU time 381.73 seconds
Started Feb 25 01:22:56 PM PST 24
Finished Feb 25 01:29:18 PM PST 24
Peak memory 202404 kb
Host smart-8ca8e306-f085-4a09-920a-e2f561f72d50
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799599202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.1799599202
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3842479703
Short name T680
Test name
Test status
Simulation time 1401864139 ps
CPU time 13.88 seconds
Started Feb 25 01:22:47 PM PST 24
Finished Feb 25 01:23:01 PM PST 24
Peak memory 202652 kb
Host smart-54997d7c-2bf6-4231-89eb-77734a9eea84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842479703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3842479703
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.490488834
Short name T699
Test name
Test status
Simulation time 30763675405 ps
CPU time 1246.92 seconds
Started Feb 25 01:22:46 PM PST 24
Finished Feb 25 01:43:33 PM PST 24
Peak memory 376248 kb
Host smart-df323635-6534-4d57-92aa-79a16aefd5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490488834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.490488834
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.506655807
Short name T480
Test name
Test status
Simulation time 1045791061 ps
CPU time 24.84 seconds
Started Feb 25 01:22:33 PM PST 24
Finished Feb 25 01:22:58 PM PST 24
Peak memory 202400 kb
Host smart-6136efc5-bec1-4158-8bdc-1134f4b8a5aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506655807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.506655807
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.795197750
Short name T791
Test name
Test status
Simulation time 65831124916 ps
CPU time 6180.95 seconds
Started Feb 25 01:22:54 PM PST 24
Finished Feb 25 03:05:56 PM PST 24
Peak memory 388584 kb
Host smart-5fd2fb75-0d50-40ba-8351-88e665e5d1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795197750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_stress_all.795197750
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3180595976
Short name T455
Test name
Test status
Simulation time 3585889400 ps
CPU time 243.73 seconds
Started Feb 25 01:22:46 PM PST 24
Finished Feb 25 01:26:50 PM PST 24
Peak memory 202428 kb
Host smart-124140d6-599c-4397-96bf-86c34acbc277
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180595976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.3180595976
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2377424140
Short name T124
Test name
Test status
Simulation time 1602344742 ps
CPU time 27.83 seconds
Started Feb 25 01:22:55 PM PST 24
Finished Feb 25 01:23:23 PM PST 24
Peak memory 213804 kb
Host smart-2a6ba34c-6352-421f-bda7-90faae500127
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377424140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2377424140
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2703465322
Short name T814
Test name
Test status
Simulation time 52287263840 ps
CPU time 1050.75 seconds
Started Feb 25 01:22:55 PM PST 24
Finished Feb 25 01:40:26 PM PST 24
Peak memory 379288 kb
Host smart-ef156154-a812-4008-ba26-d4cfdb5d5637
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703465322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.2703465322
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.105619978
Short name T547
Test name
Test status
Simulation time 25678243 ps
CPU time 0.61 seconds
Started Feb 25 01:23:05 PM PST 24
Finished Feb 25 01:23:05 PM PST 24
Peak memory 201928 kb
Host smart-9048f60a-d674-495e-9582-2f7f91777db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105619978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.105619978
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.67024264
Short name T620
Test name
Test status
Simulation time 81626406811 ps
CPU time 1734.39 seconds
Started Feb 25 01:22:53 PM PST 24
Finished Feb 25 01:51:48 PM PST 24
Peak memory 202432 kb
Host smart-743328d3-95b5-4a16-a7f0-bbdea8d6abf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67024264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.67024264
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.2470215996
Short name T728
Test name
Test status
Simulation time 8069204070 ps
CPU time 89.31 seconds
Started Feb 25 01:22:56 PM PST 24
Finished Feb 25 01:24:25 PM PST 24
Peak memory 210564 kb
Host smart-62a4a801-caaf-4601-b78c-492044ef8453
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470215996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.2470215996
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.1632070771
Short name T330
Test name
Test status
Simulation time 2949780858 ps
CPU time 53.1 seconds
Started Feb 25 01:22:55 PM PST 24
Finished Feb 25 01:23:48 PM PST 24
Peak memory 275000 kb
Host smart-cd6d3ea9-41f1-491b-aaae-8c051a27a0ef
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632070771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.1632070771
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.824256258
Short name T76
Test name
Test status
Simulation time 4553518301 ps
CPU time 148.88 seconds
Started Feb 25 01:23:06 PM PST 24
Finished Feb 25 01:25:36 PM PST 24
Peak memory 211460 kb
Host smart-542bab6f-734b-4150-a369-5f1441198887
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824256258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.824256258
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.3048351753
Short name T392
Test name
Test status
Simulation time 21497230819 ps
CPU time 312.99 seconds
Started Feb 25 01:23:08 PM PST 24
Finished Feb 25 01:28:21 PM PST 24
Peak memory 202460 kb
Host smart-4a3607e3-c093-4107-8e84-a9cbf3fecb83
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048351753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.3048351753
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.4274954777
Short name T651
Test name
Test status
Simulation time 90134728197 ps
CPU time 1403.89 seconds
Started Feb 25 01:22:56 PM PST 24
Finished Feb 25 01:46:20 PM PST 24
Peak memory 379420 kb
Host smart-bff2e73b-633b-4660-a237-48eb487ffc37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274954777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.4274954777
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.2951920956
Short name T165
Test name
Test status
Simulation time 598211836 ps
CPU time 25.71 seconds
Started Feb 25 01:23:03 PM PST 24
Finished Feb 25 01:23:28 PM PST 24
Peak memory 266632 kb
Host smart-b13caacd-a0c8-4cbd-b71b-feb1f31c47fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951920956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.2951920956
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2130576564
Short name T361
Test name
Test status
Simulation time 97548971123 ps
CPU time 471.84 seconds
Started Feb 25 01:22:55 PM PST 24
Finished Feb 25 01:30:47 PM PST 24
Peak memory 202400 kb
Host smart-0adc1b25-f5a2-4514-aab3-e62dc11e70a3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130576564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.2130576564
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2167263646
Short name T712
Test name
Test status
Simulation time 517565215 ps
CPU time 5.41 seconds
Started Feb 25 01:22:58 PM PST 24
Finished Feb 25 01:23:04 PM PST 24
Peak memory 202556 kb
Host smart-153ea46a-28e4-4694-82c5-f57ec07087ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167263646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2167263646
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.2266635081
Short name T619
Test name
Test status
Simulation time 2705990281 ps
CPU time 375.2 seconds
Started Feb 25 01:23:03 PM PST 24
Finished Feb 25 01:29:19 PM PST 24
Peak memory 373132 kb
Host smart-ea61acc5-34d3-4a79-ad3d-b3aa47592033
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266635081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2266635081
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3725294326
Short name T423
Test name
Test status
Simulation time 3499159316 ps
CPU time 28.66 seconds
Started Feb 25 01:23:03 PM PST 24
Finished Feb 25 01:23:32 PM PST 24
Peak memory 202476 kb
Host smart-f6c88822-5ada-42e1-b106-cbb3ccd4ec34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725294326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3725294326
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2101471884
Short name T390
Test name
Test status
Simulation time 2093322176 ps
CPU time 161.11 seconds
Started Feb 25 01:22:57 PM PST 24
Finished Feb 25 01:25:38 PM PST 24
Peak memory 202380 kb
Host smart-3c669d94-b503-4194-9d82-b176d48d365c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101471884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.2101471884
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3334533456
Short name T169
Test name
Test status
Simulation time 1017594438 ps
CPU time 94.58 seconds
Started Feb 25 01:22:54 PM PST 24
Finished Feb 25 01:24:29 PM PST 24
Peak memory 328108 kb
Host smart-935c042c-e6a3-4d47-9fe0-a5a18c73c3f1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334533456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3334533456
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2820984429
Short name T321
Test name
Test status
Simulation time 3620352306 ps
CPU time 778.11 seconds
Started Feb 25 01:23:05 PM PST 24
Finished Feb 25 01:36:03 PM PST 24
Peak memory 377252 kb
Host smart-bbfaa623-d640-4f2f-b114-d280865f2d2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820984429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.2820984429
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.4027894788
Short name T512
Test name
Test status
Simulation time 70555066 ps
CPU time 0.66 seconds
Started Feb 25 01:23:12 PM PST 24
Finished Feb 25 01:23:13 PM PST 24
Peak memory 202264 kb
Host smart-b61d5312-001b-4568-aa2f-2f505a213a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027894788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.4027894788
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.2005406741
Short name T662
Test name
Test status
Simulation time 145497089898 ps
CPU time 2096.47 seconds
Started Feb 25 01:23:06 PM PST 24
Finished Feb 25 01:58:03 PM PST 24
Peak memory 202452 kb
Host smart-6e915cd0-c737-4c47-a9d2-c1ed8c13ef08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005406741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.2005406741
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.672340712
Short name T285
Test name
Test status
Simulation time 29212890747 ps
CPU time 158.46 seconds
Started Feb 25 01:23:08 PM PST 24
Finished Feb 25 01:25:47 PM PST 24
Peak memory 367948 kb
Host smart-7316e5b4-7ccf-4c87-b7f5-fddd2154072d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672340712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl
e.672340712
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.2778468415
Short name T780
Test name
Test status
Simulation time 3393212427 ps
CPU time 46.92 seconds
Started Feb 25 01:23:04 PM PST 24
Finished Feb 25 01:23:52 PM PST 24
Peak memory 210688 kb
Host smart-fd8ece54-37b8-4407-a45f-ea6d4bead42d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778468415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.2778468415
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.3634939120
Short name T536
Test name
Test status
Simulation time 701987085 ps
CPU time 32.04 seconds
Started Feb 25 01:23:07 PM PST 24
Finished Feb 25 01:23:39 PM PST 24
Peak memory 235096 kb
Host smart-a0218045-19ab-40e9-b59f-16da731a92b5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634939120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.3634939120
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1923544714
Short name T367
Test name
Test status
Simulation time 3807228464 ps
CPU time 75.81 seconds
Started Feb 25 01:23:12 PM PST 24
Finished Feb 25 01:24:28 PM PST 24
Peak memory 211640 kb
Host smart-2ba24f20-1049-432e-9225-1f89a7d7e3aa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923544714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.1923544714
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1747109825
Short name T200
Test name
Test status
Simulation time 1991382770 ps
CPU time 114.19 seconds
Started Feb 25 01:23:20 PM PST 24
Finished Feb 25 01:25:15 PM PST 24
Peak memory 202264 kb
Host smart-4f993097-20cf-4a9d-9f12-3b241eda6afc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747109825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1747109825
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.1381377199
Short name T641
Test name
Test status
Simulation time 234888673085 ps
CPU time 1038.01 seconds
Started Feb 25 01:23:03 PM PST 24
Finished Feb 25 01:40:21 PM PST 24
Peak memory 373192 kb
Host smart-33353367-42e4-4c78-9ea7-a0b2c639f031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381377199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.1381377199
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.1733794752
Short name T510
Test name
Test status
Simulation time 786790641 ps
CPU time 52.16 seconds
Started Feb 25 01:23:02 PM PST 24
Finished Feb 25 01:23:55 PM PST 24
Peak memory 276956 kb
Host smart-3a147a4f-45b4-4257-9821-29f25ae0b8c8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733794752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.1733794752
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1550863601
Short name T109
Test name
Test status
Simulation time 39526528707 ps
CPU time 442.04 seconds
Started Feb 25 01:23:04 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 202308 kb
Host smart-1dc2e3d9-e992-4634-93fe-d785a107cc3b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550863601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.1550863601
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1909992144
Short name T118
Test name
Test status
Simulation time 360912407 ps
CPU time 5.33 seconds
Started Feb 25 01:23:12 PM PST 24
Finished Feb 25 01:23:18 PM PST 24
Peak memory 202484 kb
Host smart-e698757a-75c7-4dc7-b328-dc6c250e04c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909992144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1909992144
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.3660406495
Short name T293
Test name
Test status
Simulation time 6250485505 ps
CPU time 406.44 seconds
Started Feb 25 01:23:14 PM PST 24
Finished Feb 25 01:30:00 PM PST 24
Peak memory 324332 kb
Host smart-526b9b0d-bdee-4716-8059-cd8f307b23c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660406495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3660406495
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.3757075986
Short name T470
Test name
Test status
Simulation time 1578487978 ps
CPU time 30.78 seconds
Started Feb 25 01:23:03 PM PST 24
Finished Feb 25 01:23:34 PM PST 24
Peak memory 202408 kb
Host smart-120d17ef-f7c4-4d85-8935-a3ffc4902b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757075986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3757075986
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.1241864223
Short name T663
Test name
Test status
Simulation time 959579011890 ps
CPU time 2190.85 seconds
Started Feb 25 01:23:12 PM PST 24
Finished Feb 25 01:59:44 PM PST 24
Peak memory 218812 kb
Host smart-a2faed2f-fc2d-4fe6-9804-ed1246c03a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241864223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.1241864223
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.308455200
Short name T556
Test name
Test status
Simulation time 1689078757 ps
CPU time 122.13 seconds
Started Feb 25 01:23:07 PM PST 24
Finished Feb 25 01:25:09 PM PST 24
Peak memory 202324 kb
Host smart-667052ea-87d7-4c6d-8b47-4fd255674af2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308455200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_stress_pipeline.308455200
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4201725230
Short name T497
Test name
Test status
Simulation time 2831989695 ps
CPU time 29.02 seconds
Started Feb 25 01:23:05 PM PST 24
Finished Feb 25 01:23:34 PM PST 24
Peak memory 218840 kb
Host smart-a19e4b7a-d183-4942-9d43-03d413176790
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201725230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.4201725230
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2163076123
Short name T301
Test name
Test status
Simulation time 24691560423 ps
CPU time 2294.78 seconds
Started Feb 25 01:23:23 PM PST 24
Finished Feb 25 02:01:38 PM PST 24
Peak memory 378244 kb
Host smart-b129a7f2-1d8d-4587-a3f9-593792d1003a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163076123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.2163076123
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.578366853
Short name T402
Test name
Test status
Simulation time 11275230 ps
CPU time 0.67 seconds
Started Feb 25 01:23:25 PM PST 24
Finished Feb 25 01:23:26 PM PST 24
Peak memory 201932 kb
Host smart-bb300c73-9d1b-48b9-ba32-a02f177d8893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578366853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.578366853
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.2812255353
Short name T788
Test name
Test status
Simulation time 105243668153 ps
CPU time 1825.62 seconds
Started Feb 25 01:23:20 PM PST 24
Finished Feb 25 01:53:46 PM PST 24
Peak memory 202452 kb
Host smart-685c8c5f-f940-4a95-b2a5-aebf316274cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812255353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.2812255353
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.1712651116
Short name T286
Test name
Test status
Simulation time 1066565268 ps
CPU time 11.51 seconds
Started Feb 25 01:23:24 PM PST 24
Finished Feb 25 01:23:36 PM PST 24
Peak memory 202276 kb
Host smart-b3ad4744-7a33-484a-9666-9eccd86bddd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712651116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.1712651116
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3624005345
Short name T511
Test name
Test status
Simulation time 3036549905 ps
CPU time 91.74 seconds
Started Feb 25 01:23:11 PM PST 24
Finished Feb 25 01:24:43 PM PST 24
Peak memory 308908 kb
Host smart-fedf44ac-f8ca-41b9-8cb5-06dedaa3116e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624005345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3624005345
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3057407062
Short name T567
Test name
Test status
Simulation time 1558982762 ps
CPU time 135.81 seconds
Started Feb 25 01:23:25 PM PST 24
Finished Feb 25 01:25:41 PM PST 24
Peak memory 218708 kb
Host smart-89bbcfa8-504d-483c-9a02-91fdf5bf1fa8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057407062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.3057407062
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.4000615823
Short name T453
Test name
Test status
Simulation time 32076547815 ps
CPU time 291.92 seconds
Started Feb 25 01:23:25 PM PST 24
Finished Feb 25 01:28:17 PM PST 24
Peak memory 202472 kb
Host smart-fcbbcb96-f8ce-4d72-a0c9-3d905389e53d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000615823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.4000615823
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.2844450878
Short name T622
Test name
Test status
Simulation time 9555512860 ps
CPU time 664.05 seconds
Started Feb 25 01:23:12 PM PST 24
Finished Feb 25 01:34:17 PM PST 24
Peak memory 373132 kb
Host smart-beacc93e-24f4-44eb-b437-5cac4e10369e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844450878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.2844450878
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.627137916
Short name T566
Test name
Test status
Simulation time 3048319652 ps
CPU time 12.88 seconds
Started Feb 25 01:23:20 PM PST 24
Finished Feb 25 01:23:32 PM PST 24
Peak memory 211032 kb
Host smart-f0a88a3b-fbca-46d3-8844-3809ddc32bfe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627137916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s
ram_ctrl_partial_access.627137916
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2099154030
Short name T210
Test name
Test status
Simulation time 12730739834 ps
CPU time 407.97 seconds
Started Feb 25 01:23:11 PM PST 24
Finished Feb 25 01:29:59 PM PST 24
Peak memory 202384 kb
Host smart-7b8245ca-4a15-423b-9dc6-8c514d475adf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099154030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.2099154030
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.4226227555
Short name T260
Test name
Test status
Simulation time 1348447538 ps
CPU time 6.92 seconds
Started Feb 25 01:23:22 PM PST 24
Finished Feb 25 01:23:29 PM PST 24
Peak memory 202468 kb
Host smart-fe3eedd2-173a-43ca-885c-aca213645274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226227555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.4226227555
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.58082077
Short name T542
Test name
Test status
Simulation time 12268030482 ps
CPU time 863.48 seconds
Started Feb 25 01:23:21 PM PST 24
Finished Feb 25 01:37:45 PM PST 24
Peak memory 375184 kb
Host smart-03cea913-3946-4af9-921d-fdbefa88270b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58082077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.58082077
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.1645226870
Short name T467
Test name
Test status
Simulation time 1396903385 ps
CPU time 23.71 seconds
Started Feb 25 01:23:20 PM PST 24
Finished Feb 25 01:23:44 PM PST 24
Peak memory 210504 kb
Host smart-b1b94e26-88ec-4ec5-9a71-51210e58a1e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645226870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1645226870
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.3064048568
Short name T538
Test name
Test status
Simulation time 129847778362 ps
CPU time 2076.4 seconds
Started Feb 25 01:23:25 PM PST 24
Finished Feb 25 01:58:02 PM PST 24
Peak memory 382372 kb
Host smart-385629bb-0a10-40b3-b326-bad56801c465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064048568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.3064048568
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1191845048
Short name T799
Test name
Test status
Simulation time 61615538402 ps
CPU time 405.13 seconds
Started Feb 25 01:23:12 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 202384 kb
Host smart-ff6f4651-0eb9-46a2-b6da-e104a9993077
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191845048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1191845048
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.523275795
Short name T168
Test name
Test status
Simulation time 825133514 ps
CPU time 125.23 seconds
Started Feb 25 01:23:23 PM PST 24
Finished Feb 25 01:25:28 PM PST 24
Peak memory 354700 kb
Host smart-9eea1dbc-1e02-48c2-9c35-5f98ffb16e2c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523275795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.523275795
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1779994476
Short name T337
Test name
Test status
Simulation time 29985956369 ps
CPU time 693.58 seconds
Started Feb 25 01:23:36 PM PST 24
Finished Feb 25 01:35:10 PM PST 24
Peak memory 362936 kb
Host smart-05071fe2-6891-42b2-9d2d-8b9cbbf54749
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779994476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.1779994476
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1272990403
Short name T268
Test name
Test status
Simulation time 139823927 ps
CPU time 0.66 seconds
Started Feb 25 01:23:36 PM PST 24
Finished Feb 25 01:23:37 PM PST 24
Peak memory 201912 kb
Host smart-c79b1add-febf-4861-a9c6-5c1809ce518e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272990403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1272990403
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.2318782483
Short name T410
Test name
Test status
Simulation time 124531026195 ps
CPU time 2168.32 seconds
Started Feb 25 01:23:25 PM PST 24
Finished Feb 25 01:59:33 PM PST 24
Peak memory 202392 kb
Host smart-8a7470b6-9545-4885-82a6-8341b8745162
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318782483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.2318782483
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.2334216998
Short name T212
Test name
Test status
Simulation time 17140733281 ps
CPU time 189.61 seconds
Started Feb 25 01:23:36 PM PST 24
Finished Feb 25 01:26:46 PM PST 24
Peak memory 210616 kb
Host smart-1c28105e-ca84-42ef-8ac7-75b4974013e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334216998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.2334216998
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.3712712156
Short name T475
Test name
Test status
Simulation time 5066273195 ps
CPU time 48.73 seconds
Started Feb 25 01:23:24 PM PST 24
Finished Feb 25 01:24:12 PM PST 24
Peak memory 272084 kb
Host smart-a7d4e161-8bef-4acd-aa66-d0ada84b4a9c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712712156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.3712712156
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1127318679
Short name T205
Test name
Test status
Simulation time 1971174753 ps
CPU time 70.07 seconds
Started Feb 25 01:23:38 PM PST 24
Finished Feb 25 01:24:49 PM PST 24
Peak memory 211372 kb
Host smart-05064ce7-f152-47eb-ac93-160558d381ce
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127318679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.1127318679
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.2792796369
Short name T9
Test name
Test status
Simulation time 2059763649 ps
CPU time 124.24 seconds
Started Feb 25 01:23:37 PM PST 24
Finished Feb 25 01:25:42 PM PST 24
Peak memory 202228 kb
Host smart-323fdd53-7c6a-4456-823b-7e8ee5538ca0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792796369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.2792796369
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.953277425
Short name T636
Test name
Test status
Simulation time 14526578681 ps
CPU time 467.48 seconds
Started Feb 25 01:23:25 PM PST 24
Finished Feb 25 01:31:13 PM PST 24
Peak memory 378300 kb
Host smart-11d47486-2ab7-437a-8739-de950ba0295f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953277425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.953277425
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.437095168
Short name T539
Test name
Test status
Simulation time 16719464417 ps
CPU time 30.77 seconds
Started Feb 25 01:23:22 PM PST 24
Finished Feb 25 01:23:53 PM PST 24
Peak memory 210544 kb
Host smart-ee262f2d-a484-4536-ad6e-8e911ed08d50
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437095168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s
ram_ctrl_partial_access.437095168
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1826823321
Short name T571
Test name
Test status
Simulation time 63364210204 ps
CPU time 387.04 seconds
Started Feb 25 01:23:25 PM PST 24
Finished Feb 25 01:29:52 PM PST 24
Peak memory 202296 kb
Host smart-81888df6-2bc6-449c-a878-6f7761663ee3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826823321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.1826823321
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.2283965532
Short name T376
Test name
Test status
Simulation time 353198550 ps
CPU time 5.62 seconds
Started Feb 25 01:23:36 PM PST 24
Finished Feb 25 01:23:42 PM PST 24
Peak memory 202496 kb
Host smart-aae1e049-0741-40cb-b52e-9fd484772a6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283965532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2283965532
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2262934985
Short name T302
Test name
Test status
Simulation time 41653731438 ps
CPU time 425.72 seconds
Started Feb 25 01:23:38 PM PST 24
Finished Feb 25 01:30:44 PM PST 24
Peak memory 326076 kb
Host smart-9e5c2232-a944-4fbe-9e47-a06cf77c4cf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262934985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2262934985
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.3704762834
Short name T425
Test name
Test status
Simulation time 3547530810 ps
CPU time 40.54 seconds
Started Feb 25 01:23:22 PM PST 24
Finished Feb 25 01:24:02 PM PST 24
Peak memory 210660 kb
Host smart-91b0d3a0-7e7a-463f-8436-a480356a1f39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704762834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3704762834
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1816081020
Short name T563
Test name
Test status
Simulation time 16163677174 ps
CPU time 200.06 seconds
Started Feb 25 01:23:23 PM PST 24
Finished Feb 25 01:26:44 PM PST 24
Peak memory 202368 kb
Host smart-82df3bd7-6733-475f-a821-27de7a1c05cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816081020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.1816081020
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3310591397
Short name T763
Test name
Test status
Simulation time 6881036729 ps
CPU time 94.38 seconds
Started Feb 25 01:23:35 PM PST 24
Finished Feb 25 01:25:10 PM PST 24
Peak memory 336344 kb
Host smart-6a5f7e7a-6285-4587-bfbe-d518b61197ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310591397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.3310591397
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1503552636
Short name T773
Test name
Test status
Simulation time 18861716996 ps
CPU time 1693.19 seconds
Started Feb 25 01:23:50 PM PST 24
Finished Feb 25 01:52:04 PM PST 24
Peak memory 377236 kb
Host smart-7c7b5247-5207-4a13-8259-22ff4958c04b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503552636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.1503552636
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.3918722674
Short name T648
Test name
Test status
Simulation time 121877364 ps
CPU time 0.65 seconds
Started Feb 25 01:23:51 PM PST 24
Finished Feb 25 01:23:51 PM PST 24
Peak memory 201884 kb
Host smart-2c73ed0d-8ab0-4622-be12-a247440615c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918722674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.3918722674
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.943928695
Short name T607
Test name
Test status
Simulation time 33140953197 ps
CPU time 2253.78 seconds
Started Feb 25 01:23:40 PM PST 24
Finished Feb 25 02:01:14 PM PST 24
Peak memory 202476 kb
Host smart-2db9f5b5-3c4e-4687-90da-23f6e283a1b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943928695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.
943928695
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.988484964
Short name T263
Test name
Test status
Simulation time 12781594698 ps
CPU time 73.38 seconds
Started Feb 25 01:23:50 PM PST 24
Finished Feb 25 01:25:04 PM PST 24
Peak memory 210604 kb
Host smart-a80acdb5-bd9b-402b-9d02-0430633ad4cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988484964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc
alation.988484964
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3923517527
Short name T807
Test name
Test status
Simulation time 793630920 ps
CPU time 153.49 seconds
Started Feb 25 01:23:52 PM PST 24
Finished Feb 25 01:26:26 PM PST 24
Peak memory 353680 kb
Host smart-1054c44e-7286-4364-93fb-ef1982ffb3f8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923517527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3923517527
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.1352693981
Short name T354
Test name
Test status
Simulation time 4508482471 ps
CPU time 83.57 seconds
Started Feb 25 01:23:50 PM PST 24
Finished Feb 25 01:25:14 PM PST 24
Peak memory 211420 kb
Host smart-414578c9-8266-4180-8d0a-166e373d1dc0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352693981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.1352693981
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.1728327941
Short name T93
Test name
Test status
Simulation time 8958294505 ps
CPU time 151.51 seconds
Started Feb 25 01:23:50 PM PST 24
Finished Feb 25 01:26:22 PM PST 24
Peak memory 202776 kb
Host smart-1e2bc115-2cdd-4419-8116-c262995f93b1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728327941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.1728327941
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3792662777
Short name T271
Test name
Test status
Simulation time 12165449358 ps
CPU time 222.03 seconds
Started Feb 25 01:23:37 PM PST 24
Finished Feb 25 01:27:20 PM PST 24
Peak memory 300604 kb
Host smart-936133ed-6835-4af3-9c61-56e14795e0e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792662777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3792662777
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.3952569792
Short name T623
Test name
Test status
Simulation time 5407352187 ps
CPU time 56.54 seconds
Started Feb 25 01:23:52 PM PST 24
Finished Feb 25 01:24:49 PM PST 24
Peak memory 285196 kb
Host smart-5348f0e8-84dd-4d6c-a00a-6e995172247a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952569792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.3952569792
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.86648325
Short name T243
Test name
Test status
Simulation time 73174999974 ps
CPU time 241.82 seconds
Started Feb 25 01:23:50 PM PST 24
Finished Feb 25 01:27:52 PM PST 24
Peak memory 202384 kb
Host smart-929f61e3-021e-422b-9eeb-28658199083a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86648325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_partial_access_b2b.86648325
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.4147865846
Short name T721
Test name
Test status
Simulation time 1417624096 ps
CPU time 13.93 seconds
Started Feb 25 01:23:49 PM PST 24
Finished Feb 25 01:24:03 PM PST 24
Peak memory 202664 kb
Host smart-3a21e638-05ef-417e-bffe-10e9a717d1ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147865846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.4147865846
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.1931714430
Short name T494
Test name
Test status
Simulation time 24667188155 ps
CPU time 355.2 seconds
Started Feb 25 01:23:52 PM PST 24
Finished Feb 25 01:29:48 PM PST 24
Peak memory 377248 kb
Host smart-54b9e0ab-7f6b-4b0d-8c56-9db97e114b1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931714430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1931714430
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.2208352645
Short name T545
Test name
Test status
Simulation time 423527316 ps
CPU time 68.25 seconds
Started Feb 25 01:23:38 PM PST 24
Finished Feb 25 01:24:46 PM PST 24
Peak memory 327996 kb
Host smart-ff6c6a02-a3aa-4158-a4de-037428841b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208352645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2208352645
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.2247114159
Short name T830
Test name
Test status
Simulation time 739274829765 ps
CPU time 4183.9 seconds
Started Feb 25 01:23:50 PM PST 24
Finished Feb 25 02:33:34 PM PST 24
Peak memory 378284 kb
Host smart-635c6caa-fcaa-460e-a1bc-022e8190a703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247114159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.2247114159
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1952621709
Short name T806
Test name
Test status
Simulation time 3579000649 ps
CPU time 269.95 seconds
Started Feb 25 01:23:39 PM PST 24
Finished Feb 25 01:28:09 PM PST 24
Peak memory 202468 kb
Host smart-08aa0436-21ab-4759-a837-c00703811406
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952621709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.1952621709
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3867397608
Short name T114
Test name
Test status
Simulation time 801318128 ps
CPU time 74.68 seconds
Started Feb 25 01:23:50 PM PST 24
Finished Feb 25 01:25:04 PM PST 24
Peak memory 312200 kb
Host smart-7a38da77-a8d3-44d6-b985-418cfdc644a8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867397608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3867397608
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3471687873
Short name T456
Test name
Test status
Simulation time 6274022631 ps
CPU time 935.01 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:34:23 PM PST 24
Peak memory 380196 kb
Host smart-181552a5-4244-4873-af5c-058db4a114dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471687873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.3471687873
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.2153899514
Short name T735
Test name
Test status
Simulation time 22921113 ps
CPU time 0.7 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:18:48 PM PST 24
Peak memory 201888 kb
Host smart-f63ec6f3-a569-4066-adf4-3132033ca38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153899514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.2153899514
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2917315171
Short name T372
Test name
Test status
Simulation time 6916102854 ps
CPU time 477.03 seconds
Started Feb 25 01:18:39 PM PST 24
Finished Feb 25 01:26:37 PM PST 24
Peak memory 202492 kb
Host smart-3f3a4e11-c7c4-4697-bd5f-45ecb6d98553
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917315171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2917315171
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.2559549411
Short name T29
Test name
Test status
Simulation time 12639557052 ps
CPU time 130.9 seconds
Started Feb 25 01:18:46 PM PST 24
Finished Feb 25 01:20:57 PM PST 24
Peak memory 210620 kb
Host smart-f8f249c4-dd18-4ab3-89a9-00c21c598d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559549411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.2559549411
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.274935384
Short name T418
Test name
Test status
Simulation time 2853933423 ps
CPU time 56.4 seconds
Started Feb 25 01:18:40 PM PST 24
Finished Feb 25 01:19:36 PM PST 24
Peak memory 284248 kb
Host smart-56fc872c-2eca-4b7f-b7f8-aafd89131b60
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274935384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.sram_ctrl_max_throughput.274935384
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1110828348
Short name T79
Test name
Test status
Simulation time 9375301095 ps
CPU time 76.94 seconds
Started Feb 25 01:18:40 PM PST 24
Finished Feb 25 01:19:58 PM PST 24
Peak memory 210600 kb
Host smart-5ebf724f-9e90-4345-9280-1800fd3786ad
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110828348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.1110828348
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.2501671538
Short name T142
Test name
Test status
Simulation time 14370711479 ps
CPU time 271.85 seconds
Started Feb 25 01:18:40 PM PST 24
Finished Feb 25 01:23:12 PM PST 24
Peak memory 202404 kb
Host smart-59aef392-831e-43b9-bb35-e88bbb910d6a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501671538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.2501671538
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1687651872
Short name T530
Test name
Test status
Simulation time 2598244620 ps
CPU time 552.73 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:28:00 PM PST 24
Peak memory 369184 kb
Host smart-ca33e9ec-3c45-4e90-bf67-a6d11d61698f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687651872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1687651872
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.1842301170
Short name T129
Test name
Test status
Simulation time 8655796120 ps
CPU time 185.53 seconds
Started Feb 25 01:18:44 PM PST 24
Finished Feb 25 01:21:50 PM PST 24
Peak memory 374060 kb
Host smart-ef567957-158b-4bad-8f3d-f5dd13eef229
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842301170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.1842301170
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2277869480
Short name T397
Test name
Test status
Simulation time 14519348404 ps
CPU time 210.94 seconds
Started Feb 25 01:18:46 PM PST 24
Finished Feb 25 01:22:17 PM PST 24
Peak memory 202376 kb
Host smart-2faffa67-8a93-47cf-8944-0640ed95131b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277869480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.2277869480
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.753494377
Short name T338
Test name
Test status
Simulation time 17598104227 ps
CPU time 1099.27 seconds
Started Feb 25 01:18:45 PM PST 24
Finished Feb 25 01:37:04 PM PST 24
Peak memory 373228 kb
Host smart-4312c85d-019b-446f-9f30-de797a20e86c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753494377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.753494377
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.1558427581
Short name T36
Test name
Test status
Simulation time 766845810 ps
CPU time 2.87 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:18:53 PM PST 24
Peak memory 221128 kb
Host smart-4e088371-0484-4a4d-80aa-6fd05033fdac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558427581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.1558427581
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.3291101082
Short name T382
Test name
Test status
Simulation time 1500834490 ps
CPU time 6.16 seconds
Started Feb 25 01:18:38 PM PST 24
Finished Feb 25 01:18:44 PM PST 24
Peak memory 202300 kb
Host smart-84bb1bea-5f0d-4116-b135-377fdb1b0090
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291101082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3291101082
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2420367153
Short name T775
Test name
Test status
Simulation time 3313046898 ps
CPU time 242.1 seconds
Started Feb 25 01:18:39 PM PST 24
Finished Feb 25 01:22:42 PM PST 24
Peak memory 202336 kb
Host smart-ffc0f79e-8159-4088-86e1-62b659c1c145
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420367153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.2420367153
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1080484040
Short name T414
Test name
Test status
Simulation time 728349389 ps
CPU time 27.75 seconds
Started Feb 25 01:18:45 PM PST 24
Finished Feb 25 01:19:13 PM PST 24
Peak memory 218752 kb
Host smart-25c4e791-d79f-489a-b497-9b7e67d555cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080484040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1080484040
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3435968092
Short name T383
Test name
Test status
Simulation time 11702560625 ps
CPU time 1303.45 seconds
Started Feb 25 01:23:57 PM PST 24
Finished Feb 25 01:45:41 PM PST 24
Peak memory 377228 kb
Host smart-c9621758-a56a-485f-ae37-7303c51dea3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435968092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.3435968092
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.4035949741
Short name T693
Test name
Test status
Simulation time 12541178 ps
CPU time 0.6 seconds
Started Feb 25 01:23:56 PM PST 24
Finished Feb 25 01:23:57 PM PST 24
Peak memory 201884 kb
Host smart-e759557f-61bc-44c1-8a6b-4147df899054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035949741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.4035949741
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.2656760268
Short name T465
Test name
Test status
Simulation time 143716371950 ps
CPU time 2234.57 seconds
Started Feb 25 01:23:57 PM PST 24
Finished Feb 25 02:01:12 PM PST 24
Peak memory 202496 kb
Host smart-3517965b-75e6-42ec-826b-24e3dd5ac681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656760268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.2656760268
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.2809008657
Short name T409
Test name
Test status
Simulation time 42922781772 ps
CPU time 111.25 seconds
Started Feb 25 01:23:59 PM PST 24
Finished Feb 25 01:25:50 PM PST 24
Peak memory 210548 kb
Host smart-f4c54155-a4fa-45fc-bfc3-854aa48d4fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809008657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.2809008657
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.4144800469
Short name T233
Test name
Test status
Simulation time 1541372157 ps
CPU time 139.31 seconds
Started Feb 25 01:23:56 PM PST 24
Finished Feb 25 01:26:15 PM PST 24
Peak memory 348540 kb
Host smart-3e4392f8-6d99-491e-bf06-ad8e10b31bd6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144800469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.4144800469
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.502414077
Short name T652
Test name
Test status
Simulation time 5443974473 ps
CPU time 85.03 seconds
Started Feb 25 01:24:00 PM PST 24
Finished Feb 25 01:25:25 PM PST 24
Peak memory 211564 kb
Host smart-eaf81e07-e6df-4d74-b55e-31da5c146aaf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502414077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_mem_partial_access.502414077
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.3959982521
Short name T195
Test name
Test status
Simulation time 2037656088 ps
CPU time 128.41 seconds
Started Feb 25 01:23:57 PM PST 24
Finished Feb 25 01:26:06 PM PST 24
Peak memory 202328 kb
Host smart-921c6c41-f9de-48f9-877e-554ce4866581
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959982521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.3959982521
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.3070924959
Short name T365
Test name
Test status
Simulation time 2275759455 ps
CPU time 44.8 seconds
Started Feb 25 01:23:52 PM PST 24
Finished Feb 25 01:24:37 PM PST 24
Peak memory 223292 kb
Host smart-866364a6-066b-462c-8a33-8268d7fd79a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070924959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.3070924959
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.1070779983
Short name T483
Test name
Test status
Simulation time 1594500558 ps
CPU time 30.8 seconds
Started Feb 25 01:23:59 PM PST 24
Finished Feb 25 01:24:30 PM PST 24
Peak memory 202280 kb
Host smart-6934a0f1-ff1b-417c-846d-1d1224eeefe9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070779983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.1070779983
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1822276136
Short name T341
Test name
Test status
Simulation time 8250834364 ps
CPU time 277.44 seconds
Started Feb 25 01:23:56 PM PST 24
Finished Feb 25 01:28:34 PM PST 24
Peak memory 202428 kb
Host smart-51359497-d688-4ccd-bd72-ed6103319cd5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822276136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.1822276136
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.482242122
Short name T540
Test name
Test status
Simulation time 362956126 ps
CPU time 5.45 seconds
Started Feb 25 01:23:59 PM PST 24
Finished Feb 25 01:24:04 PM PST 24
Peak memory 202544 kb
Host smart-e1a91208-1219-4576-bfd7-b8a4dc34ddfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482242122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.482242122
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3748812474
Short name T345
Test name
Test status
Simulation time 6731380092 ps
CPU time 320.81 seconds
Started Feb 25 01:23:58 PM PST 24
Finished Feb 25 01:29:19 PM PST 24
Peak memory 371568 kb
Host smart-9df87c6d-52b6-484f-bd86-08e627b0c02b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748812474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3748812474
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.516219853
Short name T249
Test name
Test status
Simulation time 1428783692 ps
CPU time 15.2 seconds
Started Feb 25 01:23:51 PM PST 24
Finished Feb 25 01:24:06 PM PST 24
Peak memory 205916 kb
Host smart-83e140fc-ae1a-4190-9ae4-41b2012f386e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516219853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.516219853
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2959796977
Short name T17
Test name
Test status
Simulation time 5778690015 ps
CPU time 240.63 seconds
Started Feb 25 01:23:56 PM PST 24
Finished Feb 25 01:27:57 PM PST 24
Peak memory 202556 kb
Host smart-10eebe9f-1b50-4df8-a998-e4e4917016ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959796977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2959796977
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1551715294
Short name T141
Test name
Test status
Simulation time 853706716 ps
CPU time 150.52 seconds
Started Feb 25 01:23:57 PM PST 24
Finished Feb 25 01:26:28 PM PST 24
Peak memory 361692 kb
Host smart-a78e99d9-8187-4a84-abfc-c2ec69d44c04
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551715294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1551715294
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1784849689
Short name T618
Test name
Test status
Simulation time 5733944933 ps
CPU time 872.65 seconds
Started Feb 25 01:24:13 PM PST 24
Finished Feb 25 01:38:46 PM PST 24
Peak memory 375720 kb
Host smart-aef43ac0-b8e8-4232-9863-ee290cca9ca7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784849689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.1784849689
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.3941648747
Short name T431
Test name
Test status
Simulation time 14481326 ps
CPU time 0.66 seconds
Started Feb 25 01:24:14 PM PST 24
Finished Feb 25 01:24:14 PM PST 24
Peak memory 202176 kb
Host smart-2bab11c1-c901-4af9-b3d7-8583a7a46831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941648747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.3941648747
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.1254208445
Short name T340
Test name
Test status
Simulation time 9818917153 ps
CPU time 669.69 seconds
Started Feb 25 01:24:12 PM PST 24
Finished Feb 25 01:35:22 PM PST 24
Peak memory 202480 kb
Host smart-e03a5b3d-f709-40a6-ba13-9983f8f626e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254208445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.1254208445
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.3744501070
Short name T262
Test name
Test status
Simulation time 26110215440 ps
CPU time 1043.81 seconds
Started Feb 25 01:24:13 PM PST 24
Finished Feb 25 01:41:38 PM PST 24
Peak memory 372188 kb
Host smart-e4f6a995-4a2e-42da-8f7a-04ad542b14c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744501070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.3744501070
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.1960972670
Short name T464
Test name
Test status
Simulation time 36886962915 ps
CPU time 223.44 seconds
Started Feb 25 01:24:13 PM PST 24
Finished Feb 25 01:27:56 PM PST 24
Peak memory 210672 kb
Host smart-eb8bd89f-bd0a-4fe3-af11-7aadd291119e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960972670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.1960972670
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.1140662892
Short name T299
Test name
Test status
Simulation time 1930403747 ps
CPU time 54.31 seconds
Started Feb 25 01:24:13 PM PST 24
Finished Feb 25 01:25:08 PM PST 24
Peak memory 278308 kb
Host smart-cdce3648-03d6-45c7-8067-1e1bd9cbe9ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140662892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.1140662892
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2293543284
Short name T777
Test name
Test status
Simulation time 9764212901 ps
CPU time 146.8 seconds
Started Feb 25 01:24:14 PM PST 24
Finished Feb 25 01:26:42 PM PST 24
Peak memory 218712 kb
Host smart-e7613ab9-4f26-404f-ac79-3e17f0ede622
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293543284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.2293543284
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.1677835558
Short name T327
Test name
Test status
Simulation time 15760113952 ps
CPU time 246.52 seconds
Started Feb 25 01:24:14 PM PST 24
Finished Feb 25 01:28:21 PM PST 24
Peak memory 202312 kb
Host smart-4a1eb471-961a-4150-8377-b58c52e5058e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677835558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.1677835558
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.1166678238
Short name T435
Test name
Test status
Simulation time 1555236231 ps
CPU time 103.62 seconds
Started Feb 25 01:24:14 PM PST 24
Finished Feb 25 01:25:59 PM PST 24
Peak memory 338804 kb
Host smart-a3d5dbbc-0fe7-4b03-b55e-ae3053a786cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166678238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.1166678238
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.1563189793
Short name T363
Test name
Test status
Simulation time 829156797 ps
CPU time 14.6 seconds
Started Feb 25 01:24:13 PM PST 24
Finished Feb 25 01:24:28 PM PST 24
Peak memory 218568 kb
Host smart-d2b131f5-96c0-4365-87f3-6cbaf3b1e5bf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563189793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.1563189793
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.106437647
Short name T274
Test name
Test status
Simulation time 46863485591 ps
CPU time 478.87 seconds
Started Feb 25 01:24:14 PM PST 24
Finished Feb 25 01:32:13 PM PST 24
Peak memory 202416 kb
Host smart-87092395-7d9b-4afa-a802-d7af7c664606
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106437647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.106437647
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2722076026
Short name T117
Test name
Test status
Simulation time 2789525876 ps
CPU time 6.75 seconds
Started Feb 25 01:24:12 PM PST 24
Finished Feb 25 01:24:19 PM PST 24
Peak memory 202592 kb
Host smart-fad28e8a-67c6-4741-9de3-77494540a168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722076026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2722076026
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.261692067
Short name T782
Test name
Test status
Simulation time 30300397141 ps
CPU time 1333.95 seconds
Started Feb 25 01:24:15 PM PST 24
Finished Feb 25 01:46:29 PM PST 24
Peak memory 377280 kb
Host smart-a35c3ac5-414f-4d74-b917-2ec5787bee3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261692067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.261692067
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.2796531800
Short name T713
Test name
Test status
Simulation time 1621487612 ps
CPU time 19 seconds
Started Feb 25 01:23:59 PM PST 24
Finished Feb 25 01:24:18 PM PST 24
Peak memory 202356 kb
Host smart-923409f2-21f4-4f9d-9670-a211d5b3bfec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796531800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2796531800
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2744038984
Short name T89
Test name
Test status
Simulation time 23322151397 ps
CPU time 422.48 seconds
Started Feb 25 01:24:12 PM PST 24
Finished Feb 25 01:31:14 PM PST 24
Peak memory 202416 kb
Host smart-83270966-ed22-4015-be13-7d786e6ef280
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744038984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.2744038984
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2177528447
Short name T15
Test name
Test status
Simulation time 796171945 ps
CPU time 107.45 seconds
Started Feb 25 01:24:12 PM PST 24
Finished Feb 25 01:25:59 PM PST 24
Peak memory 338292 kb
Host smart-7f0de9b7-bc83-442a-9b55-854c1a7ccfa1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177528447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2177528447
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1334834320
Short name T723
Test name
Test status
Simulation time 31154856878 ps
CPU time 1007.84 seconds
Started Feb 25 01:24:27 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 362432 kb
Host smart-f3ff17e0-e69f-4283-a626-7c2af0fea001
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334834320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1334834320
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.2569227872
Short name T758
Test name
Test status
Simulation time 31409367 ps
CPU time 0.6 seconds
Started Feb 25 01:24:35 PM PST 24
Finished Feb 25 01:24:36 PM PST 24
Peak memory 202256 kb
Host smart-24b9884c-8f31-4de4-9b5d-0f61467996bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569227872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.2569227872
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1716502666
Short name T41
Test name
Test status
Simulation time 31802371446 ps
CPU time 2241.64 seconds
Started Feb 25 01:24:21 PM PST 24
Finished Feb 25 02:01:44 PM PST 24
Peak memory 202540 kb
Host smart-67bba085-c39d-4021-a1bc-2ca4d5606b4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716502666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1716502666
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.652183025
Short name T516
Test name
Test status
Simulation time 51014137580 ps
CPU time 120.1 seconds
Started Feb 25 01:24:22 PM PST 24
Finished Feb 25 01:26:22 PM PST 24
Peak memory 214136 kb
Host smart-289d9cc2-fbf2-4442-9c44-fbb740521f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652183025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc
alation.652183025
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.594068990
Short name T156
Test name
Test status
Simulation time 781511912 ps
CPU time 121.45 seconds
Started Feb 25 01:24:21 PM PST 24
Finished Feb 25 01:26:22 PM PST 24
Peak memory 335252 kb
Host smart-eb60749d-8d92-4220-94ea-3c8873909f87
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594068990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.sram_ctrl_max_throughput.594068990
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1666840735
Short name T203
Test name
Test status
Simulation time 2467096008 ps
CPU time 74.82 seconds
Started Feb 25 01:24:22 PM PST 24
Finished Feb 25 01:25:37 PM PST 24
Peak memory 211488 kb
Host smart-a5404ef9-5a54-461f-8559-ed66be67f8c5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666840735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.1666840735
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.2821283794
Short name T468
Test name
Test status
Simulation time 21076865443 ps
CPU time 152.61 seconds
Started Feb 25 01:24:20 PM PST 24
Finished Feb 25 01:26:53 PM PST 24
Peak memory 202448 kb
Host smart-a1873b97-2946-408b-b237-27120aded060
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821283794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.2821283794
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.2020796547
Short name T432
Test name
Test status
Simulation time 4586370076 ps
CPU time 29.54 seconds
Started Feb 25 01:24:12 PM PST 24
Finished Feb 25 01:24:42 PM PST 24
Peak memory 271580 kb
Host smart-55ceb9bf-c0a1-4e0c-8a71-e54ac4d55086
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020796547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.2020796547
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.3638499765
Short name T703
Test name
Test status
Simulation time 2771516560 ps
CPU time 12.96 seconds
Started Feb 25 01:24:32 PM PST 24
Finished Feb 25 01:24:45 PM PST 24
Peak memory 202400 kb
Host smart-acac0734-ca64-41bc-8719-24bea5c1687b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638499765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.3638499765
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.462197411
Short name T434
Test name
Test status
Simulation time 12832653188 ps
CPU time 304.01 seconds
Started Feb 25 01:24:21 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 202412 kb
Host smart-6f5c8f92-a6f3-4921-b48e-56b61947364b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462197411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.sram_ctrl_partial_access_b2b.462197411
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3891156489
Short name T582
Test name
Test status
Simulation time 4782955673 ps
CPU time 15.6 seconds
Started Feb 25 01:24:22 PM PST 24
Finished Feb 25 01:24:38 PM PST 24
Peak memory 202636 kb
Host smart-1992a9dc-1af1-4250-acf3-67ebaa0cdba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891156489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3891156489
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.996872558
Short name T377
Test name
Test status
Simulation time 2142628806 ps
CPU time 655.56 seconds
Started Feb 25 01:24:32 PM PST 24
Finished Feb 25 01:35:28 PM PST 24
Peak memory 375164 kb
Host smart-e96e86cc-f5dd-4ef0-bf29-e3b551e243cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996872558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.996872558
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.548583738
Short name T162
Test name
Test status
Simulation time 1779718191 ps
CPU time 25.34 seconds
Started Feb 25 01:24:13 PM PST 24
Finished Feb 25 01:24:39 PM PST 24
Peak memory 250732 kb
Host smart-9f40e901-6b25-47b9-9bc8-6020e9879c9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548583738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.548583738
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.3130035026
Short name T737
Test name
Test status
Simulation time 55834355217 ps
CPU time 1480.16 seconds
Started Feb 25 01:24:33 PM PST 24
Finished Feb 25 01:49:14 PM PST 24
Peak memory 375256 kb
Host smart-7880dd51-05b2-4cbd-b0ed-bb7d6fa47bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130035026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.3130035026
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2464184660
Short name T608
Test name
Test status
Simulation time 4739809124 ps
CPU time 378.38 seconds
Started Feb 25 01:24:21 PM PST 24
Finished Feb 25 01:30:40 PM PST 24
Peak memory 202440 kb
Host smart-cf131887-8887-4055-9264-82f15055e41f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464184660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.2464184660
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4273505530
Short name T590
Test name
Test status
Simulation time 2725992528 ps
CPU time 32.37 seconds
Started Feb 25 01:24:20 PM PST 24
Finished Feb 25 01:24:53 PM PST 24
Peak memory 230052 kb
Host smart-d15dbb54-ceba-4e69-a36d-bc0d8992736f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273505530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.4273505530
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.978348181
Short name T485
Test name
Test status
Simulation time 19372746439 ps
CPU time 551.49 seconds
Started Feb 25 01:24:33 PM PST 24
Finished Feb 25 01:33:45 PM PST 24
Peak memory 369916 kb
Host smart-1a1aff68-4d2e-4c13-b82f-d596a713cd2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978348181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.sram_ctrl_access_during_key_req.978348181
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.3759132837
Short name T291
Test name
Test status
Simulation time 67058670 ps
CPU time 0.66 seconds
Started Feb 25 01:24:40 PM PST 24
Finished Feb 25 01:24:42 PM PST 24
Peak memory 201844 kb
Host smart-386f42ce-e42f-4a0c-b87d-ff751cccb512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759132837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.3759132837
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.932500482
Short name T394
Test name
Test status
Simulation time 248345873979 ps
CPU time 2094.64 seconds
Started Feb 25 01:24:35 PM PST 24
Finished Feb 25 01:59:30 PM PST 24
Peak memory 202472 kb
Host smart-97f7681c-7499-46a9-8d82-6b17dcc121c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932500482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.
932500482
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.2778699990
Short name T7
Test name
Test status
Simulation time 66723996077 ps
CPU time 218.2 seconds
Started Feb 25 01:24:33 PM PST 24
Finished Feb 25 01:28:12 PM PST 24
Peak memory 210668 kb
Host smart-a1671877-dc07-4e82-86f4-c20051f8c6e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778699990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.2778699990
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.2640629714
Short name T261
Test name
Test status
Simulation time 1460905297 ps
CPU time 77.16 seconds
Started Feb 25 01:24:37 PM PST 24
Finished Feb 25 01:25:54 PM PST 24
Peak memory 313456 kb
Host smart-4254e204-1889-40c0-886d-0349ad646f86
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640629714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.2640629714
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1137490887
Short name T251
Test name
Test status
Simulation time 6779575931 ps
CPU time 78.03 seconds
Started Feb 25 01:24:45 PM PST 24
Finished Feb 25 01:26:03 PM PST 24
Peak memory 211840 kb
Host smart-b526e6bd-dbd7-4a11-9638-ffb9c313086e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137490887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.1137490887
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.2745661948
Short name T656
Test name
Test status
Simulation time 8388774605 ps
CPU time 253.96 seconds
Started Feb 25 01:24:40 PM PST 24
Finished Feb 25 01:28:54 PM PST 24
Peak memory 202396 kb
Host smart-dfe4e227-ddd9-40ba-a63c-27db7196e64a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745661948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.2745661948
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.383119396
Short name T507
Test name
Test status
Simulation time 6126438509 ps
CPU time 77.82 seconds
Started Feb 25 01:24:34 PM PST 24
Finished Feb 25 01:25:52 PM PST 24
Peak memory 310660 kb
Host smart-08282bc0-9f0b-4308-9fbc-bf6e25e122db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383119396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip
le_keys.383119396
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.4174954522
Short name T180
Test name
Test status
Simulation time 1043485133 ps
CPU time 150.05 seconds
Started Feb 25 01:24:36 PM PST 24
Finished Feb 25 01:27:07 PM PST 24
Peak memory 370908 kb
Host smart-69eab233-f579-4e15-b013-0257b670c722
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174954522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.4174954522
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1150412518
Short name T246
Test name
Test status
Simulation time 37300284410 ps
CPU time 443.85 seconds
Started Feb 25 01:24:33 PM PST 24
Finished Feb 25 01:31:57 PM PST 24
Peak memory 202348 kb
Host smart-ee76ec4b-6aae-4e42-93bf-1ff34ab7b645
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150412518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.1150412518
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.1532556952
Short name T190
Test name
Test status
Simulation time 687494347 ps
CPU time 5.34 seconds
Started Feb 25 01:24:38 PM PST 24
Finished Feb 25 01:24:44 PM PST 24
Peak memory 202564 kb
Host smart-f0dd2f71-57cd-4382-b772-79eca2a12d8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532556952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1532556952
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3743603324
Short name T131
Test name
Test status
Simulation time 25219807780 ps
CPU time 1189.34 seconds
Started Feb 25 01:24:39 PM PST 24
Finished Feb 25 01:44:28 PM PST 24
Peak memory 380308 kb
Host smart-aa758e44-e6b2-4848-881b-9b583e30bec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743603324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3743603324
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.3269239601
Short name T576
Test name
Test status
Simulation time 594256882 ps
CPU time 134.74 seconds
Started Feb 25 01:24:35 PM PST 24
Finished Feb 25 01:26:50 PM PST 24
Peak memory 346564 kb
Host smart-11eeb428-4f7f-4a37-bc6a-9cb0b0b08908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269239601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3269239601
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.691031784
Short name T805
Test name
Test status
Simulation time 266865148758 ps
CPU time 6847.05 seconds
Started Feb 25 01:24:33 PM PST 24
Finished Feb 25 03:18:41 PM PST 24
Peak memory 386584 kb
Host smart-d71a7aea-56ff-4a91-8fca-cf3d3d0c413c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691031784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_stress_all.691031784
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1386339991
Short name T178
Test name
Test status
Simulation time 16776884677 ps
CPU time 422.59 seconds
Started Feb 25 01:24:35 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 202428 kb
Host smart-0227f898-9352-497f-8c5c-39fd2acb29c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386339991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1386339991
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2967599380
Short name T384
Test name
Test status
Simulation time 2616973339 ps
CPU time 27.39 seconds
Started Feb 25 01:24:35 PM PST 24
Finished Feb 25 01:25:02 PM PST 24
Peak memory 212296 kb
Host smart-07cf8cea-50cf-4fc7-9b0f-4cd89a590e86
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967599380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2967599380
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2297301916
Short name T297
Test name
Test status
Simulation time 21451410469 ps
CPU time 506.15 seconds
Started Feb 25 01:24:45 PM PST 24
Finished Feb 25 01:33:11 PM PST 24
Peak memory 320868 kb
Host smart-13d4fce0-acb9-4598-ac16-9ae355ee31e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297301916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.2297301916
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.3711330261
Short name T189
Test name
Test status
Simulation time 13290912 ps
CPU time 0.61 seconds
Started Feb 25 01:24:43 PM PST 24
Finished Feb 25 01:24:44 PM PST 24
Peak memory 202072 kb
Host smart-c5947a10-de66-46a4-bef0-2d753049d23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711330261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.3711330261
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.2004444580
Short name T329
Test name
Test status
Simulation time 65342450849 ps
CPU time 1418.77 seconds
Started Feb 25 01:24:43 PM PST 24
Finished Feb 25 01:48:22 PM PST 24
Peak memory 202592 kb
Host smart-f9b6ea36-6a9a-47b9-9fbd-c2638aaf1d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004444580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.2004444580
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3518900298
Short name T298
Test name
Test status
Simulation time 703775811 ps
CPU time 36.04 seconds
Started Feb 25 01:24:41 PM PST 24
Finished Feb 25 01:25:17 PM PST 24
Peak memory 251432 kb
Host smart-0de781c6-9a55-4225-9713-ccfc2401f070
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518900298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3518900298
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.12623944
Short name T389
Test name
Test status
Simulation time 18938210500 ps
CPU time 151.59 seconds
Started Feb 25 01:24:47 PM PST 24
Finished Feb 25 01:27:19 PM PST 24
Peak memory 211688 kb
Host smart-6b6161bc-5d91-47a1-8c19-96901ad731a3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_mem_partial_access.12623944
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.2291047583
Short name T597
Test name
Test status
Simulation time 28705495156 ps
CPU time 156.47 seconds
Started Feb 25 01:24:46 PM PST 24
Finished Feb 25 01:27:23 PM PST 24
Peak memory 202316 kb
Host smart-b838bf5f-42bd-4a9c-a90e-4938ba19b87d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291047583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.2291047583
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.1911456044
Short name T184
Test name
Test status
Simulation time 27976285144 ps
CPU time 964.31 seconds
Started Feb 25 01:24:38 PM PST 24
Finished Feb 25 01:40:43 PM PST 24
Peak memory 378372 kb
Host smart-1ca60f1e-feba-4b35-a8c9-8ee500648769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911456044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.1911456044
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.2530623834
Short name T134
Test name
Test status
Simulation time 1007770493 ps
CPU time 26.07 seconds
Started Feb 25 01:24:47 PM PST 24
Finished Feb 25 01:25:14 PM PST 24
Peak memory 250576 kb
Host smart-e4a96308-8503-4d64-9a40-51599fafc46f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530623834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.2530623834
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.727156267
Short name T447
Test name
Test status
Simulation time 6464983171 ps
CPU time 335.95 seconds
Started Feb 25 01:24:42 PM PST 24
Finished Feb 25 01:30:18 PM PST 24
Peak memory 210640 kb
Host smart-f48481b4-6da8-41d4-8135-ed2e7abd0150
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727156267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.sram_ctrl_partial_access_b2b.727156267
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.1136206578
Short name T351
Test name
Test status
Simulation time 343951170 ps
CPU time 5.93 seconds
Started Feb 25 01:24:46 PM PST 24
Finished Feb 25 01:24:52 PM PST 24
Peak memory 202500 kb
Host smart-cbbefefa-ee6c-4fec-8800-7eff44b92220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136206578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1136206578
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.3172155822
Short name T554
Test name
Test status
Simulation time 13422918368 ps
CPU time 806.97 seconds
Started Feb 25 01:24:46 PM PST 24
Finished Feb 25 01:38:13 PM PST 24
Peak memory 378192 kb
Host smart-8831009b-cde4-40d2-8695-90adf68a7c9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172155822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3172155822
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.887379940
Short name T639
Test name
Test status
Simulation time 732762842 ps
CPU time 15.32 seconds
Started Feb 25 01:24:40 PM PST 24
Finished Feb 25 01:24:56 PM PST 24
Peak memory 202356 kb
Host smart-2bd4272e-81bb-425d-97a8-1c8c7352af51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887379940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.887379940
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.789451427
Short name T449
Test name
Test status
Simulation time 5133831449 ps
CPU time 365.13 seconds
Started Feb 25 01:24:38 PM PST 24
Finished Feb 25 01:30:44 PM PST 24
Peak memory 202456 kb
Host smart-189869d6-4a24-4df3-95e8-3cc87e078c4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789451427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_stress_pipeline.789451427
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2244716348
Short name T10
Test name
Test status
Simulation time 1514329860 ps
CPU time 105.1 seconds
Started Feb 25 01:24:41 PM PST 24
Finished Feb 25 01:26:26 PM PST 24
Peak memory 335280 kb
Host smart-9403a37d-8de4-4d11-8fdb-821b928c774c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244716348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2244716348
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3697375455
Short name T374
Test name
Test status
Simulation time 27282172779 ps
CPU time 1580.92 seconds
Started Feb 25 01:24:53 PM PST 24
Finished Feb 25 01:51:15 PM PST 24
Peak memory 374196 kb
Host smart-806be4f4-2868-4a22-beed-2225a5f4e0a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697375455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.3697375455
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2653880558
Short name T621
Test name
Test status
Simulation time 21209032 ps
CPU time 0.66 seconds
Started Feb 25 01:24:54 PM PST 24
Finished Feb 25 01:24:55 PM PST 24
Peak memory 201912 kb
Host smart-3d44a481-ce79-4930-acec-f0403a243485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653880558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2653880558
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.2835798918
Short name T493
Test name
Test status
Simulation time 146406063599 ps
CPU time 2711.68 seconds
Started Feb 25 01:24:46 PM PST 24
Finished Feb 25 02:09:58 PM PST 24
Peak memory 210608 kb
Host smart-4453aba5-6e24-4496-b000-7422eb2a9798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835798918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.2835798918
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.3251735702
Short name T139
Test name
Test status
Simulation time 6379375759 ps
CPU time 97.75 seconds
Started Feb 25 01:24:57 PM PST 24
Finished Feb 25 01:26:35 PM PST 24
Peak memory 356988 kb
Host smart-51e34711-4aba-4dc8-9874-4e0d38944748
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251735702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.3251735702
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.3244900387
Short name T489
Test name
Test status
Simulation time 30400871434 ps
CPU time 75.08 seconds
Started Feb 25 01:24:47 PM PST 24
Finished Feb 25 01:26:02 PM PST 24
Peak memory 210724 kb
Host smart-338e6cd8-1bec-4d5d-b07e-a18c98460414
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244900387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.3244900387
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1999895420
Short name T311
Test name
Test status
Simulation time 2983182313 ps
CPU time 31.89 seconds
Started Feb 25 01:24:47 PM PST 24
Finished Feb 25 01:25:19 PM PST 24
Peak memory 235160 kb
Host smart-b218e02a-1707-417f-ac60-465b0f393eb6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999895420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1999895420
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1840449888
Short name T219
Test name
Test status
Simulation time 6454851899 ps
CPU time 132.35 seconds
Started Feb 25 01:24:54 PM PST 24
Finished Feb 25 01:27:07 PM PST 24
Peak memory 211512 kb
Host smart-b867e38d-e6f1-4e67-9f49-33de7ccca060
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840449888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.1840449888
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.3365620443
Short name T820
Test name
Test status
Simulation time 13918728037 ps
CPU time 278.6 seconds
Started Feb 25 01:24:53 PM PST 24
Finished Feb 25 01:29:33 PM PST 24
Peak memory 202412 kb
Host smart-cb594e01-cf71-4ff1-a98c-33d233eeff19
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365620443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.3365620443
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.580569134
Short name T748
Test name
Test status
Simulation time 20117485430 ps
CPU time 1163.95 seconds
Started Feb 25 01:24:44 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 375924 kb
Host smart-4c5850ce-7bfa-4d78-8e82-77beae878ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580569134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip
le_keys.580569134
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1908600734
Short name T458
Test name
Test status
Simulation time 2902488288 ps
CPU time 33.4 seconds
Started Feb 25 01:24:45 PM PST 24
Finished Feb 25 01:25:18 PM PST 24
Peak memory 224824 kb
Host smart-be315d25-7861-4b2d-91dd-a7a92bb357b6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908600734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1908600734
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1404633099
Short name T108
Test name
Test status
Simulation time 130179045059 ps
CPU time 297.7 seconds
Started Feb 25 01:24:47 PM PST 24
Finished Feb 25 01:29:45 PM PST 24
Peak memory 202400 kb
Host smart-efdd90fa-0bd6-4ce0-b6a7-b7a76bd302cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404633099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.1404633099
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.1188047474
Short name T422
Test name
Test status
Simulation time 1409898215 ps
CPU time 6.28 seconds
Started Feb 25 01:24:57 PM PST 24
Finished Feb 25 01:25:04 PM PST 24
Peak memory 202548 kb
Host smart-b4a84458-aedd-4bf2-a876-69b1f991b17c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188047474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1188047474
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.1982799884
Short name T393
Test name
Test status
Simulation time 5744619354 ps
CPU time 308.54 seconds
Started Feb 25 01:24:54 PM PST 24
Finished Feb 25 01:30:03 PM PST 24
Peak memory 368952 kb
Host smart-d7d58286-7b44-42de-a51b-2ee6673dc7b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982799884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1982799884
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.2944474773
Short name T420
Test name
Test status
Simulation time 1761329400 ps
CPU time 17.31 seconds
Started Feb 25 01:24:47 PM PST 24
Finished Feb 25 01:25:04 PM PST 24
Peak memory 202456 kb
Host smart-aee50b63-c79c-4222-b426-b390c25b7800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944474773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2944474773
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.1967912918
Short name T386
Test name
Test status
Simulation time 991841110206 ps
CPU time 7056.52 seconds
Started Feb 25 01:24:57 PM PST 24
Finished Feb 25 03:22:35 PM PST 24
Peak memory 382184 kb
Host smart-c2d31ef6-c9c3-4f2b-ad8d-aa8a971172e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967912918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.1967912918
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.250987997
Short name T90
Test name
Test status
Simulation time 18228007495 ps
CPU time 351.67 seconds
Started Feb 25 01:24:45 PM PST 24
Finished Feb 25 01:30:37 PM PST 24
Peak memory 202428 kb
Host smart-754a04b2-0d78-47c7-b46b-2974c7c11702
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250987997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_stress_pipeline.250987997
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.677443731
Short name T154
Test name
Test status
Simulation time 759278788 ps
CPU time 83.76 seconds
Started Feb 25 01:24:46 PM PST 24
Finished Feb 25 01:26:10 PM PST 24
Peak memory 309736 kb
Host smart-5ce4af89-9cf2-4847-a355-44203d6024c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677443731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.677443731
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2150180083
Short name T838
Test name
Test status
Simulation time 14249282908 ps
CPU time 803.03 seconds
Started Feb 25 01:25:02 PM PST 24
Finished Feb 25 01:38:26 PM PST 24
Peak memory 377180 kb
Host smart-a0ebbda8-08a6-4a23-9b77-1f1e9921b5b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150180083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2150180083
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.587613958
Short name T228
Test name
Test status
Simulation time 36177654 ps
CPU time 0.64 seconds
Started Feb 25 01:25:06 PM PST 24
Finished Feb 25 01:25:06 PM PST 24
Peak memory 202240 kb
Host smart-fd7a0cc0-692a-4f09-a2a6-7cbca108dab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587613958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.587613958
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.1301864081
Short name T733
Test name
Test status
Simulation time 71135200608 ps
CPU time 1066.45 seconds
Started Feb 25 01:24:53 PM PST 24
Finished Feb 25 01:42:41 PM PST 24
Peak memory 202432 kb
Host smart-fafc25d1-f6ca-45a5-a770-e832c4824dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301864081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.1301864081
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.202666723
Short name T743
Test name
Test status
Simulation time 31068538431 ps
CPU time 2354.15 seconds
Started Feb 25 01:25:02 PM PST 24
Finished Feb 25 02:04:17 PM PST 24
Peak memory 379308 kb
Host smart-f890b7a3-bd24-4c54-8778-452e10ba6a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202666723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executabl
e.202666723
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.3757795378
Short name T574
Test name
Test status
Simulation time 11067429542 ps
CPU time 104.7 seconds
Started Feb 25 01:24:57 PM PST 24
Finished Feb 25 01:26:42 PM PST 24
Peak memory 214052 kb
Host smart-01bd2911-5d6e-47e8-83da-53fbf92ce573
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757795378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.3757795378
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.1402647068
Short name T643
Test name
Test status
Simulation time 1698899067 ps
CPU time 181.79 seconds
Started Feb 25 01:24:54 PM PST 24
Finished Feb 25 01:27:56 PM PST 24
Peak memory 366052 kb
Host smart-97a04d5e-a847-4a98-8667-9054fc0d1710
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402647068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.1402647068
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.148080721
Short name T736
Test name
Test status
Simulation time 15621195880 ps
CPU time 142.65 seconds
Started Feb 25 01:25:04 PM PST 24
Finished Feb 25 01:27:26 PM PST 24
Peak memory 210916 kb
Host smart-16af3281-a151-44ff-837a-fff8c8742792
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148080721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_mem_partial_access.148080721
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.2558943557
Short name T646
Test name
Test status
Simulation time 74601322694 ps
CPU time 312.09 seconds
Started Feb 25 01:25:03 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 202412 kb
Host smart-76328a7a-54e4-4751-994f-ac71e187d473
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558943557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.2558943557
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.262298975
Short name T627
Test name
Test status
Simulation time 26916471620 ps
CPU time 140.61 seconds
Started Feb 25 01:24:53 PM PST 24
Finished Feb 25 01:27:15 PM PST 24
Peak memory 315696 kb
Host smart-73e60d41-deac-43ab-bd8b-eff8f0839391
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262298975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip
le_keys.262298975
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.448056947
Short name T549
Test name
Test status
Simulation time 1712720620 ps
CPU time 43.12 seconds
Started Feb 25 01:24:53 PM PST 24
Finished Feb 25 01:25:37 PM PST 24
Peak memory 278956 kb
Host smart-4db37c1e-984f-4e5a-801b-b1c931b6d3c7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448056947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s
ram_ctrl_partial_access.448056947
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2837152166
Short name T606
Test name
Test status
Simulation time 18417776195 ps
CPU time 397.26 seconds
Started Feb 25 01:24:54 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 210600 kb
Host smart-9971bdd1-61e8-43c6-85e3-ed80248a6e46
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837152166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.2837152166
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.279129345
Short name T740
Test name
Test status
Simulation time 3377445903 ps
CPU time 15.33 seconds
Started Feb 25 01:25:02 PM PST 24
Finished Feb 25 01:25:18 PM PST 24
Peak memory 202608 kb
Host smart-e5d46fdd-5cf7-4582-990d-d006b53acaad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279129345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.279129345
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.2023582493
Short name T186
Test name
Test status
Simulation time 1563991778 ps
CPU time 29.02 seconds
Started Feb 25 01:25:04 PM PST 24
Finished Feb 25 01:25:33 PM PST 24
Peak memory 215228 kb
Host smart-dd60f5e5-d74a-4960-89bb-c97a81032edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023582493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2023582493
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.1238592120
Short name T38
Test name
Test status
Simulation time 898416674 ps
CPU time 9.12 seconds
Started Feb 25 01:24:53 PM PST 24
Finished Feb 25 01:25:03 PM PST 24
Peak memory 202340 kb
Host smart-882a60a1-48a6-4ace-900b-310e7f204d45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238592120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1238592120
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1475156280
Short name T110
Test name
Test status
Simulation time 147440494839 ps
CPU time 4054.12 seconds
Started Feb 25 01:25:03 PM PST 24
Finished Feb 25 02:32:37 PM PST 24
Peak memory 379548 kb
Host smart-0e653934-7064-4c85-bea3-7091d8929045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475156280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1475156280
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1440683514
Short name T91
Test name
Test status
Simulation time 7829715087 ps
CPU time 342.95 seconds
Started Feb 25 01:24:55 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 202440 kb
Host smart-7b81ab80-cc63-4247-894c-01e5378e4fd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440683514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1440683514
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4154348324
Short name T191
Test name
Test status
Simulation time 1481628388 ps
CPU time 48.92 seconds
Started Feb 25 01:24:58 PM PST 24
Finished Feb 25 01:25:47 PM PST 24
Peak memory 288260 kb
Host smart-656a8aa9-2e15-4519-bbd9-b952e3b20fd2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154348324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.4154348324
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3595331623
Short name T391
Test name
Test status
Simulation time 35864941044 ps
CPU time 1728.24 seconds
Started Feb 25 01:25:26 PM PST 24
Finished Feb 25 01:54:14 PM PST 24
Peak memory 378208 kb
Host smart-3ac3ab01-81ee-4064-afb7-694fe3ff91f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595331623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.3595331623
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.197628920
Short name T785
Test name
Test status
Simulation time 14908616 ps
CPU time 0.67 seconds
Started Feb 25 01:25:19 PM PST 24
Finished Feb 25 01:25:20 PM PST 24
Peak memory 201868 kb
Host smart-c45cb3a7-f159-4527-8594-573acb480044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197628920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.197628920
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.1295501113
Short name T604
Test name
Test status
Simulation time 64685364898 ps
CPU time 1503.73 seconds
Started Feb 25 01:25:04 PM PST 24
Finished Feb 25 01:50:08 PM PST 24
Peak memory 202448 kb
Host smart-e8ad435d-e299-4edb-9894-21756667be69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295501113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.1295501113
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.4019812070
Short name T798
Test name
Test status
Simulation time 8768760938 ps
CPU time 92.15 seconds
Started Feb 25 01:25:19 PM PST 24
Finished Feb 25 01:26:52 PM PST 24
Peak memory 214036 kb
Host smart-997ebb3c-a6ef-4cb9-a858-e4e9635663eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019812070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.4019812070
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.282520852
Short name T245
Test name
Test status
Simulation time 6048830505 ps
CPU time 30.53 seconds
Started Feb 25 01:25:19 PM PST 24
Finished Feb 25 01:25:49 PM PST 24
Peak memory 210688 kb
Host smart-9ad25abd-71e2-4e29-b797-d7d742a0e33f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282520852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sram_ctrl_max_throughput.282520852
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3373155561
Short name T793
Test name
Test status
Simulation time 4499458969 ps
CPU time 152.33 seconds
Started Feb 25 01:25:21 PM PST 24
Finished Feb 25 01:27:53 PM PST 24
Peak memory 215024 kb
Host smart-80d4f789-6486-4c60-9806-360ddb6dad21
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373155561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.3373155561
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.2609211823
Short name T3
Test name
Test status
Simulation time 61722289656 ps
CPU time 317.3 seconds
Started Feb 25 01:25:20 PM PST 24
Finished Feb 25 01:30:38 PM PST 24
Peak memory 202476 kb
Host smart-f3215755-b72b-4174-bc84-62cdcadc7f3a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609211823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.2609211823
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.3931746689
Short name T558
Test name
Test status
Simulation time 20116689641 ps
CPU time 1425.66 seconds
Started Feb 25 01:25:02 PM PST 24
Finished Feb 25 01:48:48 PM PST 24
Peak memory 378160 kb
Host smart-b11c0130-8edc-4a22-b024-974406848841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931746689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.3931746689
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.3649409522
Short name T125
Test name
Test status
Simulation time 1898638937 ps
CPU time 11.31 seconds
Started Feb 25 01:25:19 PM PST 24
Finished Feb 25 01:25:31 PM PST 24
Peak memory 218104 kb
Host smart-db881006-ae96-4db3-94b3-2db3f1b5a786
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649409522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.3649409522
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.748033624
Short name T336
Test name
Test status
Simulation time 28679555720 ps
CPU time 484.57 seconds
Started Feb 25 01:25:18 PM PST 24
Finished Feb 25 01:33:23 PM PST 24
Peak memory 202424 kb
Host smart-d112ecad-5cdb-45a8-93eb-2c2871c85b14
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748033624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.sram_ctrl_partial_access_b2b.748033624
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.1400446306
Short name T577
Test name
Test status
Simulation time 678028181 ps
CPU time 14.29 seconds
Started Feb 25 01:25:19 PM PST 24
Finished Feb 25 01:25:34 PM PST 24
Peak memory 202656 kb
Host smart-07a27be1-5730-4faf-9c4d-9a0b2bc50602
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400446306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1400446306
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.2117427796
Short name T495
Test name
Test status
Simulation time 41081785514 ps
CPU time 812.93 seconds
Started Feb 25 01:25:20 PM PST 24
Finished Feb 25 01:38:53 PM PST 24
Peak memory 376120 kb
Host smart-efc6f3b4-95d9-4bf8-8fc0-57eafa942619
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117427796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2117427796
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.2307541748
Short name T119
Test name
Test status
Simulation time 734226825 ps
CPU time 11.22 seconds
Started Feb 25 01:25:02 PM PST 24
Finished Feb 25 01:25:14 PM PST 24
Peak memory 202348 kb
Host smart-afd0e315-0ec7-449a-a7b7-a2e792d473d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307541748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2307541748
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3727310043
Short name T214
Test name
Test status
Simulation time 10537744619 ps
CPU time 193.02 seconds
Started Feb 25 01:25:19 PM PST 24
Finished Feb 25 01:28:33 PM PST 24
Peak memory 202368 kb
Host smart-15781555-f550-4848-a2fe-a36b320cc1d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727310043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.3727310043
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1519086437
Short name T701
Test name
Test status
Simulation time 2709655599 ps
CPU time 29.13 seconds
Started Feb 25 01:25:20 PM PST 24
Finished Feb 25 01:25:50 PM PST 24
Peak memory 218508 kb
Host smart-fb7a8e52-904e-4640-a5ae-f66d5271a509
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519086437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1519086437
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.144853606
Short name T331
Test name
Test status
Simulation time 7153181638 ps
CPU time 1034.14 seconds
Started Feb 25 01:25:51 PM PST 24
Finished Feb 25 01:43:06 PM PST 24
Peak memory 378100 kb
Host smart-5d8e6567-b512-4fa8-82fb-19a024541b44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144853606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 48.sram_ctrl_access_during_key_req.144853606
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.2894892098
Short name T158
Test name
Test status
Simulation time 76673475 ps
CPU time 0.62 seconds
Started Feb 25 01:25:50 PM PST 24
Finished Feb 25 01:25:51 PM PST 24
Peak memory 201940 kb
Host smart-bb95e28b-18ba-46d8-91ac-c9350cee107c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894892098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.2894892098
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.1579863802
Short name T673
Test name
Test status
Simulation time 135225440953 ps
CPU time 717.19 seconds
Started Feb 25 01:25:51 PM PST 24
Finished Feb 25 01:37:49 PM PST 24
Peak memory 202488 kb
Host smart-2126b22d-0ed2-433f-a973-63c681c9a793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579863802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.1579863802
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.3477657228
Short name T346
Test name
Test status
Simulation time 13981083849 ps
CPU time 580.87 seconds
Started Feb 25 01:25:51 PM PST 24
Finished Feb 25 01:35:32 PM PST 24
Peak memory 379388 kb
Host smart-2d83a872-86f6-4972-8b42-7ac94d5d8dce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477657228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.3477657228
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.151501440
Short name T695
Test name
Test status
Simulation time 33330676403 ps
CPU time 105.07 seconds
Started Feb 25 01:25:57 PM PST 24
Finished Feb 25 01:27:43 PM PST 24
Peak memory 214328 kb
Host smart-fd018bec-574e-4f8f-bb08-7c544f1d3724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151501440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc
alation.151501440
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2926206546
Short name T533
Test name
Test status
Simulation time 744687649 ps
CPU time 54.65 seconds
Started Feb 25 01:25:51 PM PST 24
Finished Feb 25 01:26:46 PM PST 24
Peak memory 272180 kb
Host smart-c8994890-7143-4f01-8b09-bc6bf0984d80
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926206546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2926206546
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1598431080
Short name T68
Test name
Test status
Simulation time 994990263 ps
CPU time 79.55 seconds
Started Feb 25 01:25:58 PM PST 24
Finished Feb 25 01:27:18 PM PST 24
Peak memory 218652 kb
Host smart-05dcb308-c2a4-4fe6-b030-c887edcf27d4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598431080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.1598431080
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.3233829018
Short name T204
Test name
Test status
Simulation time 14492189216 ps
CPU time 289.58 seconds
Started Feb 25 01:25:54 PM PST 24
Finished Feb 25 01:30:43 PM PST 24
Peak memory 202488 kb
Host smart-cf85f47d-ed42-4c1e-879c-2609a6f504e3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233829018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.3233829018
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.4004622877
Short name T469
Test name
Test status
Simulation time 25784624245 ps
CPU time 1211.57 seconds
Started Feb 25 01:25:52 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 378252 kb
Host smart-a397f426-b5fc-4d9c-9c3d-fb5a1dd008c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004622877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.4004622877
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.3799847263
Short name T508
Test name
Test status
Simulation time 976016451 ps
CPU time 41.56 seconds
Started Feb 25 01:25:51 PM PST 24
Finished Feb 25 01:26:33 PM PST 24
Peak memory 202300 kb
Host smart-9a65907f-3c50-4981-b7f3-391411ba689e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799847263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.3799847263
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3227890941
Short name T230
Test name
Test status
Simulation time 62747881404 ps
CPU time 363.09 seconds
Started Feb 25 01:25:54 PM PST 24
Finished Feb 25 01:31:57 PM PST 24
Peak memory 202356 kb
Host smart-2d213d0b-c743-4ae4-bd23-b895cb347955
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227890941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.3227890941
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1712635399
Short name T342
Test name
Test status
Simulation time 1302729830 ps
CPU time 14.02 seconds
Started Feb 25 01:25:53 PM PST 24
Finished Feb 25 01:26:07 PM PST 24
Peak memory 202660 kb
Host smart-12d55dd3-e3df-406b-9c57-832a2a5e48b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712635399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1712635399
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.1820295428
Short name T666
Test name
Test status
Simulation time 36543833516 ps
CPU time 936.26 seconds
Started Feb 25 01:25:51 PM PST 24
Finished Feb 25 01:41:28 PM PST 24
Peak memory 378356 kb
Host smart-6d6fae49-203d-482b-8be2-9095dc902177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820295428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1820295428
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.910030927
Short name T525
Test name
Test status
Simulation time 2996701189 ps
CPU time 14.14 seconds
Started Feb 25 01:25:52 PM PST 24
Finished Feb 25 01:26:06 PM PST 24
Peak memory 202408 kb
Host smart-3f47f7eb-b850-49ab-91ca-67666a1f1f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910030927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.910030927
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3713350103
Short name T583
Test name
Test status
Simulation time 3063843000 ps
CPU time 205.5 seconds
Started Feb 25 01:25:52 PM PST 24
Finished Feb 25 01:29:18 PM PST 24
Peak memory 202432 kb
Host smart-939f7391-9f48-4d6a-8f8c-7d79c6792435
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713350103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3713350103
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3381040738
Short name T344
Test name
Test status
Simulation time 2728035458 ps
CPU time 32.18 seconds
Started Feb 25 01:25:51 PM PST 24
Finished Feb 25 01:26:24 PM PST 24
Peak memory 230076 kb
Host smart-befa0beb-1f0f-4166-b4f0-782f752e2938
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381040738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3381040738
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2020056752
Short name T667
Test name
Test status
Simulation time 10265541079 ps
CPU time 934.98 seconds
Started Feb 25 01:26:04 PM PST 24
Finished Feb 25 01:41:40 PM PST 24
Peak memory 372952 kb
Host smart-287d006b-e686-4ddc-82ad-792f2ca5ea55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020056752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.2020056752
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.3527733364
Short name T348
Test name
Test status
Simulation time 14986659 ps
CPU time 0.7 seconds
Started Feb 25 01:26:03 PM PST 24
Finished Feb 25 01:26:05 PM PST 24
Peak memory 201880 kb
Host smart-ad1cb991-ac9d-4de5-aff7-23873f5dc840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527733364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.3527733364
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2764832871
Short name T160
Test name
Test status
Simulation time 689315769539 ps
CPU time 2990.71 seconds
Started Feb 25 01:26:09 PM PST 24
Finished Feb 25 02:16:00 PM PST 24
Peak memory 202360 kb
Host smart-cc6810a7-e191-4b3e-8578-57580caa9bb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764832871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2764832871
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1065625206
Short name T676
Test name
Test status
Simulation time 3816505654 ps
CPU time 32.67 seconds
Started Feb 25 01:26:01 PM PST 24
Finished Feb 25 01:26:34 PM PST 24
Peak memory 210620 kb
Host smart-644722d8-944e-48d7-a9a0-3f1210ea76be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065625206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1065625206
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.3433105653
Short name T11
Test name
Test status
Simulation time 1430584530 ps
CPU time 43.55 seconds
Started Feb 25 01:26:04 PM PST 24
Finished Feb 25 01:26:48 PM PST 24
Peak memory 260616 kb
Host smart-7046ab23-d40f-457e-bf94-8bc059888b93
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433105653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.3433105653
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1147415292
Short name T581
Test name
Test status
Simulation time 17394964733 ps
CPU time 154.64 seconds
Started Feb 25 01:26:09 PM PST 24
Finished Feb 25 01:28:43 PM PST 24
Peak memory 211356 kb
Host smart-93e64a6a-6b97-422f-b9c0-c85e44ff5081
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147415292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.1147415292
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.2066754873
Short name T334
Test name
Test status
Simulation time 3726929555 ps
CPU time 122.57 seconds
Started Feb 25 01:26:09 PM PST 24
Finished Feb 25 01:28:12 PM PST 24
Peak memory 202336 kb
Host smart-d14a66b3-d956-41fb-b0e3-b059b5f878e5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066754873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.2066754873
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.365575711
Short name T370
Test name
Test status
Simulation time 4558166513 ps
CPU time 86.53 seconds
Started Feb 25 01:25:58 PM PST 24
Finished Feb 25 01:27:25 PM PST 24
Peak memory 303624 kb
Host smart-6e0ef101-e4b0-4341-a134-02635500ed12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365575711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip
le_keys.365575711
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.3311320675
Short name T727
Test name
Test status
Simulation time 2279662922 ps
CPU time 80.89 seconds
Started Feb 25 01:26:08 PM PST 24
Finished Feb 25 01:27:29 PM PST 24
Peak memory 323816 kb
Host smart-62eb1538-ae17-47b0-9048-0d8e4e1c1ce1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311320675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.3311320675
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2417651982
Short name T690
Test name
Test status
Simulation time 38401313601 ps
CPU time 413.76 seconds
Started Feb 25 01:25:59 PM PST 24
Finished Feb 25 01:32:54 PM PST 24
Peak memory 202412 kb
Host smart-b3e6e191-43cb-4633-a359-b7860db63337
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417651982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.2417651982
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.3277141846
Short name T42
Test name
Test status
Simulation time 1888578846 ps
CPU time 13.99 seconds
Started Feb 25 01:26:01 PM PST 24
Finished Feb 25 01:26:15 PM PST 24
Peak memory 202640 kb
Host smart-08b05801-76d5-42ca-b916-e9fedb166e2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277141846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3277141846
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.2311785663
Short name T166
Test name
Test status
Simulation time 77004693313 ps
CPU time 1560.49 seconds
Started Feb 25 01:26:01 PM PST 24
Finished Feb 25 01:52:01 PM PST 24
Peak memory 380264 kb
Host smart-96d5eae4-1a3c-449f-a29a-daccb8d71285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311785663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2311785663
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.2172322800
Short name T772
Test name
Test status
Simulation time 4459980924 ps
CPU time 64.85 seconds
Started Feb 25 01:25:58 PM PST 24
Finished Feb 25 01:27:04 PM PST 24
Peak memory 299480 kb
Host smart-3a96e282-f57e-4ef7-9b50-6ec6b9d1b9fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172322800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2172322800
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2755627938
Short name T833
Test name
Test status
Simulation time 10529694578 ps
CPU time 395.32 seconds
Started Feb 25 01:26:01 PM PST 24
Finished Feb 25 01:32:36 PM PST 24
Peak memory 202368 kb
Host smart-0e70c73f-ba31-4f42-8dc1-d1f0928c70e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755627938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.2755627938
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1728719873
Short name T428
Test name
Test status
Simulation time 1498776700 ps
CPU time 87.87 seconds
Started Feb 25 01:26:02 PM PST 24
Finished Feb 25 01:27:30 PM PST 24
Peak memory 325056 kb
Host smart-1aa951fa-d9ed-48f7-97f3-212105128705
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728719873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1728719873
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.628184990
Short name T572
Test name
Test status
Simulation time 21454776062 ps
CPU time 430.36 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:26:01 PM PST 24
Peak memory 332888 kb
Host smart-c1099600-0de5-4b4e-a5e4-3c7b77e7bc08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628184990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.sram_ctrl_access_during_key_req.628184990
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.3811218081
Short name T700
Test name
Test status
Simulation time 66135738 ps
CPU time 0.64 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:18:47 PM PST 24
Peak memory 202264 kb
Host smart-87226595-f75d-47ce-a381-12f8da6a3c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811218081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.3811218081
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.4024280538
Short name T244
Test name
Test status
Simulation time 179669909798 ps
CPU time 1481.39 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:43:32 PM PST 24
Peak memory 202404 kb
Host smart-04c822a1-3fac-4e2e-90db-ca282f1de4e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024280538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
4024280538
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.1462929074
Short name T694
Test name
Test status
Simulation time 12118062666 ps
CPU time 598.67 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:28:46 PM PST 24
Peak memory 377248 kb
Host smart-4acf902a-0fe3-4138-95da-be012487d4af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462929074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.1462929074
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2182558800
Short name T406
Test name
Test status
Simulation time 1487429878 ps
CPU time 68.51 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:19:58 PM PST 24
Peak memory 301652 kb
Host smart-a6001225-246e-4ea2-90d6-24ef3d47a659
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182558800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2182558800
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2640345233
Short name T739
Test name
Test status
Simulation time 8950497153 ps
CPU time 149.82 seconds
Started Feb 25 01:18:51 PM PST 24
Finished Feb 25 01:21:22 PM PST 24
Peak memory 218740 kb
Host smart-5c06eb30-0e76-42a8-9e69-4dd5c319fb16
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640345233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2640345233
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.3101793710
Short name T526
Test name
Test status
Simulation time 14354918609 ps
CPU time 136.94 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:21:05 PM PST 24
Peak memory 202372 kb
Host smart-fd08140a-29a8-40d3-9724-004e5c6f2d28
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101793710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.3101793710
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.3915653941
Short name T442
Test name
Test status
Simulation time 21523782471 ps
CPU time 1076.31 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:36:44 PM PST 24
Peak memory 380680 kb
Host smart-53da222c-160e-4fb8-9631-adfac435ab1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915653941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.3915653941
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.3770934126
Short name T398
Test name
Test status
Simulation time 757922672 ps
CPU time 12 seconds
Started Feb 25 01:18:46 PM PST 24
Finished Feb 25 01:18:58 PM PST 24
Peak memory 202496 kb
Host smart-e7bacaa4-374e-4504-bd54-caa240f5c4a8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770934126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.3770934126
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1190946287
Short name T176
Test name
Test status
Simulation time 10545535756 ps
CPU time 168.06 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:21:36 PM PST 24
Peak memory 202428 kb
Host smart-e21bbf2b-b16b-48dc-95dc-772603bb93a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190946287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.1190946287
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1243294935
Short name T253
Test name
Test status
Simulation time 697285476 ps
CPU time 5.5 seconds
Started Feb 25 01:18:53 PM PST 24
Finished Feb 25 01:18:59 PM PST 24
Peak memory 202576 kb
Host smart-f4fd8ea0-fa8d-4eeb-be33-1f5c9903bfff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243294935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1243294935
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.1025685670
Short name T369
Test name
Test status
Simulation time 4976438148 ps
CPU time 459.89 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:26:27 PM PST 24
Peak memory 372160 kb
Host smart-901f332c-6d58-4740-b45f-a3f9c3485202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025685670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1025685670
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.268279000
Short name T707
Test name
Test status
Simulation time 4158363600 ps
CPU time 29.91 seconds
Started Feb 25 01:18:51 PM PST 24
Finished Feb 25 01:19:22 PM PST 24
Peak memory 202392 kb
Host smart-2c759826-32e1-4b4a-ad34-dbf80cc5c1d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268279000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.268279000
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.4235116010
Short name T170
Test name
Test status
Simulation time 125865753449 ps
CPU time 4609.52 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 02:35:40 PM PST 24
Peak memory 379104 kb
Host smart-1bd69e7a-a3ed-459d-9952-3c9194f55ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235116010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.4235116010
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1752645418
Short name T4
Test name
Test status
Simulation time 9044510798 ps
CPU time 332.12 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:24:23 PM PST 24
Peak memory 202444 kb
Host smart-b65e601a-fe90-4449-8d09-168a50bc9f0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752645418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.1752645418
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.769731533
Short name T266
Test name
Test status
Simulation time 1185865397 ps
CPU time 45.05 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:19:33 PM PST 24
Peak memory 259040 kb
Host smart-33d7c8e1-b12a-4aef-bd1c-28dcf7385943
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769731533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.769731533
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2408446437
Short name T492
Test name
Test status
Simulation time 31576885763 ps
CPU time 1492.45 seconds
Started Feb 25 01:18:51 PM PST 24
Finished Feb 25 01:43:44 PM PST 24
Peak memory 377248 kb
Host smart-531e6e84-fb4a-4e1d-9b8f-e0111625e46e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408446437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.2408446437
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.964382260
Short name T591
Test name
Test status
Simulation time 11767348 ps
CPU time 0.68 seconds
Started Feb 25 01:18:51 PM PST 24
Finished Feb 25 01:18:53 PM PST 24
Peak memory 202196 kb
Host smart-5305a399-4f0b-4c0e-b0ed-991333bf8887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964382260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.964382260
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.3359869060
Short name T240
Test name
Test status
Simulation time 538266729505 ps
CPU time 1467.98 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:43:16 PM PST 24
Peak memory 202388 kb
Host smart-98d445a9-af23-42fc-a958-95070529cfdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359869060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
3359869060
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.2454501773
Short name T359
Test name
Test status
Simulation time 1400740191 ps
CPU time 41.01 seconds
Started Feb 25 01:18:47 PM PST 24
Finished Feb 25 01:19:29 PM PST 24
Peak memory 252496 kb
Host smart-badcbc3f-f3e4-4fdc-811b-500df6b9c68b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454501773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.2454501773
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3902861967
Short name T529
Test name
Test status
Simulation time 5202225761 ps
CPU time 155.03 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:21:25 PM PST 24
Peak memory 214764 kb
Host smart-fb7c1ff1-f1e6-468a-94fb-9d0aebe4666f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902861967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.3902861967
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3267947718
Short name T611
Test name
Test status
Simulation time 17129901078 ps
CPU time 237.77 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:22:47 PM PST 24
Peak memory 202592 kb
Host smart-01d0a353-6b86-4082-bea4-242c4b3b6094
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267947718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3267947718
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.2097172619
Short name T665
Test name
Test status
Simulation time 6593286288 ps
CPU time 434.6 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:26:04 PM PST 24
Peak memory 362404 kb
Host smart-b49c592c-b2bf-418b-be87-230fef9d04b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097172619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.2097172619
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.259832317
Short name T147
Test name
Test status
Simulation time 671830188 ps
CPU time 35.64 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:19:27 PM PST 24
Peak memory 283240 kb
Host smart-32f426cc-588a-428c-b85e-a22904a619db
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259832317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.259832317
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1323251243
Short name T532
Test name
Test status
Simulation time 32952978930 ps
CPU time 415.89 seconds
Started Feb 25 01:18:56 PM PST 24
Finished Feb 25 01:25:53 PM PST 24
Peak memory 202400 kb
Host smart-da6063e9-49d2-4149-bb9b-7045de0053ea
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323251243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.1323251243
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.2918896074
Short name T642
Test name
Test status
Simulation time 1409194692 ps
CPU time 13.88 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:19:04 PM PST 24
Peak memory 202616 kb
Host smart-75c65e3d-b6a3-45da-973f-0d769c84b53c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918896074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2918896074
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3430965429
Short name T18
Test name
Test status
Simulation time 28761324385 ps
CPU time 213.81 seconds
Started Feb 25 01:18:54 PM PST 24
Finished Feb 25 01:22:28 PM PST 24
Peak memory 335356 kb
Host smart-28f22f11-fb4e-475a-9dab-a061197fb11c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430965429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3430965429
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.1565041258
Short name T202
Test name
Test status
Simulation time 1722584627 ps
CPU time 35.58 seconds
Started Feb 25 01:18:49 PM PST 24
Finished Feb 25 01:19:25 PM PST 24
Peak memory 287300 kb
Host smart-1fdf5b9c-393c-433d-b9ba-d95820141664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565041258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1565041258
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2803942648
Short name T319
Test name
Test status
Simulation time 10980348725 ps
CPU time 371.33 seconds
Started Feb 25 01:18:49 PM PST 24
Finished Feb 25 01:25:01 PM PST 24
Peak memory 202468 kb
Host smart-d6f32938-e6ed-4b0f-bfca-09a841e190e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803942648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.2803942648
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.236190681
Short name T292
Test name
Test status
Simulation time 1377422295 ps
CPU time 28.65 seconds
Started Feb 25 01:18:49 PM PST 24
Finished Feb 25 01:19:19 PM PST 24
Peak memory 217448 kb
Host smart-7964922b-3b70-40d4-9f02-2c27735136c7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236190681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.236190681
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.678485451
Short name T347
Test name
Test status
Simulation time 7461493778 ps
CPU time 1225.54 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:39:16 PM PST 24
Peak memory 378312 kb
Host smart-71ecc332-9d83-4148-9804-861396ba4141
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678485451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_access_during_key_req.678485451
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.4192695247
Short name T756
Test name
Test status
Simulation time 12511500 ps
CPU time 0.63 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:18:52 PM PST 24
Peak memory 202012 kb
Host smart-e4478d43-72e5-4edc-b61a-f79fb0ed6479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192695247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.4192695247
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.3286986889
Short name T795
Test name
Test status
Simulation time 162281303745 ps
CPU time 822.48 seconds
Started Feb 25 01:18:51 PM PST 24
Finished Feb 25 01:32:34 PM PST 24
Peak memory 202352 kb
Host smart-767ea6f8-730a-48a6-a746-babbed2850ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286986889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
3286986889
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.624981005
Short name T765
Test name
Test status
Simulation time 12897533981 ps
CPU time 415.42 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:25:46 PM PST 24
Peak memory 370076 kb
Host smart-f9c938a3-272f-4982-a6e0-f3c0a1515b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624981005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.624981005
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.3628666651
Short name T548
Test name
Test status
Simulation time 49249760447 ps
CPU time 115.77 seconds
Started Feb 25 01:18:54 PM PST 24
Finished Feb 25 01:20:50 PM PST 24
Peak memory 210604 kb
Host smart-3da17f13-e59c-4433-b53f-4758e7f7f4ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628666651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.3628666651
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.3434528650
Short name T303
Test name
Test status
Simulation time 1482375343 ps
CPU time 46.8 seconds
Started Feb 25 01:18:52 PM PST 24
Finished Feb 25 01:19:39 PM PST 24
Peak memory 272916 kb
Host smart-6bfa744c-9c63-42e0-9a69-3d5e1b6bd3fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434528650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.3434528650
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2811674277
Short name T312
Test name
Test status
Simulation time 10545075713 ps
CPU time 79.1 seconds
Started Feb 25 01:18:56 PM PST 24
Finished Feb 25 01:20:16 PM PST 24
Peak memory 218768 kb
Host smart-cf7b0829-8678-4dce-a57b-da4de2544da8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811674277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.2811674277
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.4290516408
Short name T213
Test name
Test status
Simulation time 18810170227 ps
CPU time 273.19 seconds
Started Feb 25 01:18:53 PM PST 24
Finished Feb 25 01:23:26 PM PST 24
Peak memory 202400 kb
Host smart-407c9423-bf9c-4455-b2a3-40cb3080f099
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290516408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.4290516408
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.3988783395
Short name T305
Test name
Test status
Simulation time 19838489952 ps
CPU time 1504.28 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:43:55 PM PST 24
Peak memory 375260 kb
Host smart-b47b0190-c702-472e-90d5-6601c08fe803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988783395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.3988783395
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1884013371
Short name T647
Test name
Test status
Simulation time 1408365175 ps
CPU time 146.52 seconds
Started Feb 25 01:18:54 PM PST 24
Finished Feb 25 01:21:21 PM PST 24
Peak memory 367004 kb
Host smart-46c69417-925d-4dd6-b14c-13ecb6b126e7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884013371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1884013371
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2067891288
Short name T136
Test name
Test status
Simulation time 10447815151 ps
CPU time 342.45 seconds
Started Feb 25 01:18:50 PM PST 24
Finished Feb 25 01:24:33 PM PST 24
Peak memory 202440 kb
Host smart-dcc5441e-4c9b-442b-9bac-10cd799dccae
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067891288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.2067891288
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3812466414
Short name T126
Test name
Test status
Simulation time 346657308 ps
CPU time 6.72 seconds
Started Feb 25 01:18:51 PM PST 24
Finished Feb 25 01:18:58 PM PST 24
Peak memory 202524 kb
Host smart-9757a5ad-a509-4614-975b-5dbb71ce862f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812466414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3812466414
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.2684414513
Short name T800
Test name
Test status
Simulation time 2903672417 ps
CPU time 248.21 seconds
Started Feb 25 01:18:51 PM PST 24
Finished Feb 25 01:23:00 PM PST 24
Peak memory 344604 kb
Host smart-2e3a4591-8478-4527-852e-3edad29d1fd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684414513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2684414513
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.342653935
Short name T138
Test name
Test status
Simulation time 742170446 ps
CPU time 15.13 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:19:05 PM PST 24
Peak memory 202344 kb
Host smart-e21dc34b-b679-4c52-9850-1134fd193906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342653935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.342653935
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.2546122546
Short name T704
Test name
Test status
Simulation time 172157461502 ps
CPU time 3991.88 seconds
Started Feb 25 01:18:56 PM PST 24
Finished Feb 25 02:25:29 PM PST 24
Peak memory 385476 kb
Host smart-e5561d6f-76dd-4a61-b0f7-85d66b113f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546122546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.2546122546
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2039101343
Short name T552
Test name
Test status
Simulation time 4977749357 ps
CPU time 353.89 seconds
Started Feb 25 01:18:48 PM PST 24
Finished Feb 25 01:24:43 PM PST 24
Peak memory 210628 kb
Host smart-f2167823-b944-4c58-a39a-2a23123076a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039101343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.2039101343
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3483408446
Short name T123
Test name
Test status
Simulation time 682021562 ps
CPU time 25.72 seconds
Started Feb 25 01:18:49 PM PST 24
Finished Feb 25 01:19:16 PM PST 24
Peak memory 210652 kb
Host smart-f3b61da7-07b7-4a50-a15c-6b237a3760c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483408446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3483408446
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.26991092
Short name T270
Test name
Test status
Simulation time 8783281456 ps
CPU time 961.07 seconds
Started Feb 25 01:19:00 PM PST 24
Finished Feb 25 01:35:02 PM PST 24
Peak memory 369028 kb
Host smart-8fdc83d3-7e7a-420c-8f99-94a85de5388d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26991092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.sram_ctrl_access_during_key_req.26991092
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.982991626
Short name T616
Test name
Test status
Simulation time 36353701 ps
CPU time 0.69 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:19:03 PM PST 24
Peak memory 201884 kb
Host smart-3595f9c8-ae64-4b3c-914e-33582a774922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982991626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.982991626
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.1893700334
Short name T209
Test name
Test status
Simulation time 61631668023 ps
CPU time 1042.73 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:36:27 PM PST 24
Peak memory 202404 kb
Host smart-034ef699-e8ef-4272-bd67-f91f904388e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893700334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
1893700334
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.2301636639
Short name T368
Test name
Test status
Simulation time 28147946826 ps
CPU time 79.66 seconds
Started Feb 25 01:19:00 PM PST 24
Finished Feb 25 01:20:20 PM PST 24
Peak memory 210616 kb
Host smart-cf0fcb48-74cf-4556-b6ca-fb608d8ffd66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301636639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.2301636639
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.3800966677
Short name T568
Test name
Test status
Simulation time 771220128 ps
CPU time 163.47 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:21:45 PM PST 24
Peak memory 367992 kb
Host smart-dda5bf94-46d6-4934-a15f-bdafa2176cb3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800966677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.3800966677
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1154687016
Short name T657
Test name
Test status
Simulation time 1551545874 ps
CPU time 131.3 seconds
Started Feb 25 01:19:03 PM PST 24
Finished Feb 25 01:21:15 PM PST 24
Peak memory 211376 kb
Host smart-7658c145-50ab-416c-8060-70a9defd79ff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154687016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1154687016
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.1847600226
Short name T710
Test name
Test status
Simulation time 17127081902 ps
CPU time 257.05 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:23:21 PM PST 24
Peak memory 202400 kb
Host smart-5090a771-acda-42c1-93a3-ba0962ffda30
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847600226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.1847600226
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.330410733
Short name T437
Test name
Test status
Simulation time 77211245054 ps
CPU time 1214.36 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:39:16 PM PST 24
Peak memory 379364 kb
Host smart-d5ef02f9-644e-462e-a746-a4f26a43e8c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330410733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl
e_keys.330410733
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.654538890
Short name T407
Test name
Test status
Simulation time 3170103381 ps
CPU time 84.13 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:20:25 PM PST 24
Peak memory 310576 kb
Host smart-1691431c-0a04-42fc-94b4-069708330d0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654538890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr
am_ctrl_partial_access.654538890
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3160692465
Short name T181
Test name
Test status
Simulation time 32132739602 ps
CPU time 221.56 seconds
Started Feb 25 01:19:00 PM PST 24
Finished Feb 25 01:22:42 PM PST 24
Peak memory 202428 kb
Host smart-383b4a88-644a-4f16-8811-22a1919e0543
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160692465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.3160692465
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.2619336319
Short name T502
Test name
Test status
Simulation time 677453838 ps
CPU time 13.98 seconds
Started Feb 25 01:18:57 PM PST 24
Finished Feb 25 01:19:11 PM PST 24
Peak memory 202660 kb
Host smart-cd4b3587-960a-4e49-bf34-cf87a9aca5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619336319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2619336319
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3768264937
Short name T172
Test name
Test status
Simulation time 7285378410 ps
CPU time 627.51 seconds
Started Feb 25 01:18:58 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 334416 kb
Host smart-1930a20c-21f2-421d-a3c9-f44f7957758e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768264937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3768264937
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.747429405
Short name T506
Test name
Test status
Simulation time 701273443 ps
CPU time 13.71 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:19:15 PM PST 24
Peak memory 202336 kb
Host smart-35a47747-f61c-46f2-8491-ef30786118aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747429405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.747429405
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3806011080
Short name T317
Test name
Test status
Simulation time 773388329 ps
CPU time 59.22 seconds
Started Feb 25 01:18:58 PM PST 24
Finished Feb 25 01:19:57 PM PST 24
Peak memory 293324 kb
Host smart-fb103618-e1f2-4b57-9efc-c23b843d9089
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806011080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3806011080
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.292544537
Short name T161
Test name
Test status
Simulation time 1382684400 ps
CPU time 113.27 seconds
Started Feb 25 01:18:58 PM PST 24
Finished Feb 25 01:20:52 PM PST 24
Peak memory 293428 kb
Host smart-fd1be389-2810-430d-8971-5f0d094d698e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292544537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_access_during_key_req.292544537
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.389394030
Short name T551
Test name
Test status
Simulation time 21055758 ps
CPU time 0.71 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:19:03 PM PST 24
Peak memory 201884 kb
Host smart-549e4f5c-d4b0-4891-8bb1-6a4044d0abda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389394030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.389394030
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1003789110
Short name T313
Test name
Test status
Simulation time 72079054642 ps
CPU time 1545.53 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:44:50 PM PST 24
Peak memory 202500 kb
Host smart-a1fa2c3b-422f-446d-8d9f-230b76ab6028
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003789110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1003789110
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.638760664
Short name T709
Test name
Test status
Simulation time 57150069188 ps
CPU time 960.49 seconds
Started Feb 25 01:18:59 PM PST 24
Finished Feb 25 01:35:00 PM PST 24
Peak memory 368020 kb
Host smart-f9b639c8-30fd-4c9a-92f1-b7d38a13b7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638760664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable
.638760664
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.4205384827
Short name T326
Test name
Test status
Simulation time 19229214067 ps
CPU time 100.82 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:20:43 PM PST 24
Peak memory 210560 kb
Host smart-48d482ba-8566-4fd0-8984-99eed1aea1b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205384827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.4205384827
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.4128360395
Short name T463
Test name
Test status
Simulation time 1457773614 ps
CPU time 41.59 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:19:44 PM PST 24
Peak memory 257656 kb
Host smart-b6d2e535-4c90-4e6d-a281-aff48e144859
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128360395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.4128360395
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2320405343
Short name T380
Test name
Test status
Simulation time 17386116846 ps
CPU time 151.73 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:21:34 PM PST 24
Peak memory 211476 kb
Host smart-8bddec15-d43d-455b-b0b7-9af180c336a2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320405343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.2320405343
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.1361694535
Short name T39
Test name
Test status
Simulation time 15759286773 ps
CPU time 244.54 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:23:09 PM PST 24
Peak memory 202572 kb
Host smart-33980782-216f-410c-a654-25d62b6c2f58
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361694535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.1361694535
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.1236482496
Short name T541
Test name
Test status
Simulation time 7823431917 ps
CPU time 1251.33 seconds
Started Feb 25 01:18:58 PM PST 24
Finished Feb 25 01:39:50 PM PST 24
Peak memory 377404 kb
Host smart-ab468e76-7806-4645-bf2b-f7713849f147
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236482496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.1236482496
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.2425392446
Short name T417
Test name
Test status
Simulation time 1740791865 ps
CPU time 32.63 seconds
Started Feb 25 01:18:56 PM PST 24
Finished Feb 25 01:19:31 PM PST 24
Peak memory 269220 kb
Host smart-64f64ba1-1dde-4fef-8d73-48600f864fa3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425392446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.2425392446
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1305394955
Short name T487
Test name
Test status
Simulation time 33426193237 ps
CPU time 400.01 seconds
Started Feb 25 01:19:02 PM PST 24
Finished Feb 25 01:25:42 PM PST 24
Peak memory 210552 kb
Host smart-4b53b10b-34a0-439a-b895-f5d267a58dc0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305394955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.1305394955
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.393057134
Short name T35
Test name
Test status
Simulation time 680436460 ps
CPU time 6.95 seconds
Started Feb 25 01:19:04 PM PST 24
Finished Feb 25 01:19:11 PM PST 24
Peak memory 202556 kb
Host smart-14d41a98-9153-4147-a6ba-4f203af17a57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393057134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.393057134
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.818215694
Short name T828
Test name
Test status
Simulation time 21156160140 ps
CPU time 858.39 seconds
Started Feb 25 01:19:00 PM PST 24
Finished Feb 25 01:33:19 PM PST 24
Peak memory 375208 kb
Host smart-fe211d60-cc50-4d3b-bac1-f32e0d6d00d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818215694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.818215694
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1635587663
Short name T617
Test name
Test status
Simulation time 4599654064 ps
CPU time 83.98 seconds
Started Feb 25 01:19:01 PM PST 24
Finished Feb 25 01:20:25 PM PST 24
Peak memory 306756 kb
Host smart-333f39e2-5440-43e0-aefe-d21e585f71e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635587663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1635587663
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1346364352
Short name T265
Test name
Test status
Simulation time 3618273064 ps
CPU time 242.46 seconds
Started Feb 25 01:19:03 PM PST 24
Finished Feb 25 01:23:06 PM PST 24
Peak memory 202424 kb
Host smart-413508da-e050-4a1b-9f5f-75dece879442
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346364352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.1346364352
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1224165473
Short name T661
Test name
Test status
Simulation time 1617348991 ps
CPU time 137.81 seconds
Started Feb 25 01:19:09 PM PST 24
Finished Feb 25 01:21:28 PM PST 24
Peak memory 357744 kb
Host smart-6b5e2d7a-059b-4602-bbbf-da46635b7246
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224165473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.1224165473
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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