Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	284324702	1			T1	62686		T2	16354		T3	387698
instr_valid_dis	256349122	1			T1	62686		T2	16354		T3	387698
instr_en	17147861	1			T12	469212		T15	20000		T113	443390

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	7726174	1			T10	55496		T12	143464		T31	51556
sram_ifetch_valid_disable	257151720	1			T1	62686		T2	16354		T3	387698
sram_ifetch_enable	19446808	1			T10	225242		T12	194656		T16	87026

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	284324702	1			T1	62686		T2	16354		T3	387698
hw_debug_en_valid_off	257255258	1			T1	62686		T2	16354		T3	387698
hw_debug_en_on	18280146	1			T10	307894		T12	162526		T16	103802

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	257151720	1			T1	62686		T2	16354		T3	387698
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	246949624	1			T1	62686		T2	16354		T3	387698
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	6328165	1			T12	131092		T113	77204		T115	168632
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3140362	1			T10	38438		T12	5772		T31	27886
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	906094	1			T10	38438		T15	15368		T116	40554
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1210080	1			T12	5772		T113	73208		T32	26624
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3272348	1			T10	17058		T12	86936		T15	33586
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1268144	1			T10	17058		T15	15942		T25	26982
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1059834	1			T12	86936		T113	70098		T115	32264
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6669036	1			T10	116250		T12	47960		T16	24978
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2559866	1			T10	116250		T16	24978		T15	75380
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2597598	1			T12	47960		T113	31990		T115	79542

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7782558	1			T12	194656		T15	20000		T113	206360
lc_exec_en	8338762	1			T10	174586		T12	27630		T16	78824
valid_exec_dis	254731264	1			T1	62686		T2	16354		T3	387698
invalid_exec_dis	27172982	1			T10	280738		T12	338120		T16	87026