Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	117226257	1			T1	1469		T2	7469		T3	176324
triple_byte_access	2703707	1			T1	3542		T2	137		T3	3439
halfword_access	4147312	1			T1	6472		T2	220		T3	5314
byte_access	5803077	1			T1	12505		T2	284		T3	7045
zero_access	1757213	1			T1	7355		T2	67		T3	1727

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65386952

1

T1

15549

T2

4138

T3

97207

auto[1]

66250614

1

T1

15794

T2

4039

T3

96642

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	58070164	1			T1	110		T2	3776		T3	88327
auto[0]	triple_byte_access	1284966	1			T1	628		T2	71		T3	1705
auto[0]	halfword_access	2021292	1			T1	2210		T2	110		T3	2758
auto[0]	byte_access	2963489	1			T1	6700		T2	149		T3	3553
auto[0]	zero_access	1047041	1			T1	5901		T2	32		T3	864
auto[1]	word_access	59156093	1			T1	1359		T2	3693		T3	87997
auto[1]	triple_byte_access	1418741	1			T1	2914		T2	66		T3	1734
auto[1]	halfword_access	2126020	1			T1	4262		T2	110		T3	2556
auto[1]	byte_access	2839588	1			T1	5805		T2	135		T3	3492
auto[1]	zero_access	710172	1			T1	1454		T2	35		T3	863