Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14353359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

138397651

1

T1

701

T2

182646

T3

2992

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	75094393	1			T1	2048		T2	100505		T3	724
values[0x0]	37396725	1			T1	715		T2	48309		T3	1079
values[0x1]	40259892	1			T1	1432		T2	52090		T3	1189

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7323613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145427397

1

T1

2462

T2

191743

T3

2992

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	471469	1			T1	15		T2	884		T3	13
valid_sources[0x01]	435876	1			T1	14		T2	753		T3	8
valid_sources[0x02]	467332	1			T1	12		T2	826		T3	10
valid_sources[0x03]	581305	1			T1	14		T2	757		T3	10
valid_sources[0x04]	802042	1			T1	19		T2	807		T3	13
valid_sources[0x05]	1970338	1			T1	9		T2	801		T3	12
valid_sources[0x06]	481346	1			T1	11		T2	786		T3	12
valid_sources[0x07]	488373	1			T1	25		T2	809		T3	7
valid_sources[0x08]	435587	1			T1	27		T2	748		T3	9
valid_sources[0x09]	3581854	1			T1	22		T2	744		T3	9
valid_sources[0x0a]	457971	1			T1	19		T2	790		T3	8
valid_sources[0x0b]	552361	1			T1	22		T2	754		T3	13
valid_sources[0x0c]	432522	1			T1	19		T2	751		T3	14
valid_sources[0x0d]	440372	1			T1	11		T2	779		T3	7
valid_sources[0x0e]	492327	1			T1	15		T2	769		T3	7
valid_sources[0x0f]	452905	1			T1	14		T2	785		T3	9
valid_sources[0x10]	1916342	1			T1	20		T2	770		T3	7
valid_sources[0x11]	498658	1			T1	20		T2	792		T3	8
valid_sources[0x12]	468508	1			T1	21		T2	789		T3	15
valid_sources[0x13]	468173	1			T1	21		T2	806		T3	14
valid_sources[0x14]	1623662	1			T1	18		T2	807		T3	14
valid_sources[0x15]	474620	1			T1	18		T2	784		T3	13
valid_sources[0x16]	457908	1			T1	24		T2	738		T3	17
valid_sources[0x17]	442472	1			T1	13		T2	813		T3	15
valid_sources[0x18]	510001	1			T1	12		T2	775		T3	12
valid_sources[0x19]	457867	1			T1	24		T2	779		T3	12
valid_sources[0x1a]	465429	1			T1	27		T2	818		T3	10
valid_sources[0x1b]	503560	1			T1	22		T2	722		T3	8
valid_sources[0x1c]	446458	1			T1	12		T2	785		T3	11
valid_sources[0x1d]	467647	1			T1	16		T2	793		T3	8
valid_sources[0x1e]	457763	1			T1	11		T2	722		T3	9
valid_sources[0x1f]	968763	1			T1	14		T2	794		T3	10
valid_sources[0x20]	473704	1			T1	14		T2	761		T3	14
valid_sources[0x21]	482244	1			T1	14		T2	749		T3	7
valid_sources[0x22]	444726	1			T1	8		T2	716		T3	12
valid_sources[0x23]	559961	1			T1	15		T2	790		T3	7
valid_sources[0x24]	434343	1			T1	16		T2	814		T3	8
valid_sources[0x25]	441626	1			T1	19		T2	817		T3	9
valid_sources[0x26]	666828	1			T1	9		T2	809		T3	12
valid_sources[0x27]	511204	1			T1	20		T2	780		T3	10
valid_sources[0x28]	513738	1			T1	17		T2	804		T3	9
valid_sources[0x29]	459490	1			T1	12		T2	774		T3	11
valid_sources[0x2a]	460901	1			T1	23		T2	790		T3	15
valid_sources[0x2b]	485827	1			T1	11		T2	802		T3	15
valid_sources[0x2c]	1700547	1			T1	9		T2	745		T3	8
valid_sources[0x2d]	461716	1			T1	9		T2	762		T3	8
valid_sources[0x2e]	2040241	1			T1	11		T2	791		T3	9
valid_sources[0x2f]	439536	1			T1	17		T2	809		T3	13
valid_sources[0x30]	438883	1			T1	16		T2	767		T3	6
valid_sources[0x31]	450054	1			T1	15		T2	771		T3	20
valid_sources[0x32]	464401	1			T1	7		T2	768		T3	17
valid_sources[0x33]	478988	1			T1	23		T2	755		T3	11
valid_sources[0x34]	441672	1			T1	27		T2	822		T3	7
valid_sources[0x35]	443740	1			T1	10		T2	845		T3	13
valid_sources[0x36]	497292	1			T1	6		T2	783		T3	13
valid_sources[0x37]	1513531	1			T1	14		T2	827		T3	11
valid_sources[0x38]	451687	1			T1	11		T2	835		T3	12
valid_sources[0x39]	447050	1			T1	7		T2	796		T3	12
valid_sources[0x3a]	458848	1			T1	12		T2	777		T3	10
valid_sources[0x3b]	458984	1			T1	13		T2	840		T3	10
valid_sources[0x3c]	826628	1			T1	22		T2	709		T3	11
valid_sources[0x3d]	471622	1			T1	16		T2	800		T3	12
valid_sources[0x3e]	456393	1			T1	17		T2	735		T3	12
valid_sources[0x3f]	445052	1			T1	25		T2	792		T3	8
valid_sources[0x40]	440688	1			T1	18		T2	799		T3	7
valid_sources[0x41]	576967	1			T1	31		T2	784		T3	11
valid_sources[0x42]	435758	1			T1	11		T2	814		T3	15
valid_sources[0x43]	446956	1			T1	10		T2	773		T3	10
valid_sources[0x44]	481904	1			T1	15		T2	834		T3	12
valid_sources[0x45]	1036834	1			T1	20		T2	805		T3	12
valid_sources[0x46]	490068	1			T1	8		T2	782		T3	9
valid_sources[0x47]	499319	1			T1	14		T2	725		T3	10
valid_sources[0x48]	510173	1			T1	16		T2	789		T3	15
valid_sources[0x49]	471393	1			T1	15		T2	787		T3	14
valid_sources[0x4a]	484726	1			T1	20		T2	788		T3	16
valid_sources[0x4b]	550523	1			T1	19		T2	792		T3	14
valid_sources[0x4c]	603260	1			T1	13		T2	836		T3	16
valid_sources[0x4d]	885060	1			T1	7		T2	827		T3	11
valid_sources[0x4e]	461688	1			T1	28		T2	736		T3	9
valid_sources[0x4f]	436461	1			T1	17		T2	709		T3	14
valid_sources[0x50]	439107	1			T1	19		T2	783		T3	12
valid_sources[0x51]	466321	1			T1	20		T2	782		T3	12
valid_sources[0x52]	2077634	1			T1	11		T2	775		T3	15
valid_sources[0x53]	484508	1			T1	20		T2	824		T3	7
valid_sources[0x54]	497589	1			T1	13		T2	759		T3	18
valid_sources[0x55]	460723	1			T1	8		T2	809		T3	14
valid_sources[0x56]	453087	1			T1	16		T2	711		T3	12
valid_sources[0x57]	2324337	1			T1	20		T2	807		T3	11
valid_sources[0x58]	443891	1			T1	26		T2	816		T3	16
valid_sources[0x59]	541862	1			T1	17		T2	827		T3	16
valid_sources[0x5a]	519401	1			T1	15		T2	774		T3	14
valid_sources[0x5b]	495450	1			T1	11		T2	763		T3	13
valid_sources[0x5c]	441015	1			T1	18		T2	790		T3	9
valid_sources[0x5d]	524601	1			T1	20		T2	805		T3	11
valid_sources[0x5e]	446476	1			T1	19		T2	834		T3	9
valid_sources[0x5f]	442502	1			T1	20		T2	822		T3	14
valid_sources[0x60]	455489	1			T1	17		T2	838		T3	12
valid_sources[0x61]	487093	1			T1	21		T2	777		T3	5
valid_sources[0x62]	446163	1			T1	15		T2	824		T3	12
valid_sources[0x63]	453712	1			T1	12		T2	798		T3	7
valid_sources[0x64]	447762	1			T1	9		T2	776		T3	18
valid_sources[0x65]	465347	1			T1	16		T2	740		T3	11
valid_sources[0x66]	545589	1			T1	17		T2	815		T3	6
valid_sources[0x67]	484295	1			T1	11		T2	767		T3	10
valid_sources[0x68]	442952	1			T1	15		T2	798		T3	15
valid_sources[0x69]	1732276	1			T1	19		T2	773		T3	11
valid_sources[0x6a]	467870	1			T1	12		T2	786		T3	15
valid_sources[0x6b]	466844	1			T1	17		T2	842		T3	14
valid_sources[0x6c]	476375	1			T1	15		T2	814		T3	15
valid_sources[0x6d]	439054	1			T1	17		T2	735		T3	9
valid_sources[0x6e]	511924	1			T1	18		T2	666		T3	10
valid_sources[0x6f]	760404	1			T1	19		T2	761		T3	12
valid_sources[0x70]	1603699	1			T1	15		T2	773		T3	16
valid_sources[0x71]	479556	1			T1	20		T2	720		T3	13
valid_sources[0x72]	435659	1			T1	16		T2	749		T3	11
valid_sources[0x73]	434354	1			T1	14		T2	792		T3	9
valid_sources[0x74]	430889	1			T1	14		T2	751		T3	15
valid_sources[0x75]	1179767	1			T1	14		T2	803		T3	12
valid_sources[0x76]	498835	1			T1	17		T2	787		T3	12
valid_sources[0x77]	452290	1			T1	26		T2	783		T3	8
valid_sources[0x78]	434326	1			T1	25		T2	737		T3	13
valid_sources[0x79]	445059	1			T1	8		T2	809		T3	10
valid_sources[0x7a]	502646	1			T1	13		T2	822		T3	12
valid_sources[0x7b]	515843	1			T1	19		T2	883		T3	13
valid_sources[0x7c]	439065	1			T1	11		T2	760		T3	11
valid_sources[0x7d]	575920	1			T1	15		T2	783		T3	12
valid_sources[0x7e]	561950	1			T1	15		T2	788		T3	10
valid_sources[0x7f]	463451	1			T1	14		T2	786		T3	12
valid_sources[0x80]	448758	1			T1	17		T2	805		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67873661

1

T1

364

T2

91361

T3

724

values[0x0]

all_enables

biggest_size

35258987

1

T1

170

T2

45555

T3

1079

values[0x1]

all_enables

biggest_size

35265003

1

T1

167

T2

45730

T3

1189

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33494	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

163215

1

T1

1

T2

13

T3

1361

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57468	1			T3	412		T4	41		T11	14
values[0x0]	66967	1			T2	22		T3	509		T7	3
values[0x1]	72274	1			T1	2		T2	22		T3	552

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24801	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

171908

1

T1

1

T2

19

T3

1416

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	556	1			T3	2		T12	1		T29	12
valid_sources[0x01]	679	1			T3	3		T29	3		T30	7
valid_sources[0x02]	1245	1			T3	1		T17	1		T29	15
valid_sources[0x03]	1159	1			T3	6		T29	13		T30	9
valid_sources[0x04]	1007	1			T3	1		T4	1		T12	1
valid_sources[0x05]	896	1			T3	2		T29	15		T30	6
valid_sources[0x06]	1000	1			T3	11		T4	2		T12	2
valid_sources[0x07]	747	1			T3	7		T4	1		T29	3
valid_sources[0x08]	830	1			T3	10		T4	1		T29	17
valid_sources[0x09]	967	1			T3	18		T8	1		T29	9
valid_sources[0x0a]	601	1			T29	20		T30	8		T49	1
valid_sources[0x0b]	744	1			T2	1		T3	3		T12	1
valid_sources[0x0c]	753	1			T2	1		T3	4		T29	9
valid_sources[0x0d]	638	1			T3	3		T29	15		T30	11
valid_sources[0x0e]	660	1			T3	9		T4	1		T29	9
valid_sources[0x0f]	535	1			T3	11		T4	1		T12	1
valid_sources[0x10]	752	1			T3	3		T12	1		T29	13
valid_sources[0x11]	787	1			T29	8		T30	6		T6	2
valid_sources[0x12]	780	1			T2	2		T3	2		T29	10
valid_sources[0x13]	749	1			T4	1		T29	14		T30	5
valid_sources[0x14]	952	1			T12	2		T29	8		T30	9
valid_sources[0x15]	588	1			T2	2		T3	1		T11	1
valid_sources[0x16]	867	1			T3	1		T29	18		T30	11
valid_sources[0x17]	734	1			T3	2		T29	18		T30	15
valid_sources[0x18]	659	1			T31	1		T29	15		T30	11
valid_sources[0x19]	650	1			T29	10		T30	10		T49	2
valid_sources[0x1a]	572	1			T3	10		T29	16		T30	12
valid_sources[0x1b]	1015	1			T29	15		T30	11		T49	2
valid_sources[0x1c]	605	1			T29	19		T30	13		T23	2
valid_sources[0x1d]	834	1			T3	8		T29	10		T30	16
valid_sources[0x1e]	726	1			T2	1		T3	24		T4	1
valid_sources[0x1f]	787	1			T3	5		T4	2		T11	5
valid_sources[0x20]	914	1			T3	16		T12	2		T29	16
valid_sources[0x21]	611	1			T3	3		T29	10		T30	8
valid_sources[0x22]	1123	1			T3	5		T29	14		T30	18
valid_sources[0x23]	702	1			T3	3		T12	1		T24	1
valid_sources[0x24]	604	1			T3	7		T4	1		T29	9
valid_sources[0x25]	640	1			T3	7		T12	1		T29	7
valid_sources[0x26]	979	1			T3	3		T4	1		T12	1
valid_sources[0x27]	601	1			T2	3		T29	14		T30	13
valid_sources[0x28]	615	1			T3	3		T29	11		T30	11
valid_sources[0x29]	764	1			T3	4		T29	11		T30	11
valid_sources[0x2a]	636	1			T3	1		T29	9		T30	6
valid_sources[0x2b]	812	1			T3	4		T29	11		T30	5
valid_sources[0x2c]	698	1			T3	13		T12	1		T16	1
valid_sources[0x2d]	827	1			T3	4		T29	10		T30	15
valid_sources[0x2e]	1072	1			T3	6		T29	5		T30	13
valid_sources[0x2f]	779	1			T2	1		T3	3		T29	12
valid_sources[0x30]	690	1			T2	1		T3	2		T29	14
valid_sources[0x31]	625	1			T3	3		T29	4		T30	18
valid_sources[0x32]	642	1			T3	5		T29	12		T30	6
valid_sources[0x33]	1127	1			T3	15		T29	13		T30	5
valid_sources[0x34]	780	1			T3	8		T29	14		T30	9
valid_sources[0x35]	1123	1			T3	3		T12	2		T29	9
valid_sources[0x36]	800	1			T12	1		T29	12		T30	13
valid_sources[0x37]	853	1			T3	6		T4	1		T29	11
valid_sources[0x38]	808	1			T2	1		T3	16		T29	16
valid_sources[0x39]	1012	1			T2	2		T3	13		T4	1
valid_sources[0x3a]	625	1			T3	1		T29	14		T30	6
valid_sources[0x3b]	722	1			T3	5		T4	1		T29	8
valid_sources[0x3c]	693	1			T3	4		T4	3		T11	9
valid_sources[0x3d]	650	1			T3	3		T29	14		T30	15
valid_sources[0x3e]	1173	1			T3	7		T29	6		T30	11
valid_sources[0x3f]	888	1			T2	1		T3	1		T29	19
valid_sources[0x40]	635	1			T3	3		T12	1		T29	5
valid_sources[0x41]	585	1			T3	8		T4	2		T29	16
valid_sources[0x42]	687	1			T2	1		T3	2		T12	1
valid_sources[0x43]	720	1			T3	16		T4	1		T29	9
valid_sources[0x44]	679	1			T3	4		T29	13		T30	8
valid_sources[0x45]	730	1			T3	8		T4	1		T29	7
valid_sources[0x46]	830	1			T3	8		T4	1		T12	1
valid_sources[0x47]	862	1			T2	1		T3	12		T25	3
valid_sources[0x48]	704	1			T3	13		T4	1		T29	11
valid_sources[0x49]	799	1			T3	3		T4	1		T11	6
valid_sources[0x4a]	865	1			T3	8		T29	15		T30	12
valid_sources[0x4b]	815	1			T3	11		T29	9		T30	12
valid_sources[0x4c]	825	1			T3	7		T11	8		T29	7
valid_sources[0x4d]	567	1			T3	2		T4	3		T14	3
valid_sources[0x4e]	868	1			T3	7		T29	14		T30	11
valid_sources[0x4f]	608	1			T3	2		T29	8		T30	7
valid_sources[0x50]	937	1			T3	3		T12	1		T29	11
valid_sources[0x51]	758	1			T3	3		T4	1		T29	16
valid_sources[0x52]	691	1			T3	6		T4	1		T29	17
valid_sources[0x53]	932	1			T3	6		T29	22		T30	11
valid_sources[0x54]	595	1			T3	4		T4	1		T12	1
valid_sources[0x55]	639	1			T3	4		T4	2		T11	1
valid_sources[0x56]	833	1			T2	1		T3	7		T51	1
valid_sources[0x57]	867	1			T3	8		T4	1		T12	1
valid_sources[0x58]	969	1			T3	2		T25	2		T29	7
valid_sources[0x59]	631	1			T4	1		T29	15		T30	17
valid_sources[0x5a]	988	1			T3	11		T4	2		T29	17
valid_sources[0x5b]	570	1			T3	8		T29	12		T30	12
valid_sources[0x5c]	770	1			T51	1		T29	12		T30	6
valid_sources[0x5d]	607	1			T3	1		T29	9		T30	8
valid_sources[0x5e]	1040	1			T3	3		T12	2		T29	9
valid_sources[0x5f]	712	1			T2	1		T3	10		T29	9
valid_sources[0x60]	662	1			T2	1		T3	10		T29	11
valid_sources[0x61]	636	1			T3	11		T4	1		T29	12
valid_sources[0x62]	827	1			T3	4		T29	9		T30	7
valid_sources[0x63]	593	1			T3	3		T29	19		T107	15
valid_sources[0x64]	874	1			T2	1		T3	7		T29	18
valid_sources[0x65]	931	1			T3	9		T4	1		T12	1
valid_sources[0x66]	1002	1			T3	4		T11	8		T29	11
valid_sources[0x67]	730	1			T3	3		T29	10		T30	10
valid_sources[0x68]	761	1			T3	5		T4	1		T29	16
valid_sources[0x69]	609	1			T3	3		T29	14		T30	12
valid_sources[0x6a]	848	1			T3	5		T12	2		T29	3
valid_sources[0x6b]	870	1			T3	8		T29	12		T30	12
valid_sources[0x6c]	635	1			T2	1		T3	6		T4	1
valid_sources[0x6d]	790	1			T3	10		T29	17		T30	11
valid_sources[0x6e]	642	1			T3	2		T7	10		T29	8
valid_sources[0x6f]	632	1			T3	5		T29	9		T30	8
valid_sources[0x70]	798	1			T2	1		T29	8		T30	7
valid_sources[0x71]	693	1			T3	9		T4	1		T25	1
valid_sources[0x72]	993	1			T2	1		T3	1		T29	9
valid_sources[0x73]	884	1			T3	5		T4	1		T29	13
valid_sources[0x74]	579	1			T3	2		T29	9		T30	19
valid_sources[0x75]	499	1			T3	8		T4	1		T29	4
valid_sources[0x76]	684	1			T3	9		T29	9		T30	7
valid_sources[0x77]	633	1			T2	2		T3	8		T12	1
valid_sources[0x78]	911	1			T29	8		T30	9		T49	1
valid_sources[0x79]	1201	1			T3	14		T29	18		T30	10
valid_sources[0x7a]	601	1			T3	4		T29	21		T30	9
valid_sources[0x7b]	611	1			T3	8		T4	1		T29	9
valid_sources[0x7c]	940	1			T4	1		T29	17		T30	12
valid_sources[0x7d]	882	1			T3	4		T11	3		T29	6
valid_sources[0x7e]	827	1			T3	5		T29	11		T30	11
valid_sources[0x7f]	724	1			T3	18		T29	7		T30	8
valid_sources[0x80]	570	1			T11	11		T29	7		T30	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44657

1

T3

361

T4

25

T11

6

values[0x0]

all_enables

biggest_size

59970

1

T2

12

T3

505

T4

6

values[0x1]

all_enables

biggest_size

58588

1

T1

1

T2

1

T3

495