Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14320618

1

T1

3494

T2

15924

T3

2611

full_word

135606657

1

T1

701

T2

158805

T3

3319

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	149926965	1			T1	4195		T2	174729		T3	5930
auto[TlIntgErrCmd]	87	1			T100	2		T101	8		T115	3
auto[TlIntgErrData]	114	1			T100	7		T101	6		T102	6
auto[TlIntgErrBoth]	109	1			T100	11		T101	6		T102	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72149747

1

T1

2048

T2

74330

T3

1326

auto[1]

77777528

1

T1

2147

T2

100399

T3

4604

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6997867	1			T1	1684		T2	6810		T3	530
auto[TlIntgErrNone]	partial	auto[1]	7322461	1			T1	1810		T2	9114		T3	2081
auto[TlIntgErrNone]	full_word	auto[0]	65151729	1			T1	364		T2	67520		T3	796
auto[TlIntgErrNone]	full_word	auto[1]	70454908	1			T1	337		T2	91285		T3	2523
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T100	1		T101	4		T115	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T100	1		T101	4		T115	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T117	1		T118	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T111	1		T118	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T100	2		T101	4		T102	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T100	5		T101	2		T102	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T112	1		T116	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T111	1		T121	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T100	5		T101	3		T102	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T100	5		T101	3		T102	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T116	1		T121	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T100	1		T111	1		T122	1