Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	856675	1			T1	264		T2	4957		T13	2030
auto[1]	7907376	1			T1	311		T2	647		T4	6
auto[2]	651361	1			T1	236		T2	2796		T13	1304
auto[3]	7670361	1			T1	273		T2	290		T4	8

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10009631	1			T1	22		T2	6926		T4	11
auto[1]	1601073	1			T1	109		T2	892		T4	1
auto[2]	1619908	1			T1	137		T2	776		T4	2
auto[3]	3855161	1			T1	816		T2	96		T10	48680

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5123263

1

T1

1084

T2

8690

T4

14

auto[1]

11962510

1

T14

151823

T17

92200

T18

109873

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	321408	1			T1	10		T2	4128		T13	1684
auto[0]	auto[0]	auto[1]	34160	1			T1	39		T2	395		T13	168
auto[0]	auto[0]	auto[2]	34169	1			T1	37		T2	395		T13	157
auto[0]	auto[0]	auto[3]	110833	1			T1	178		T2	39		T13	21
auto[0]	auto[1]	auto[0]	1339242	1			T1	7		T2	339		T4	6
auto[0]	auto[1]	auto[1]	163465	1			T1	49		T2	261		T10	243
auto[0]	auto[1]	auto[2]	180586	1			T1	28		T2	26		T10	2842
auto[0]	auto[1]	auto[3]	530175	1			T1	227		T2	21		T10	25114
auto[0]	auto[2]	auto[0]	233685	1			T1	3		T2	2348		T13	1034
auto[0]	auto[2]	auto[1]	32138	1			T1	16		T2	224		T13	100
auto[0]	auto[2]	auto[2]	22944	1			T1	31		T2	205		T13	156
auto[0]	auto[2]	auto[3]	79028	1			T1	186		T2	19		T13	14
auto[0]	auto[3]	auto[0]	1216698	1			T1	2		T2	111		T4	5
auto[0]	auto[3]	auto[1]	163086	1			T1	5		T2	12		T4	1
auto[0]	auto[3]	auto[2]	187503	1			T1	41		T2	150		T4	2
auto[0]	auto[3]	auto[3]	474143	1			T1	225		T2	17		T10	23566
auto[1]	auto[0]	auto[0]	11730	1			T129	758		T130	619		T131	1090
auto[1]	auto[0]	auto[1]	52677	1			T129	3411		T130	2909		T131	4807
auto[1]	auto[0]	auto[2]	53079	1			T129	3426		T130	3086		T131	4864
auto[1]	auto[0]	auto[3]	238619	1			T129	15079		T130	13716		T131	22128
auto[1]	auto[1]	auto[0]	3438132	1			T14	62597		T17	1658		T18	45546
auto[1]	auto[1]	auto[1]	575335	1			T14	6170		T17	6907		T18	4464
auto[1]	auto[1]	auto[2]	537200	1			T14	6285		T17	7335		T18	4483
auto[1]	auto[1]	auto[3]	1143241	1			T14	625		T17	30196		T18	445
auto[1]	auto[2]	auto[0]	10342	1			T132	1		T129	719		T130	629
auto[1]	auto[2]	auto[1]	47158	1			T129	3093		T130	2705		T131	4445
auto[1]	auto[2]	auto[2]	41047	1			T129	2860		T130	1989		T131	4051
auto[1]	auto[2]	auto[3]	185019	1			T129	12691		T130	8984		T131	18601
auto[1]	auto[3]	auto[0]	3438394	1			T14	63073		T17	1572		T18	45346
auto[1]	auto[3]	auto[1]	533054	1			T14	6229		T17	7504		T18	4586
auto[1]	auto[3]	auto[2]	563380	1			T14	6243		T17	6691		T18	4533
auto[1]	auto[3]	auto[3]	1094103	1			T14	601		T17	30337		T18	470