Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	990346439	163513	0	0
ctrl_regwen_rd_A	990346439	8728	0	0
exec_rd_A	990346439	8231	0	0
exec_regwen_rd_A	990346439	9141	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990346439	163513	0	0
T3	48601	1643	0	0
T4	155635	0	0	0
T7	1215	0	0	0
T8	34413	0	0	0
T9	44410	0	0	0
T10	157127	0	0	0
T11	339021	0	0	0
T12	224133	0	0	0
T13	898192	0	0	0
T16	34144	0	0	0
T29	0	3693	0	0
T30	0	1974	0	0
T38	0	3126	0	0
T43	0	834	0	0
T44	0	939	0	0
T45	0	4306	0	0
T46	0	523	0	0
T47	0	2002	0	0
T48	0	1455	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990346439	8728	0	0
T18	252821	0	0	0
T22	142179	0	0	0
T27	691493	0	0	0
T29	136098	746	0	0
T30	126182	486	0	0
T44	0	175	0	0
T45	0	914	0	0
T46	0	156	0	0
T48	0	354	0	0
T49	334310	0	0	0
T62	750517	0	0	0
T63	590042	0	0	0
T103	0	649	0	0
T104	0	357	0	0
T105	0	349	0	0
T106	0	273	0	0
T107	159396	0	0	0
T108	37143	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990346439	8231	0	0
T18	252821	0	0	0
T22	142179	0	0	0
T27	691493	0	0	0
T29	136098	559	0	0
T30	126182	502	0	0
T44	0	220	0	0
T45	0	902	0	0
T46	0	141	0	0
T48	0	275	0	0
T49	334310	0	0	0
T62	750517	0	0	0
T63	590042	0	0	0
T103	0	529	0	0
T104	0	483	0	0
T105	0	413	0	0
T106	0	292	0	0
T107	159396	0	0	0
T108	37143	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990346439	9141	0	0
T18	252821	0	0	0
T22	142179	0	0	0
T27	691493	0	0	0
T29	136098	610	0	0
T30	126182	575	0	0
T44	0	225	0	0
T45	0	1000	0	0
T46	0	96	0	0
T48	0	364	0	0
T49	334310	0	0	0
T62	750517	0	0	0
T63	590042	0	0	0
T103	0	678	0	0
T104	0	507	0	0
T105	0	451	0	0
T106	0	268	0	0
T107	159396	0	0	0
T108	37143	0	0	0