Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	336153630	1			T1	357168		T2	18510		T3	225394
instr_valid_dis	284079097	1			T1	357168		T2	18510		T3	225394
instr_en	40106108	1			T8	114380		T14	133998		T4	22400

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17324989	1			T8	106056		T14	36686		T4	86312
sram_ifetch_valid_disable	289185043	1			T1	357168		T2	18510		T3	225394
sram_ifetch_enable	29643598	1			T8	124460		T14	173786		T4	194944

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	336153630	1			T1	357168		T2	18510		T3	225394
hw_debug_en_valid_off	291082395	1			T1	357168		T2	18510		T3	225394
hw_debug_en_on	29527147	1			T8	188758		T14	74068		T4	187014

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	289185043	1			T1	357168		T2	18510		T3	225394
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	269717492	1			T1	357168		T2	18510		T3	225394
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13563850	1			T8	65242		T14	23530		T58	92164
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5794502	1			T8	44362		T14	24868		T58	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1095334	1			T8	11786		T58	20000		T59	17982
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4284270	1			T8	16862		T14	24868		T107	56990
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	9866797	1			T8	47624		T14	11818		T4	86312
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1647047	1			T4	41652		T59	13588		T6	154636
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	7738708	1			T8	32118		T14	11818		T58	9502
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6946514	1			T8	119788		T14	62250		T4	31862
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2557082	1			T8	54546		T14	55076		T58	17052
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3249618	1			T8	65242		T14	7174		T58	44146

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13691404	1			T8	158		T14	73782		T4	22400
lc_exec_en	12713836	1			T8	21346		T4	68840		T58	11078
valid_exec_dis	282972117	1			T1	357168		T2	18510		T3	225394
invalid_exec_dis	46968587	1			T8	230516		T14	210472		T4	281256