| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.263626615 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3307901205 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3266338767 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3611361429 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2196972733 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1203249041 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2122493635 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1012152840 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2996859434 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3262790085 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.724739999 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.132141598 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.392646826 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.65783354 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3438670985 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1216172562 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2259775372 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1609558178 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.669714082 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2323105418 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2304522606 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.799621299 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.236037245 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2515243223 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1750730752 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3019574661 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1216640319 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2749200657 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2314420391 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2224198650 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2792042708 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1836425715 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4024468422 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.662048430 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2517678041 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3630594431 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.289225715 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.888879545 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3054715742 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3693849713 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1640904613 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3234292445 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4062969207 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.474979233 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2014092500 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2914944198 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.76097942 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2199588010 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.708012661 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2456469117 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3672956208 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2039922355 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3514600522 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.564582800 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4040559206 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.433540815 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2962192796 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1971030972 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2280405254 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4144622834 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3693307418 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2087856673 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4189194573 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1695024910 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.958551069 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3722448806 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.490620929 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.788200379 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1282283047 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2915897715 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1151305846 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1485109005 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2815375356 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1897431635 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4252571981 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2826699857 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.442804283 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.670145585 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2849833597 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1386494420 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3775922984 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2749375506 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.576888116 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3062606595 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.344243806 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.212365453 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3894522050 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1303390083 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3671446732 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.183050574 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3056690308 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2173342124 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.868098199 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3372006096 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3996916581 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.808236714 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1253686764 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2375312970 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.901931248 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.975307254 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1776852922 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.249706790 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1688211361 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3100830949 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.717359525 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.810598952 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3141575783 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.375256334 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4158971936 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1972583593 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.420881133 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2875445915 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.444641824 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.785375703 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2727243116 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1621055822 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1076043252 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3688185520 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2508903949 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1813677967 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3787408315 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3196355668 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2926115577 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3507775463 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3170443321 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3623899850 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2992524140 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3389088386 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1496611296 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.912044633 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.291162448 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.2871769338 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1287984087 |
| /workspace/coverage/default/0.sram_ctrl_executable.2560081238 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.3595195078 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1757664284 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1547458540 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.2407889079 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3154054391 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.1515220606 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1039642353 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1463297245 |
| /workspace/coverage/default/0.sram_ctrl_regwen.4191401213 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.675130103 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2812791106 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1054929393 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.395739413 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1476758466 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2741533170 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2486671496 |
| /workspace/coverage/default/1.sram_ctrl_bijection.408330792 |
| /workspace/coverage/default/1.sram_ctrl_executable.3364503530 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.4007964413 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.2520147678 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1924526929 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.1337169751 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2644310870 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1863088223 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3675625727 |
| /workspace/coverage/default/1.sram_ctrl_regwen.19261464 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.3732523415 |
| /workspace/coverage/default/1.sram_ctrl_smoke.838537048 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.573081667 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3199709404 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3797288140 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.669950765 |
| /workspace/coverage/default/10.sram_ctrl_bijection.2516765999 |
| /workspace/coverage/default/10.sram_ctrl_executable.3966613309 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.3000856509 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3398654999 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1285002895 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3252802005 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1503052664 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2639230708 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.4114897441 |
| /workspace/coverage/default/10.sram_ctrl_regwen.2106000936 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2441854664 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.938152638 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3171989890 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3878959844 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3280956375 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1710976003 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2669295281 |
| /workspace/coverage/default/11.sram_ctrl_bijection.2313348608 |
| /workspace/coverage/default/11.sram_ctrl_executable.543150256 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.945520280 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2686751781 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3313313605 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.879361944 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1486357945 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1565943554 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2379998631 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.1567320031 |
| /workspace/coverage/default/11.sram_ctrl_regwen.201489746 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1109812032 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2882428051 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3334884900 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1927483587 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.4093670042 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.1285565383 |
| /workspace/coverage/default/12.sram_ctrl_bijection.4221597889 |
| /workspace/coverage/default/12.sram_ctrl_executable.2065392473 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.4251328641 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.785969523 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2766426080 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.2792389139 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.150617203 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.1941176694 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.3644473142 |
| /workspace/coverage/default/12.sram_ctrl_regwen.3506826844 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1657401621 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.3186677004 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3781053126 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.6448559 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.27868985 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.1055987870 |
| /workspace/coverage/default/13.sram_ctrl_bijection.101339799 |
| /workspace/coverage/default/13.sram_ctrl_executable.239106340 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.262851913 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1412786595 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3059967813 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.309923031 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.388822830 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.400712935 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2186840087 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.3890893011 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2155736098 |
| /workspace/coverage/default/13.sram_ctrl_smoke.3276565810 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.14545222 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2964462634 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1542181569 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.343664281 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.3723651493 |
| /workspace/coverage/default/14.sram_ctrl_bijection.1144788154 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.4256784096 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2668498784 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.356848188 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1893036147 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.960699041 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.2563848203 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1061938924 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.3408816976 |
| /workspace/coverage/default/14.sram_ctrl_regwen.554996867 |
| /workspace/coverage/default/14.sram_ctrl_smoke.1964161363 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.3599064686 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3192505164 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2372673176 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2307250342 |
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| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1493554279 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.3532573331 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.1483724516 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.3678371246 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1490521865 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.968906152 |
| /workspace/coverage/default/43.sram_ctrl_regwen.269637190 |
| /workspace/coverage/default/43.sram_ctrl_smoke.3754717745 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1013217662 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3210621322 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1719488373 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.620494649 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.4121110695 |
| /workspace/coverage/default/44.sram_ctrl_bijection.2698956981 |
| /workspace/coverage/default/44.sram_ctrl_executable.1690707925 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.1390430333 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.1882693625 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1893786222 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.1616782611 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1112444043 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2112410479 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.494253596 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.2182300500 |
| /workspace/coverage/default/44.sram_ctrl_regwen.3853882421 |
| /workspace/coverage/default/44.sram_ctrl_smoke.2044960012 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.316427930 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3977285101 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.492391233 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.748923093 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2634376530 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.3207080390 |
| /workspace/coverage/default/45.sram_ctrl_bijection.2037320590 |
| /workspace/coverage/default/45.sram_ctrl_executable.1697112273 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.2798674046 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.935776162 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1212808455 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.2292859933 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.15090097 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.4254734638 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.554131091 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.3491340829 |
| /workspace/coverage/default/45.sram_ctrl_regwen.867087252 |
| /workspace/coverage/default/45.sram_ctrl_smoke.2097173151 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.869789107 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.719494162 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3803596404 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1812436 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.4187474145 |
| /workspace/coverage/default/46.sram_ctrl_bijection.4104056602 |
| /workspace/coverage/default/46.sram_ctrl_executable.1489632003 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.4169457667 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1766455549 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.310982447 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.4168993663 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.2631087790 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.235815995 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.3986073342 |
| /workspace/coverage/default/46.sram_ctrl_regwen.3922521215 |
| /workspace/coverage/default/46.sram_ctrl_smoke.374719085 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.934225033 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2360257777 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1842428528 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1628598102 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2921736565 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.27414541 |
| /workspace/coverage/default/47.sram_ctrl_bijection.441566540 |
| /workspace/coverage/default/47.sram_ctrl_executable.3498850328 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.39253299 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.2049613924 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.779173100 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2140319998 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.963005348 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.3312770004 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.801753704 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.995674478 |
| /workspace/coverage/default/47.sram_ctrl_regwen.2128482536 |
| /workspace/coverage/default/47.sram_ctrl_smoke.1832445709 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.1860782822 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3245863750 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3394476079 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2442194420 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2349542530 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.2584091319 |
| /workspace/coverage/default/48.sram_ctrl_bijection.430529089 |
| /workspace/coverage/default/48.sram_ctrl_executable.3392185346 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.913034521 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.565441873 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2820226216 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.3914185089 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.1133836792 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.3740463498 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.749925960 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3712467366 |
| /workspace/coverage/default/48.sram_ctrl_regwen.204157959 |
| /workspace/coverage/default/48.sram_ctrl_smoke.3734550094 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.2300650876 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3102889125 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1970870344 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2480087827 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2288618027 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.90513739 |
| /workspace/coverage/default/49.sram_ctrl_bijection.4242247480 |
| /workspace/coverage/default/49.sram_ctrl_executable.871653826 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3341128884 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.812085692 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2997281907 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.1132645929 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.129479921 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.4203707750 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.844674722 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1603369808 |
| /workspace/coverage/default/49.sram_ctrl_regwen.206214525 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1782123602 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1374553145 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1771478855 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1942669157 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.2724917053 |
| /workspace/coverage/default/5.sram_ctrl_bijection.2272501187 |
| /workspace/coverage/default/5.sram_ctrl_executable.243578421 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2156832202 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.911470074 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.3987148509 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.244458071 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.881791671 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2581817182 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.879480297 |
| /workspace/coverage/default/5.sram_ctrl_regwen.743587172 |
| /workspace/coverage/default/5.sram_ctrl_smoke.1122175930 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3340010762 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1637068445 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2277276245 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.549912202 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3410166804 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1693393235 |
| /workspace/coverage/default/6.sram_ctrl_executable.3873230590 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.359396062 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.4187190083 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2686469619 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.966078395 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.1533458255 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2897476446 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1970766478 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.2290533707 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3849845509 |
| /workspace/coverage/default/6.sram_ctrl_smoke.743392351 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.560533639 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.289719439 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3080248260 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1133647255 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3909503916 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2697864095 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2221827935 |
| /workspace/coverage/default/7.sram_ctrl_executable.1099137165 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.760738983 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1063473263 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.2868821940 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1913182090 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.2916463115 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2296624063 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.1537944660 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3193456592 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3187892839 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.3414049037 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3636372222 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.374719731 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1916615444 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.535882407 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3403589303 |
| /workspace/coverage/default/8.sram_ctrl_bijection.1832999679 |
| /workspace/coverage/default/8.sram_ctrl_executable.3595707979 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.615436154 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.3702153233 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3437004693 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1273841552 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.1416201875 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3514358988 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.777777843 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.1428815174 |
| /workspace/coverage/default/8.sram_ctrl_regwen.3913348994 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2329543637 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.1864679157 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1288010997 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.111989999 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.853175954 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2053560415 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.3649432578 |
| /workspace/coverage/default/9.sram_ctrl_bijection.2061681216 |
| /workspace/coverage/default/9.sram_ctrl_executable.3243638414 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.2133997505 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.2377693945 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1331471827 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3028410701 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.1256191175 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.4149532695 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1269250295 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1594660071 |
| /workspace/coverage/default/9.sram_ctrl_regwen.3426335497 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1051816259 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.661209792 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1802359397 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.4075394972 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3738728287 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3618221034 |
|
|
Mar 07 01:13:41 PM PST 24 |
Mar 07 01:32:46 PM PST 24 |
56448949528 ps |
| T2 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.702709526 |
|
|
Mar 07 01:16:21 PM PST 24 |
Mar 07 01:16:48 PM PST 24 |
3598259034 ps |
| T3 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.960699041 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:24:48 PM PST 24 |
53832524533 ps |
| T7 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2156832202 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 01:12:33 PM PST 24 |
767485919 ps |
| T8 |
/workspace/coverage/default/11.sram_ctrl_stress_all.2837312050 |
|
|
Mar 07 01:12:14 PM PST 24 |
Mar 07 03:19:00 PM PST 24 |
306025281856 ps |
| T9 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.920401271 |
|
|
Mar 07 01:13:22 PM PST 24 |
Mar 07 01:14:43 PM PST 24 |
9823033608 ps |
| T10 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2820226216 |
|
|
Mar 07 01:16:21 PM PST 24 |
Mar 07 01:18:43 PM PST 24 |
8756327336 ps |
| T11 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.6448559 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:13:40 PM PST 24 |
3058639701 ps |
| T12 |
/workspace/coverage/default/28.sram_ctrl_smoke.73900929 |
|
|
Mar 07 01:13:23 PM PST 24 |
Mar 07 01:13:40 PM PST 24 |
1373037643 ps |
| T13 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.374719731 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:15:49 PM PST 24 |
18829864317 ps |
| T14 |
/workspace/coverage/default/34.sram_ctrl_executable.2292932889 |
|
|
Mar 07 01:14:08 PM PST 24 |
Mar 07 01:33:13 PM PST 24 |
110640457650 ps |
| T15 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.4281821726 |
|
|
Mar 07 01:12:30 PM PST 24 |
Mar 07 01:33:23 PM PST 24 |
17054937537 ps |
| T52 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2916463115 |
|
|
Mar 07 01:11:53 PM PST 24 |
Mar 07 01:13:23 PM PST 24 |
858519152 ps |
| T4 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3547703523 |
|
|
Mar 07 01:12:40 PM PST 24 |
Mar 07 02:22:56 PM PST 24 |
337505948118 ps |
| T57 |
/workspace/coverage/default/6.sram_ctrl_smoke.743392351 |
|
|
Mar 07 01:11:45 PM PST 24 |
Mar 07 01:12:02 PM PST 24 |
4954642854 ps |
| T58 |
/workspace/coverage/default/8.sram_ctrl_executable.3595707979 |
|
|
Mar 07 01:12:03 PM PST 24 |
Mar 07 01:27:21 PM PST 24 |
13968817621 ps |
| T59 |
/workspace/coverage/default/14.sram_ctrl_executable.569229170 |
|
|
Mar 07 01:12:12 PM PST 24 |
Mar 07 01:29:26 PM PST 24 |
14495449914 ps |
| T17 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1504998968 |
|
|
Mar 07 01:13:38 PM PST 24 |
Mar 07 01:13:38 PM PST 24 |
14620479 ps |
| T30 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1565105132 |
|
|
Mar 07 01:14:22 PM PST 24 |
Mar 07 01:14:25 PM PST 24 |
627832422 ps |
| T44 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.4210178241 |
|
|
Mar 07 01:15:06 PM PST 24 |
Mar 07 01:20:03 PM PST 24 |
12215992227 ps |
| T24 |
/workspace/coverage/default/29.sram_ctrl_bijection.2346545715 |
|
|
Mar 07 01:13:37 PM PST 24 |
Mar 07 01:46:48 PM PST 24 |
91114081990 ps |
| T28 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2645931869 |
|
|
Mar 07 01:13:38 PM PST 24 |
Mar 07 01:13:49 PM PST 24 |
783548360 ps |
| T16 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.3357387246 |
|
|
Mar 07 01:12:46 PM PST 24 |
Mar 07 01:36:59 PM PST 24 |
110356033273 ps |
| T107 |
/workspace/coverage/default/30.sram_ctrl_executable.4261882520 |
|
|
Mar 07 01:13:38 PM PST 24 |
Mar 07 01:33:36 PM PST 24 |
43680408579 ps |
| T92 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.749925960 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:20:45 PM PST 24 |
4801305840 ps |
| T93 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3210621322 |
|
|
Mar 07 01:15:16 PM PST 24 |
Mar 07 01:17:32 PM PST 24 |
2935161950 ps |
| T20 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1714757282 |
|
|
Mar 07 01:15:17 PM PST 24 |
Mar 07 01:15:18 PM PST 24 |
23614549 ps |
| T5 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.659524592 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:24:49 PM PST 24 |
48509002915 ps |
| T25 |
/workspace/coverage/default/14.sram_ctrl_regwen.554996867 |
|
|
Mar 07 01:12:15 PM PST 24 |
Mar 07 01:21:24 PM PST 24 |
34903985334 ps |
| T6 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1222004630 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 02:45:32 PM PST 24 |
42624143076 ps |
| T108 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.2292859933 |
|
|
Mar 07 01:15:50 PM PST 24 |
Mar 07 01:20:47 PM PST 24 |
14343361925 ps |
| T74 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1047339071 |
|
|
Mar 07 01:14:33 PM PST 24 |
Mar 07 01:16:41 PM PST 24 |
1638190735 ps |
| T27 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.1797982678 |
|
|
Mar 07 01:15:02 PM PST 24 |
Mar 07 01:19:36 PM PST 24 |
16811273046 ps |
| T75 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3944611903 |
|
|
Mar 07 01:15:30 PM PST 24 |
Mar 07 01:48:21 PM PST 24 |
16514421675 ps |
| T137 |
/workspace/coverage/default/9.sram_ctrl_smoke.1051816259 |
|
|
Mar 07 01:12:01 PM PST 24 |
Mar 07 01:12:24 PM PST 24 |
5597319716 ps |
| T94 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.183626841 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:20:46 PM PST 24 |
84821484939 ps |
| T135 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3308016625 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:40:10 PM PST 24 |
65974022875 ps |
| T138 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3028410701 |
|
|
Mar 07 01:11:58 PM PST 24 |
Mar 07 01:14:00 PM PST 24 |
2058598544 ps |
| T18 |
/workspace/coverage/default/3.sram_ctrl_alert_test.4159749329 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:11:42 PM PST 24 |
101028696 ps |
| T131 |
/workspace/coverage/default/16.sram_ctrl_bijection.2298265045 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:29:02 PM PST 24 |
230749151785 ps |
| T139 |
/workspace/coverage/default/8.sram_ctrl_bijection.1832999679 |
|
|
Mar 07 01:12:03 PM PST 24 |
Mar 07 01:22:11 PM PST 24 |
29067568184 ps |
| T133 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2126918660 |
|
|
Mar 07 01:15:07 PM PST 24 |
Mar 07 01:27:51 PM PST 24 |
20142775541 ps |
| T140 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.813398596 |
|
|
Mar 07 01:13:45 PM PST 24 |
Mar 07 01:16:26 PM PST 24 |
43040180542 ps |
| T31 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3491340829 |
|
|
Mar 07 01:15:39 PM PST 24 |
Mar 07 01:15:43 PM PST 24 |
705084713 ps |
| T76 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2634376530 |
|
|
Mar 07 01:15:40 PM PST 24 |
Mar 07 01:21:14 PM PST 24 |
7703718237 ps |
| T134 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.4023241133 |
|
|
Mar 07 01:12:42 PM PST 24 |
Mar 07 01:13:50 PM PST 24 |
2930604417 ps |
| T29 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2157303592 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 01:12:17 PM PST 24 |
206821819 ps |
| T141 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3514358988 |
|
|
Mar 07 01:12:07 PM PST 24 |
Mar 07 01:13:59 PM PST 24 |
1205063523 ps |
| T53 |
/workspace/coverage/default/41.sram_ctrl_regwen.1168957306 |
|
|
Mar 07 01:15:07 PM PST 24 |
Mar 07 01:26:56 PM PST 24 |
54405792445 ps |
| T77 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.620494649 |
|
|
Mar 07 01:15:30 PM PST 24 |
Mar 07 01:30:52 PM PST 24 |
37563819159 ps |
| T142 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.4011173370 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:17:55 PM PST 24 |
258226864644 ps |
| T143 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1483724516 |
|
|
Mar 07 01:15:20 PM PST 24 |
Mar 07 01:20:19 PM PST 24 |
3734589087 ps |
| T19 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2525682270 |
|
|
Mar 07 01:14:21 PM PST 24 |
Mar 07 01:14:22 PM PST 24 |
14732304 ps |
| T78 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3521359246 |
|
|
Mar 07 01:12:29 PM PST 24 |
Mar 07 01:20:35 PM PST 24 |
133748923207 ps |
| T88 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1385816067 |
|
|
Mar 07 01:15:16 PM PST 24 |
Mar 07 01:17:27 PM PST 24 |
1681940558 ps |
| T144 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3898696010 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 01:16:28 PM PST 24 |
2017715776 ps |
| T145 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1428969353 |
|
|
Mar 07 01:14:56 PM PST 24 |
Mar 07 01:17:31 PM PST 24 |
20728899132 ps |
| T26 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2556247639 |
|
|
Mar 07 01:13:58 PM PST 24 |
Mar 07 02:17:41 PM PST 24 |
53066011100 ps |
| T146 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3704664998 |
|
|
Mar 07 01:14:45 PM PST 24 |
Mar 07 01:15:25 PM PST 24 |
956754717 ps |
| T54 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.4251328641 |
|
|
Mar 07 01:12:14 PM PST 24 |
Mar 07 01:29:43 PM PST 24 |
107038480790 ps |
| T95 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2851226213 |
|
|
Mar 07 01:12:50 PM PST 24 |
Mar 07 01:18:20 PM PST 24 |
13953030126 ps |
| T55 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3254613604 |
|
|
Mar 07 01:11:49 PM PST 24 |
Mar 07 01:16:21 PM PST 24 |
16102881848 ps |
| T147 |
/workspace/coverage/default/27.sram_ctrl_partial_access.57618776 |
|
|
Mar 07 01:13:29 PM PST 24 |
Mar 07 01:13:38 PM PST 24 |
3046997299 ps |
| T148 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.766674278 |
|
|
Mar 07 01:12:44 PM PST 24 |
Mar 07 01:17:05 PM PST 24 |
15758151041 ps |
| T96 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2686469619 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:12:59 PM PST 24 |
1989949301 ps |
| T32 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.4081402400 |
|
|
Mar 07 01:14:16 PM PST 24 |
Mar 07 01:14:19 PM PST 24 |
682149958 ps |
| T149 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1941176694 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:12:18 PM PST 24 |
2826162444 ps |
| T150 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1542181569 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:12:45 PM PST 24 |
728025049 ps |
| T56 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1860782822 |
|
|
Mar 07 01:16:13 PM PST 24 |
Mar 07 02:51:23 PM PST 24 |
235538747980 ps |
| T109 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3136047624 |
|
|
Mar 07 01:12:53 PM PST 24 |
Mar 07 01:21:05 PM PST 24 |
46796640910 ps |
| T112 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1751753840 |
|
|
Mar 07 01:12:28 PM PST 24 |
Mar 07 02:40:56 PM PST 24 |
352142830664 ps |
| T151 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2441324012 |
|
|
Mar 07 01:15:05 PM PST 24 |
Mar 07 01:19:56 PM PST 24 |
13924526277 ps |
| T123 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1547458540 |
|
|
Mar 07 01:11:29 PM PST 24 |
Mar 07 01:12:46 PM PST 24 |
5782153699 ps |
| T152 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.4195041626 |
|
|
Mar 07 01:14:05 PM PST 24 |
Mar 07 01:16:12 PM PST 24 |
8218244650 ps |
| T122 |
/workspace/coverage/default/33.sram_ctrl_executable.5505912 |
|
|
Mar 07 01:14:10 PM PST 24 |
Mar 07 01:30:11 PM PST 24 |
38000014058 ps |
| T130 |
/workspace/coverage/default/9.sram_ctrl_stress_all.661209792 |
|
|
Mar 07 01:12:10 PM PST 24 |
Mar 07 02:35:52 PM PST 24 |
146750994525 ps |
| T153 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2766426080 |
|
|
Mar 07 01:12:08 PM PST 24 |
Mar 07 01:13:17 PM PST 24 |
2790911020 ps |
| T154 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3080349355 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:27:44 PM PST 24 |
15079772999 ps |
| T132 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2598704893 |
|
|
Mar 07 01:11:38 PM PST 24 |
Mar 07 02:20:52 PM PST 24 |
124637441383 ps |
| T45 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1147487148 |
|
|
Mar 07 01:14:43 PM PST 24 |
Mar 07 01:15:33 PM PST 24 |
1781600141 ps |
| T155 |
/workspace/coverage/default/27.sram_ctrl_regwen.169897597 |
|
|
Mar 07 01:13:25 PM PST 24 |
Mar 07 01:25:53 PM PST 24 |
8551343424 ps |
| T156 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3944787158 |
|
|
Mar 07 01:12:26 PM PST 24 |
Mar 07 01:12:42 PM PST 24 |
5320990701 ps |
| T124 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.136640169 |
|
|
Mar 07 01:12:28 PM PST 24 |
Mar 07 01:13:47 PM PST 24 |
21975874554 ps |
| T157 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4131875795 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 01:20:47 PM PST 24 |
37489361847 ps |
| T158 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2921736565 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:54:45 PM PST 24 |
17503942412 ps |
| T159 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.427606504 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:12:43 PM PST 24 |
7528293913 ps |
| T160 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.532239284 |
|
|
Mar 07 01:12:23 PM PST 24 |
Mar 07 01:17:11 PM PST 24 |
25689457179 ps |
| T161 |
/workspace/coverage/default/20.sram_ctrl_regwen.4139113736 |
|
|
Mar 07 01:12:37 PM PST 24 |
Mar 07 01:14:17 PM PST 24 |
4880906316 ps |
| T162 |
/workspace/coverage/default/33.sram_ctrl_stress_all.3842935759 |
|
|
Mar 07 01:14:07 PM PST 24 |
Mar 07 02:35:21 PM PST 24 |
34228148222 ps |
| T163 |
/workspace/coverage/default/15.sram_ctrl_executable.343367937 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:23:14 PM PST 24 |
30878773885 ps |
| T164 |
/workspace/coverage/default/32.sram_ctrl_executable.731871687 |
|
|
Mar 07 01:13:55 PM PST 24 |
Mar 07 01:18:27 PM PST 24 |
16076856646 ps |
| T110 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2086358480 |
|
|
Mar 07 01:14:55 PM PST 24 |
Mar 07 02:48:55 PM PST 24 |
1563808259571 ps |
| T165 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1787863209 |
|
|
Mar 07 01:11:46 PM PST 24 |
Mar 07 01:11:59 PM PST 24 |
738406068 ps |
| T166 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3740463498 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:18:28 PM PST 24 |
2564887077 ps |
| T167 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1374553145 |
|
|
Mar 07 01:16:23 PM PST 24 |
Mar 07 01:20:08 PM PST 24 |
15341032774 ps |
| T136 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1917620839 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:45:28 PM PST 24 |
70564825482 ps |
| T168 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3293725168 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:13:16 PM PST 24 |
1437577109 ps |
| T111 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1506628308 |
|
|
Mar 07 01:13:56 PM PST 24 |
Mar 07 04:11:39 PM PST 24 |
1015900792738 ps |
| T169 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.469230174 |
|
|
Mar 07 01:14:21 PM PST 24 |
Mar 07 01:14:57 PM PST 24 |
767647306 ps |
| T170 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.638094674 |
|
|
Mar 07 01:14:43 PM PST 24 |
Mar 07 01:20:56 PM PST 24 |
20038084891 ps |
| T46 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.14545222 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:13:29 PM PST 24 |
853013920 ps |
| T47 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1842851083 |
|
|
Mar 07 01:12:41 PM PST 24 |
Mar 07 01:13:13 PM PST 24 |
1208141527 ps |
| T171 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.938937021 |
|
|
Mar 07 01:11:37 PM PST 24 |
Mar 07 01:11:40 PM PST 24 |
351210071 ps |
| T172 |
/workspace/coverage/default/49.sram_ctrl_alert_test.90513739 |
|
|
Mar 07 01:16:36 PM PST 24 |
Mar 07 01:16:37 PM PST 24 |
42915990 ps |
| T173 |
/workspace/coverage/default/34.sram_ctrl_partial_access.685764335 |
|
|
Mar 07 01:14:09 PM PST 24 |
Mar 07 01:14:29 PM PST 24 |
2683731877 ps |
| T174 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.760738983 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:13:44 PM PST 24 |
808557760 ps |
| T175 |
/workspace/coverage/default/23.sram_ctrl_executable.2859202657 |
|
|
Mar 07 01:12:51 PM PST 24 |
Mar 07 01:33:07 PM PST 24 |
217112719027 ps |
| T176 |
/workspace/coverage/default/48.sram_ctrl_regwen.204157959 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:30:37 PM PST 24 |
21796337594 ps |
| T177 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1112444043 |
|
|
Mar 07 01:15:30 PM PST 24 |
Mar 07 01:21:25 PM PST 24 |
1870426816 ps |
| T178 |
/workspace/coverage/default/38.sram_ctrl_bijection.3728598793 |
|
|
Mar 07 01:14:32 PM PST 24 |
Mar 07 01:47:05 PM PST 24 |
326505820510 ps |
| T179 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1337169751 |
|
|
Mar 07 01:11:36 PM PST 24 |
Mar 07 01:15:43 PM PST 24 |
4067217945 ps |
| T180 |
/workspace/coverage/default/24.sram_ctrl_smoke.1110141467 |
|
|
Mar 07 01:12:52 PM PST 24 |
Mar 07 01:12:57 PM PST 24 |
437586302 ps |
| T181 |
/workspace/coverage/default/20.sram_ctrl_bijection.1074428244 |
|
|
Mar 07 01:12:39 PM PST 24 |
Mar 07 01:48:57 PM PST 24 |
643992629541 ps |
| T182 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1798841042 |
|
|
Mar 07 01:14:44 PM PST 24 |
Mar 07 01:14:48 PM PST 24 |
1346567550 ps |
| T183 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2791178876 |
|
|
Mar 07 01:13:07 PM PST 24 |
Mar 07 01:13:08 PM PST 24 |
14806249 ps |
| T184 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3595195078 |
|
|
Mar 07 01:11:29 PM PST 24 |
Mar 07 01:13:59 PM PST 24 |
8970334168 ps |
| T185 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3207080390 |
|
|
Mar 07 01:15:51 PM PST 24 |
Mar 07 01:15:52 PM PST 24 |
54651311 ps |
| T186 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.233523548 |
|
|
Mar 07 01:12:52 PM PST 24 |
Mar 07 01:34:06 PM PST 24 |
51176722566 ps |
| T187 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3840258126 |
|
|
Mar 07 01:12:30 PM PST 24 |
Mar 07 01:12:34 PM PST 24 |
713314283 ps |
| T125 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1474565208 |
|
|
Mar 07 01:12:30 PM PST 24 |
Mar 07 01:16:36 PM PST 24 |
24164111874 ps |
| T188 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.129479921 |
|
|
Mar 07 01:16:22 PM PST 24 |
Mar 07 01:31:47 PM PST 24 |
35338476657 ps |
| T189 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.878704050 |
|
|
Mar 07 01:14:55 PM PST 24 |
Mar 07 01:16:37 PM PST 24 |
772066915 ps |
| T190 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3234469036 |
|
|
Mar 07 01:12:47 PM PST 24 |
Mar 07 01:16:09 PM PST 24 |
3240817739 ps |
| T191 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.291162448 |
|
|
Mar 07 01:11:27 PM PST 24 |
Mar 07 01:21:05 PM PST 24 |
30311710069 ps |
| T192 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.3810942813 |
|
|
Mar 07 01:13:42 PM PST 24 |
Mar 07 01:18:37 PM PST 24 |
18251942168 ps |
| T193 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.548142440 |
|
|
Mar 07 01:12:49 PM PST 24 |
Mar 07 01:16:51 PM PST 24 |
7248545573 ps |
| T194 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.985944942 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:33:17 PM PST 24 |
14170985562 ps |
| T195 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2115061523 |
|
|
Mar 07 01:14:44 PM PST 24 |
Mar 07 01:16:40 PM PST 24 |
1454962730 ps |
| T196 |
/workspace/coverage/default/46.sram_ctrl_partial_access.2631087790 |
|
|
Mar 07 01:15:49 PM PST 24 |
Mar 07 01:15:54 PM PST 24 |
921835319 ps |
| T197 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3619551235 |
|
|
Mar 07 01:12:43 PM PST 24 |
Mar 07 01:17:28 PM PST 24 |
12671791892 ps |
| T198 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.4150741294 |
|
|
Mar 07 01:14:57 PM PST 24 |
Mar 07 01:40:29 PM PST 24 |
16423370791 ps |
| T199 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1769348793 |
|
|
Mar 07 01:12:27 PM PST 24 |
Mar 07 01:12:42 PM PST 24 |
709478930 ps |
| T126 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.278953510 |
|
|
Mar 07 01:12:41 PM PST 24 |
Mar 07 01:13:59 PM PST 24 |
2737684751 ps |
| T200 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.2327212671 |
|
|
Mar 07 01:14:22 PM PST 24 |
Mar 07 01:16:57 PM PST 24 |
8952585232 ps |
| T201 |
/workspace/coverage/default/39.sram_ctrl_executable.2456441128 |
|
|
Mar 07 01:14:43 PM PST 24 |
Mar 07 01:27:41 PM PST 24 |
47179418718 ps |
| T202 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1864679157 |
|
|
Mar 07 01:12:07 PM PST 24 |
Mar 07 02:43:19 PM PST 24 |
99421064637 ps |
| T203 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3229029764 |
|
|
Mar 07 01:11:41 PM PST 24 |
Mar 07 01:16:26 PM PST 24 |
44336999112 ps |
| T48 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1054929393 |
|
|
Mar 07 01:11:29 PM PST 24 |
Mar 07 01:12:07 PM PST 24 |
1362500718 ps |
| T204 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.124714740 |
|
|
Mar 07 01:11:46 PM PST 24 |
Mar 07 01:14:15 PM PST 24 |
14062704783 ps |
| T205 |
/workspace/coverage/default/26.sram_ctrl_stress_all.1760285381 |
|
|
Mar 07 01:13:22 PM PST 24 |
Mar 07 01:56:50 PM PST 24 |
243761847321 ps |
| T206 |
/workspace/coverage/default/22.sram_ctrl_regwen.388364790 |
|
|
Mar 07 01:12:38 PM PST 24 |
Mar 07 01:37:09 PM PST 24 |
80729533429 ps |
| T207 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1590813657 |
|
|
Mar 07 01:12:22 PM PST 24 |
Mar 07 01:18:12 PM PST 24 |
8986346069 ps |
| T208 |
/workspace/coverage/default/42.sram_ctrl_regwen.2242501070 |
|
|
Mar 07 01:15:16 PM PST 24 |
Mar 07 01:21:06 PM PST 24 |
22013127522 ps |
| T209 |
/workspace/coverage/default/33.sram_ctrl_regwen.3564356869 |
|
|
Mar 07 01:14:06 PM PST 24 |
Mar 07 01:17:43 PM PST 24 |
7329597675 ps |
| T210 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2187747776 |
|
|
Mar 07 01:13:07 PM PST 24 |
Mar 07 01:39:12 PM PST 24 |
30861790865 ps |
| T211 |
/workspace/coverage/default/3.sram_ctrl_regwen.4109091535 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:31:39 PM PST 24 |
3541592160 ps |
| T49 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2175881496 |
|
|
Mar 07 01:11:49 PM PST 24 |
Mar 07 01:11:58 PM PST 24 |
786431453 ps |
| T212 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1490521865 |
|
|
Mar 07 01:15:16 PM PST 24 |
Mar 07 01:21:18 PM PST 24 |
31693991238 ps |
| T213 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2604553429 |
|
|
Mar 07 01:15:05 PM PST 24 |
Mar 07 01:16:27 PM PST 24 |
3218726403 ps |
| T127 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3169124807 |
|
|
Mar 07 01:13:38 PM PST 24 |
Mar 07 01:31:45 PM PST 24 |
18875184018 ps |
| T214 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.234210132 |
|
|
Mar 07 01:13:06 PM PST 24 |
Mar 07 01:22:44 PM PST 24 |
20721728776 ps |
| T215 |
/workspace/coverage/default/22.sram_ctrl_stress_all.283104263 |
|
|
Mar 07 01:12:46 PM PST 24 |
Mar 07 01:33:03 PM PST 24 |
43949849763 ps |
| T216 |
/workspace/coverage/default/47.sram_ctrl_executable.3498850328 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:27:17 PM PST 24 |
106799852436 ps |
| T217 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3154054391 |
|
|
Mar 07 01:11:28 PM PST 24 |
Mar 07 01:27:04 PM PST 24 |
9688306043 ps |
| T218 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3675625727 |
|
|
Mar 07 01:11:28 PM PST 24 |
Mar 07 01:17:03 PM PST 24 |
8930853146 ps |
| T219 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1052744580 |
|
|
Mar 07 01:14:41 PM PST 24 |
Mar 07 01:14:42 PM PST 24 |
30838072 ps |
| T220 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2053560415 |
|
|
Mar 07 01:12:07 PM PST 24 |
Mar 07 01:19:24 PM PST 24 |
16689740490 ps |
| T221 |
/workspace/coverage/default/5.sram_ctrl_regwen.743587172 |
|
|
Mar 07 01:11:55 PM PST 24 |
Mar 07 01:18:19 PM PST 24 |
17355938224 ps |
| T222 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1416201875 |
|
|
Mar 07 01:11:51 PM PST 24 |
Mar 07 01:15:50 PM PST 24 |
19078529415 ps |
| T223 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2108183141 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:16:53 PM PST 24 |
12474038915 ps |
| T224 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.262851913 |
|
|
Mar 07 01:12:12 PM PST 24 |
Mar 07 01:15:23 PM PST 24 |
21804567969 ps |
| T225 |
/workspace/coverage/default/30.sram_ctrl_smoke.3120032217 |
|
|
Mar 07 01:13:41 PM PST 24 |
Mar 07 01:13:52 PM PST 24 |
5851084558 ps |
| T226 |
/workspace/coverage/default/38.sram_ctrl_partial_access.4211466064 |
|
|
Mar 07 01:14:34 PM PST 24 |
Mar 07 01:14:51 PM PST 24 |
4316551574 ps |
| T227 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3213951417 |
|
|
Mar 07 01:12:36 PM PST 24 |
Mar 07 01:12:40 PM PST 24 |
704605088 ps |
| T50 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1534611626 |
|
|
Mar 07 01:11:46 PM PST 24 |
Mar 07 01:12:04 PM PST 24 |
1628786890 ps |
| T228 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3259084808 |
|
|
Mar 07 01:13:43 PM PST 24 |
Mar 07 01:13:46 PM PST 24 |
1257180647 ps |
| T229 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3312770004 |
|
|
Mar 07 01:16:07 PM PST 24 |
Mar 07 01:16:46 PM PST 24 |
440345772 ps |
| T230 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3154190196 |
|
|
Mar 07 01:13:57 PM PST 24 |
Mar 07 01:27:46 PM PST 24 |
8527481510 ps |
| T231 |
/workspace/coverage/default/17.sram_ctrl_bijection.2073573400 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:21:38 PM PST 24 |
8286578416 ps |
| T232 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2169780493 |
|
|
Mar 07 01:12:47 PM PST 24 |
Mar 07 01:12:48 PM PST 24 |
29942573 ps |
| T233 |
/workspace/coverage/default/8.sram_ctrl_regwen.3913348994 |
|
|
Mar 07 01:12:03 PM PST 24 |
Mar 07 01:40:44 PM PST 24 |
14371131067 ps |
| T234 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.133317009 |
|
|
Mar 07 01:13:44 PM PST 24 |
Mar 07 01:15:34 PM PST 24 |
6719851727 ps |
| T235 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2906378732 |
|
|
Mar 07 01:13:54 PM PST 24 |
Mar 07 01:13:55 PM PST 24 |
42118541 ps |
| T236 |
/workspace/coverage/default/34.sram_ctrl_smoke.4267088494 |
|
|
Mar 07 01:14:08 PM PST 24 |
Mar 07 01:16:07 PM PST 24 |
462934832 ps |
| T237 |
/workspace/coverage/default/29.sram_ctrl_executable.4135128279 |
|
|
Mar 07 01:13:44 PM PST 24 |
Mar 07 01:23:27 PM PST 24 |
10251023502 ps |
| T238 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2044746436 |
|
|
Mar 07 01:11:47 PM PST 24 |
Mar 07 01:12:16 PM PST 24 |
2984411853 ps |
| T239 |
/workspace/coverage/default/36.sram_ctrl_smoke.2832222327 |
|
|
Mar 07 01:14:21 PM PST 24 |
Mar 07 01:15:29 PM PST 24 |
863888756 ps |
| T240 |
/workspace/coverage/default/4.sram_ctrl_alert_test.2567327577 |
|
|
Mar 07 01:11:46 PM PST 24 |
Mar 07 01:11:47 PM PST 24 |
17685446 ps |
| T241 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.4046546761 |
|
|
Mar 07 01:14:08 PM PST 24 |
Mar 07 01:26:48 PM PST 24 |
40865952686 ps |
| T242 |
/workspace/coverage/default/6.sram_ctrl_stress_all.560533639 |
|
|
Mar 07 01:12:03 PM PST 24 |
Mar 07 02:34:45 PM PST 24 |
584126952808 ps |
| T243 |
/workspace/coverage/default/3.sram_ctrl_executable.1409582062 |
|
|
Mar 07 01:11:39 PM PST 24 |
Mar 07 01:16:58 PM PST 24 |
4292800468 ps |
| T51 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2360257777 |
|
|
Mar 07 01:16:01 PM PST 24 |
Mar 07 01:17:12 PM PST 24 |
8547104759 ps |
| T244 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2520147678 |
|
|
Mar 07 01:11:33 PM PST 24 |
Mar 07 01:12:12 PM PST 24 |
728103677 ps |
| T245 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.2223687656 |
|
|
Mar 07 01:12:26 PM PST 24 |
Mar 07 01:13:15 PM PST 24 |
9082390636 ps |
| T246 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2612664591 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:13:36 PM PST 24 |
13741362761 ps |
| T247 |
/workspace/coverage/default/0.sram_ctrl_bijection.1287984087 |
|
|
Mar 07 01:11:29 PM PST 24 |
Mar 07 01:43:13 PM PST 24 |
28881298412 ps |
| T248 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.4227993092 |
|
|
Mar 07 01:14:32 PM PST 24 |
Mar 07 01:15:20 PM PST 24 |
732155138 ps |
| T249 |
/workspace/coverage/default/46.sram_ctrl_executable.1489632003 |
|
|
Mar 07 01:15:58 PM PST 24 |
Mar 07 01:22:13 PM PST 24 |
25155472946 ps |
| T250 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.879361944 |
|
|
Mar 07 01:12:11 PM PST 24 |
Mar 07 01:14:55 PM PST 24 |
43161418917 ps |
| T251 |
/workspace/coverage/default/44.sram_ctrl_alert_test.4121110695 |
|
|
Mar 07 01:15:40 PM PST 24 |
Mar 07 01:15:41 PM PST 24 |
41816987 ps |
| T252 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2186840087 |
|
|
Mar 07 01:12:13 PM PST 24 |
Mar 07 01:15:21 PM PST 24 |
31540369961 ps |
| T253 |
/workspace/coverage/default/12.sram_ctrl_regwen.3506826844 |
|
|
Mar 07 01:12:09 PM PST 24 |
Mar 07 01:13:43 PM PST 24 |
2300779648 ps |
| T254 |
/workspace/coverage/default/20.sram_ctrl_executable.2356982112 |
|
|
Mar 07 01:12:39 PM PST 24 |
Mar 07 01:16:05 PM PST 24 |
21400997767 ps |
| T255 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.3987148509 |
|
|
Mar 07 01:12:03 PM PST 24 |
Mar 07 01:16:14 PM PST 24 |
3943871953 ps |
| T256 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.4114349672 |
|
|
Mar 07 01:14:36 PM PST 24 |
Mar 07 01:18:28 PM PST 24 |
7457206808 ps |
| T257 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3726663240 |
|
|
Mar 07 01:12:51 PM PST 24 |
Mar 07 01:13:29 PM PST 24 |
5486992536 ps |
| T258 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.343664281 |
|
|
Mar 07 01:12:14 PM PST 24 |
Mar 07 01:20:00 PM PST 24 |
23559223167 ps |
| T259 |
/workspace/coverage/default/32.sram_ctrl_bijection.3495338589 |
|
|
Mar 07 01:13:54 PM PST 24 |
Mar 07 01:46:34 PM PST 24 |
120869358447 ps |
| T260 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1842428528 |
|
|
Mar 07 01:15:50 PM PST 24 |
Mar 07 01:19:31 PM PST 24 |
4448513759 ps |
| T261 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1417436757 |
|
|
Mar 07 01:14:54 PM PST 24 |
Mar 07 01:26:42 PM PST 24 |
12976104958 ps |
| T262 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1164558261 |
|
|
Mar 07 01:12:25 PM PST 24 |
Mar 07 01:13:46 PM PST 24 |
4662275555 ps |
| T263 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3208640310 |
|
|
Mar 07 01:12:30 PM PST 24 |
Mar 07 01:12:31 PM PST 24 |
32675316 ps |
| T264 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.1757664284 |
|
|
Mar 07 01:11:28 PM PST 24 |
Mar 07 01:12:11 PM PST 24 |
2901708360 ps |
| T265 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1245000483 |
|
|
Mar 07 01:13:39 PM PST 24 |
Mar 07 01:16:04 PM PST 24 |
3109091502 ps |
| T266 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1556156742 |
|
|
Mar 07 01:13:06 PM PST 24 |
Mar 07 01:14:08 PM PST 24 |
5695515382 ps |
| T267 |
/workspace/coverage/default/4.sram_ctrl_smoke.1271766182 |
|
|
Mar 07 01:11:40 PM PST 24 |
Mar 07 01:11:48 PM PST 24 |
1579766917 ps |
| T268 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2245880867 |
|
|
Mar 07 01:14:10 PM PST 24 |
Mar 07 01:19:02 PM PST 24 |
21721166155 ps |
| T269 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.927330673 |
|
|
Mar 07 01:11:35 PM PST 24 |
Mar 07 01:11:39 PM PST 24 |
1402991916 ps |
| T270 |
/workspace/coverage/default/7.sram_ctrl_executable.1099137165 |
|
|
Mar 07 01:12:06 PM PST 24 |
Mar 07 01:21:37 PM PST 24 |
7573816442 ps |
| T271 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1390430333 |
|
|
Mar 07 01:15:31 PM PST 24 |
Mar 07 01:16:26 PM PST 24 |
3597170363 ps |
| T272 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2787035565 |
|
|
Mar 07 01:13:03 PM PST 24 |
Mar 07 01:18:03 PM PST 24 |
22102837554 ps |
| T273 |
/workspace/coverage/default/6.sram_ctrl_regwen.3849845509 |
|
|
Mar 07 01:11:54 PM PST 24 |
Mar 07 01:29:10 PM PST 24 |
25514522321 ps |
| T274 |
/workspace/coverage/default/39.sram_ctrl_regwen.2904768723 |
|
|
Mar 07 01:14:41 PM PST 24 |
Mar 07 01:32:36 PM PST 24 |
11356506366 ps |
| T275 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.822932113 |
|
|
Mar 07 01:12:39 PM PST 24 |
Mar 07 01:16:07 PM PST 24 |
5647392382 ps |
| T276 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1628598102 |
|
|
Mar 07 01:15:50 PM PST 24 |
Mar 07 01:18:30 PM PST 24 |
3254327381 ps |
| T277 |
/workspace/coverage/default/22.sram_ctrl_executable.3302597622 |
|
|
Mar 07 01:12:35 PM PST 24 |
Mar 07 01:13:28 PM PST 24 |
1581017282 ps |
| T278 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3803596404 |
|
|
Mar 07 01:15:41 PM PST 24 |
Mar 07 01:15:58 PM PST 24 |
806185168 ps |
| T279 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1299927851 |
|
|
Mar 07 01:12:26 PM PST 24 |
Mar 07 01:16:44 PM PST 24 |
3946526915 ps |
| T280 |
/workspace/coverage/default/47.sram_ctrl_bijection.441566540 |
|
|
Mar 07 01:16:01 PM PST 24 |
Mar 07 01:39:28 PM PST 24 |
230741182684 ps |
| T128 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2524734995 |
|
|
Mar 07 01:12:56 PM PST 24 |
Mar 07 01:21:50 PM PST 24 |
96427025625 ps |
| T281 |
/workspace/coverage/default/6.sram_ctrl_bijection.1693393235 |
|
|
Mar 07 01:11:47 PM PST 24 |
Mar 07 01:33:52 PM PST 24 |
19273342503 ps |
| T282 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.549912202 |
|
|
Mar 07 01:11:49 PM PST 24 |
Mar 07 01:22:55 PM PST 24 |
10530273342 ps |
| T283 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1565051865 |
|
|
Mar 07 01:13:44 PM PST 24 |
Mar 07 01:14:03 PM PST 24 |
5334483934 ps |
| T284 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2686751781 |
|
|
Mar 07 01:12:17 PM PST 24 |
Mar 07 01:13:59 PM PST 24 |
1536613037 ps |
| T285 |
/workspace/coverage/default/48.sram_ctrl_smoke.3734550094 |
|
|
Mar 07 01:16:11 PM PST 24 |
Mar 07 01:16:35 PM PST 24 |
3581276501 ps |
| T286 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.3368289237 |
|
|
Mar 07 01:12:54 PM PST 24 |
Mar 07 01:17:05 PM PST 24 |
8214485519 ps |
| T287 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2372673176 |
|
|
Mar 07 01:12:14 PM PST 24 |
Mar 07 01:16:01 PM PST 24 |
15386031350 ps |
| T129 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1970766478 |
|
|
Mar 07 01:11:56 PM PST 24 |
Mar 07 01:17:11 PM PST 24 |
14773244028 ps |
| T288 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.21709596 |
|
|
Mar 07 01:11:43 PM PST 24 |
Mar 07 01:12:58 PM PST 24 |
2441765298 ps |
| T289 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.4086341715 |
|
|
Mar 07 01:12:50 PM PST 24 |
Mar 07 01:12:53 PM PST 24 |
4176339900 ps |
| T290 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1603369808 |
|
|
Mar 07 01:16:22 PM PST 24 |
Mar 07 01:16:26 PM PST 24 |
347015691 ps |
| T291 |
/workspace/coverage/default/5.sram_ctrl_partial_access.881791671 |
|
|
Mar 07 01:11:49 PM PST 24 |
Mar 07 01:11:54 PM PST 24 |
1271699541 ps |
| T292 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1537944660 |
|
|
Mar 07 01:12:04 PM PST 24 |
Mar 07 01:12:08 PM PST 24 |
358988254 ps |
| T293 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1832661550 |
|
|
Mar 07 01:14:07 PM PST 24 |
Mar 07 01:14:10 PM PST 24 |
704467801 ps |
| T101 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.869789107 |
|
|
Mar 07 01:15:50 PM PST 24 |
Mar 07 01:16:35 PM PST 24 |
2133383643 ps |
| T294 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1061938924 |
|
|
Mar 07 01:12:15 PM PST 24 |
Mar 07 01:19:43 PM PST 24 |
65933456532 ps |
| T295 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.3178091154 |
|
|
Mar 07 01:12:52 PM PST 24 |
Mar 07 01:38:41 PM PST 24 |
31235815162 ps |
| T296 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3233594116 |
|
|
Mar 07 01:14:13 PM PST 24 |
Mar 07 01:14:14 PM PST 24 |
34525001 ps |
| T297 |
/workspace/coverage/default/28.sram_ctrl_bijection.3650096217 |
|
|
Mar 07 01:13:24 PM PST 24 |
Mar 07 01:45:02 PM PST 24 |
166375264290 ps |
| T298 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3995331670 |
|
|
Mar 07 01:14:22 PM PST 24 |
Mar 07 01:17:04 PM PST 24 |
20296774128 ps |
| T299 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2167394253 |
|
|
Mar 07 01:14:57 PM PST 24 |
Mar 07 01:16:49 PM PST 24 |
5143722726 ps |
| T300 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1556183177 |
|
|
Mar 07 01:14:55 PM PST 24 |
Mar 07 01:20:38 PM PST 24 |
5498230799 ps |
| T301 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.962200608 |
|
|
Mar 07 01:12:24 PM PST 24 |
Mar 07 01:16:35 PM PST 24 |
15755637847 ps |
| T302 |
/workspace/coverage/default/13.sram_ctrl_alert_test.1055987870 |
|
|
Mar 07 01:12:13 PM PST 24 |
Mar 07 01:12:14 PM PST 24 |
13180339 ps |
| T303 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2465246467 |
|
|
Mar 07 01:13:05 PM PST 24 |
Mar 07 01:15:35 PM PST 24 |
15072026880 ps |
| T21 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2620234751 |
|
|
Mar 07 01:11:38 PM PST 24 |
Mar 07 01:11:42 PM PST 24 |
650860254 ps |
| T35 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2724917053 |
|
|
Mar 07 01:11:50 PM PST 24 |
Mar 07 01:11:51 PM PST 24 |
50523717 ps |
| T36 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3593115846 |
|
|
Mar 07 01:13:24 PM PST 24 |
Mar 07 01:13:31 PM PST 24 |
3942788363 ps |
| T37 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2349542530 |
|
|
Mar 07 01:16:12 PM PST 24 |
Mar 07 01:33:47 PM PST 24 |
12888484724 ps |
| T38 |
/workspace/coverage/default/17.sram_ctrl_alert_test.361826524 |
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Mar 07 01:12:29 PM PST 24 |
Mar 07 01:12:30 PM PST 24 |
34881609 ps |