Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	140936586	1			T1	162234		T2	2224		T3	102191
triple_byte_access	2761247	1			T1	3218		T2	37		T3	2136
halfword_access	4230719	1			T1	4988		T2	67		T3	3153
byte_access	5903588	1			T1	6566		T2	99		T3	4177
zero_access	1774385	1			T1	1578		T2	19		T3	1040

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77396875

1

T1

89431

T2

1206

T3

56546

auto[1]

78209650

1

T1

89153

T2

1240

T3

56151

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69936832	1			T1	81219		T2	1099		T3	51271
auto[0]	triple_byte_access	1318511	1			T1	1630		T2	18		T3	1068
auto[0]	halfword_access	2068722	1			T1	2508		T2	29		T3	1574
auto[0]	byte_access	3020717	1			T1	3295		T2	49		T3	2126
auto[0]	zero_access	1052093	1			T1	779		T2	11		T3	507
auto[1]	word_access	70999754	1			T1	81015		T2	1125		T3	50920
auto[1]	triple_byte_access	1442736	1			T1	1588		T2	19		T3	1068
auto[1]	halfword_access	2161997	1			T1	2480		T2	38		T3	1579
auto[1]	byte_access	2882871	1			T1	3271		T2	50		T3	2051
auto[1]	zero_access	722292	1			T1	799		T2	8		T3	533