Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	337441536	1			T2	18014		T3	327680		T4	9152
instr_valid_dis	298848296	1			T2	18014		T3	327680		T4	9152
instr_en	28861963	1			T19	206556		T20	435106		T21	213330

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10723494	1			T19	10016		T20	49086		T21	43308
sram_ifetch_valid_disable	300300725	1			T2	18014		T3	327680		T4	9152
sram_ifetch_enable	26417317	1			T19	41966		T20	193850		T21	199486

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	337441536	1			T2	18014		T3	327680		T4	9152
hw_debug_en_valid_off	298892882	1			T2	18014		T3	327680		T4	9152
hw_debug_en_on	26739012	1			T19	119112		T20	205766		T21	137810

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	300300725	1			T2	18014		T3	327680		T4	9152
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	284885028	1			T2	18014		T3	327680		T4	9152
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11607293	1			T19	154574		T20	192170		T21	60508
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4228552	1			T20	3236		T47	42828		T130	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1737778	1			T47	7300		T130	20000		T31	123076
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2035092	1			T20	3236		T47	35528		T31	64910
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4315344	1			T20	30074		T21	43308		T30	89392
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1472750	1			T47	27410		T130	12402		T31	5386
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1833250	1			T20	30074		T21	43308		T30	89392
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10352644	1			T19	77146		T20	54144		T21	51570
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5772706	1			T21	14464		T137	38516		T30	19772
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3375312	1			T19	77146		T20	54144		T21	37106

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12538174	1			T19	41966		T20	193850		T21	109514
lc_exec_en	12071024	1			T19	41966		T20	121548		T21	42932
valid_exec_dis	295679239	1			T2	18014		T3	327680		T4	9152
invalid_exec_dis	37140811	1			T19	51982		T20	242936		T21	242794