Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	100.00	97.91	100.00	100.00	99.72	99.70	98.52

Total tests in report: 1026

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
85.47	85.47	97.85	97.85	81.17	81.17	96.09	96.09	100.00	100.00	91.27	91.27	94.95	94.95	36.92	36.92	/workspace/coverage/default/46.sram_ctrl_stress_all.1103546148
90.96	5.49	98.88	1.03	86.75	5.58	96.80	0.71	100.00	0.00	92.96	1.69	96.73	1.78	64.56	27.64	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2857903647
94.33	3.38	99.16	0.28	89.54	2.79	96.80	0.00	100.00	0.00	95.21	2.25	96.88	0.15	82.75	18.18	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.85830957
96.48	2.15	99.44	0.28	92.89	3.35	98.15	1.35	100.00	0.00	97.46	2.25	96.88	0.00	90.54	7.79	/workspace/coverage/default/14.sram_ctrl_stress_all.4113701647
97.53	1.05	99.91	0.47	95.96	3.07	98.72	0.57	100.00	0.00	99.72	2.25	97.47	0.59	90.91	0.37	/workspace/coverage/default/1.sram_ctrl_sec_cm.395429618
98.25	0.72	99.91	0.00	96.37	0.42	98.72	0.00	100.00	0.00	99.72	0.00	97.47	0.00	95.55	4.64	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2698377659
98.52	0.27	99.91	0.00	96.65	0.28	98.79	0.07	100.00	0.00	99.72	0.00	98.66	1.19	95.92	0.37	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2124080511
98.74	0.22	99.91	0.00	97.21	0.56	99.22	0.43	100.00	0.00	99.72	0.00	98.66	0.00	96.47	0.56	/workspace/coverage/default/11.sram_ctrl_alert_test.3653288933
98.91	0.17	99.91	0.00	97.49	0.28	99.22	0.00	100.00	0.00	99.72	0.00	99.55	0.89	96.47	0.00	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3498977973
99.04	0.13	99.91	0.00	97.49	0.00	99.22	0.00	100.00	0.00	99.72	0.00	99.55	0.00	97.40	0.93	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2447864414
99.16	0.11	100.00	0.09	97.49	0.00	99.93	0.71	100.00	0.00	99.72	0.00	99.55	0.00	97.40	0.00	/workspace/coverage/default/19.sram_ctrl_ram_cfg.2094283271
99.26	0.10	100.00	0.00	97.63	0.14	99.93	0.00	100.00	0.00	99.72	0.00	99.55	0.00	97.96	0.56	/workspace/coverage/default/31.sram_ctrl_stress_all.4179982134
99.31	0.05	100.00	0.00	97.63	0.00	99.93	0.00	100.00	0.00	99.72	0.00	99.55	0.00	98.33	0.37	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3786433022
99.34	0.03	100.00	0.00	97.63	0.00	99.93	0.00	100.00	0.00	99.72	0.00	99.55	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3450757195
99.36	0.02	100.00	0.00	97.63	0.00	99.93	0.00	100.00	0.00	99.72	0.00	99.70	0.15	98.52	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2778148504
99.37	0.01	100.00	0.00	97.63	0.00	100.00	0.07	100.00	0.00	99.72	0.00	99.70	0.00	98.52	0.00	/workspace/coverage/default/10.sram_ctrl_stress_all.700051721

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2149591588
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.856745660
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3417027228
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3334106761
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3714428641
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.336637236
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2573956577
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3032964372
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2915040241
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3221935298
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2710329835
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3754571179
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1113231088
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4070385786
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.168384545
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1189755502
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1185657786
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.54672562
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.995099264
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.813896943
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2367038980
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3409950165
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2260479513
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2213697373
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4073162964
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2303125242
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2684678402
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1434943921
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2522809349
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3108549326
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.328043064
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2698117038
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2533086215
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1470575058
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4214576605
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2411165485
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2685981644
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2654317415
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4055752156
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2345379424
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.73101871
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1329664400
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1433000710
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4155458385
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1424799653
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1538307807
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1485067956
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2529317352
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2177059867
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.622110151
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2586409870
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.461309102
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2487711282
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2654238946
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3303359050
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.310049359
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1308402920
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1925974743
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3332867410
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3769280010
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1451994086
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2699363354
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.238839566
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1494547042
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1541175887
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.216685332
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3867847372
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2427931968
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.21422301
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4160912285
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3435924711
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3531987612
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2929776005
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2374790514
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1705797502
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1199609224
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4008518717
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2706635401
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2203383688
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3229631711
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2682484237
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.439918496
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1609803935
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2582436826
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3193301238
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.940915592
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3441139962
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.439993482
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2333871029
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3660287576
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2453827104
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4242395386
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4239779464
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3699138583
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.323437339
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2952191359
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.115267485
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2891548637
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.908545004
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.832152166
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2362257431
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3302207612
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2740242099
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.12842144
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4165898639
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.616718354
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4091736825
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.475601249
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1223263576
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2978143337
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3293197459
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.493167032
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1569672138
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3314622935
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1450192675
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3610916439
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2233931958
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2788231084
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3245438829
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3488698853
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3167849785
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2016854934
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1735249602
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3893160045
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1574131568
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3112508359
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.882447787
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2040869404
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3084265542
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1364715212
/workspace/coverage/default/0.sram_ctrl_alert_test.3430732811
/workspace/coverage/default/0.sram_ctrl_bijection.286311557
/workspace/coverage/default/0.sram_ctrl_executable.1615587760
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3014069049
/workspace/coverage/default/0.sram_ctrl_max_throughput.1025069675
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.280540156
/workspace/coverage/default/0.sram_ctrl_mem_walk.1314946417
/workspace/coverage/default/0.sram_ctrl_multiple_keys.390081593
/workspace/coverage/default/0.sram_ctrl_partial_access.2087597994
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2868218948
/workspace/coverage/default/0.sram_ctrl_ram_cfg.898407509
/workspace/coverage/default/0.sram_ctrl_regwen.701525455
/workspace/coverage/default/0.sram_ctrl_sec_cm.3906789728
/workspace/coverage/default/0.sram_ctrl_smoke.2262651724
/workspace/coverage/default/0.sram_ctrl_stress_all.1004090170
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3208439999
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2362384963
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3498409271
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4227083285
/workspace/coverage/default/1.sram_ctrl_alert_test.1230597932
/workspace/coverage/default/1.sram_ctrl_bijection.1915434799
/workspace/coverage/default/1.sram_ctrl_executable.184302824
/workspace/coverage/default/1.sram_ctrl_lc_escalation.990301471
/workspace/coverage/default/1.sram_ctrl_max_throughput.1306382602
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1442937024
/workspace/coverage/default/1.sram_ctrl_mem_walk.3333262717
/workspace/coverage/default/1.sram_ctrl_multiple_keys.905307704
/workspace/coverage/default/1.sram_ctrl_partial_access.2883458314
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2405024685
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2029989686
/workspace/coverage/default/1.sram_ctrl_regwen.3309093776
/workspace/coverage/default/1.sram_ctrl_smoke.2747658231
/workspace/coverage/default/1.sram_ctrl_stress_all.905442214
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1126648041
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.774646307
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1380850518
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3386374410
/workspace/coverage/default/10.sram_ctrl_alert_test.10699951
/workspace/coverage/default/10.sram_ctrl_bijection.3585460436
/workspace/coverage/default/10.sram_ctrl_executable.1091149960
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3803547759
/workspace/coverage/default/10.sram_ctrl_max_throughput.989324971
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.571382627
/workspace/coverage/default/10.sram_ctrl_mem_walk.2030268828
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3017941444
/workspace/coverage/default/10.sram_ctrl_partial_access.9206397
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.120400995
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2012668844
/workspace/coverage/default/10.sram_ctrl_regwen.519509879
/workspace/coverage/default/10.sram_ctrl_smoke.2101452970
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4247508740
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2581492450
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2925062989
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1417252736
/workspace/coverage/default/11.sram_ctrl_bijection.619462826
/workspace/coverage/default/11.sram_ctrl_executable.519827923
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2955698430
/workspace/coverage/default/11.sram_ctrl_max_throughput.3193466246
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.612584152
/workspace/coverage/default/11.sram_ctrl_mem_walk.206780634
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2621205473
/workspace/coverage/default/11.sram_ctrl_partial_access.1051547552
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.903208354
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3793911585
/workspace/coverage/default/11.sram_ctrl_regwen.3862253266
/workspace/coverage/default/11.sram_ctrl_smoke.1419422904
/workspace/coverage/default/11.sram_ctrl_stress_all.65140489
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3898790858
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.536355681
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2640230461
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2656061500
/workspace/coverage/default/12.sram_ctrl_alert_test.1668484521
/workspace/coverage/default/12.sram_ctrl_bijection.2035583842
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/workspace/coverage/default/43.sram_ctrl_access_during_key_req.267297280
/workspace/coverage/default/43.sram_ctrl_alert_test.1158559157
/workspace/coverage/default/43.sram_ctrl_bijection.2557440752
/workspace/coverage/default/43.sram_ctrl_executable.2698936700
/workspace/coverage/default/43.sram_ctrl_lc_escalation.379518756
/workspace/coverage/default/43.sram_ctrl_max_throughput.3540682479
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3530430723
/workspace/coverage/default/43.sram_ctrl_mem_walk.2209341231
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3298908513
/workspace/coverage/default/43.sram_ctrl_partial_access.1078861783
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.356844898
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1650019985
/workspace/coverage/default/43.sram_ctrl_regwen.385696379
/workspace/coverage/default/43.sram_ctrl_smoke.670096550
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3064364541
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.646878667
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1181712631
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.580989772
/workspace/coverage/default/44.sram_ctrl_alert_test.907976229
/workspace/coverage/default/44.sram_ctrl_bijection.205473664
/workspace/coverage/default/44.sram_ctrl_executable.1065035077
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1225283783
/workspace/coverage/default/44.sram_ctrl_max_throughput.2229963402
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3715406334
/workspace/coverage/default/44.sram_ctrl_mem_walk.3714278268
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3696809350
/workspace/coverage/default/44.sram_ctrl_partial_access.2073539823
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2564796256
/workspace/coverage/default/44.sram_ctrl_ram_cfg.680505970
/workspace/coverage/default/44.sram_ctrl_regwen.2586026096
/workspace/coverage/default/44.sram_ctrl_smoke.714279676
/workspace/coverage/default/44.sram_ctrl_stress_all.1747816366
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4189640352
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1823272762
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.601115364
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1224537322
/workspace/coverage/default/45.sram_ctrl_alert_test.1224764494
/workspace/coverage/default/45.sram_ctrl_bijection.2778375752
/workspace/coverage/default/45.sram_ctrl_executable.4075985953
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1001366592
/workspace/coverage/default/45.sram_ctrl_max_throughput.4254676168
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.894646314
/workspace/coverage/default/45.sram_ctrl_mem_walk.2205515935
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2580052879
/workspace/coverage/default/45.sram_ctrl_partial_access.1136337987
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.875839650
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1131733122
/workspace/coverage/default/45.sram_ctrl_regwen.3251222659
/workspace/coverage/default/45.sram_ctrl_smoke.2267900817
/workspace/coverage/default/45.sram_ctrl_stress_all.871843288
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3590819069
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4265965584
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.810194622
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.4078490720
/workspace/coverage/default/46.sram_ctrl_alert_test.1060916890
/workspace/coverage/default/46.sram_ctrl_bijection.2525858023
/workspace/coverage/default/46.sram_ctrl_executable.3051257135
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3533092355
/workspace/coverage/default/46.sram_ctrl_max_throughput.1881911948
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.378375995
/workspace/coverage/default/46.sram_ctrl_mem_walk.1896283331
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1081510371
/workspace/coverage/default/46.sram_ctrl_partial_access.2165885829
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.715227358
/workspace/coverage/default/46.sram_ctrl_ram_cfg.4036355720
/workspace/coverage/default/46.sram_ctrl_regwen.1120470633
/workspace/coverage/default/46.sram_ctrl_smoke.1744605754
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1818391519
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2761243839
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4083289137
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1522168068
/workspace/coverage/default/47.sram_ctrl_alert_test.1506978502
/workspace/coverage/default/47.sram_ctrl_bijection.3977209114
/workspace/coverage/default/47.sram_ctrl_executable.2424579324
/workspace/coverage/default/47.sram_ctrl_max_throughput.3955139220
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1439973074
/workspace/coverage/default/47.sram_ctrl_mem_walk.915881328
/workspace/coverage/default/47.sram_ctrl_multiple_keys.782546695
/workspace/coverage/default/47.sram_ctrl_partial_access.232315467
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3860882454
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3934329583
/workspace/coverage/default/47.sram_ctrl_regwen.1853386588
/workspace/coverage/default/47.sram_ctrl_smoke.1848319434
/workspace/coverage/default/47.sram_ctrl_stress_all.1388850317
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.699769127
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3646186386
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2211072024
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3281937096
/workspace/coverage/default/48.sram_ctrl_alert_test.2294631574
/workspace/coverage/default/48.sram_ctrl_bijection.1941738726
/workspace/coverage/default/48.sram_ctrl_executable.1924189342
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2944951840
/workspace/coverage/default/48.sram_ctrl_max_throughput.4098772261
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2158906039
/workspace/coverage/default/48.sram_ctrl_mem_walk.2312645351
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3405440630
/workspace/coverage/default/48.sram_ctrl_partial_access.776265458
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.667799220
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3400314172
/workspace/coverage/default/48.sram_ctrl_regwen.63833846
/workspace/coverage/default/48.sram_ctrl_smoke.86906931
/workspace/coverage/default/48.sram_ctrl_stress_all.4117883573
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1825065184
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3794237678
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2371188826
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1298302476
/workspace/coverage/default/49.sram_ctrl_alert_test.1762019436
/workspace/coverage/default/49.sram_ctrl_bijection.3298813561
/workspace/coverage/default/49.sram_ctrl_executable.2741618332
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2173487662
/workspace/coverage/default/49.sram_ctrl_max_throughput.2000752993
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3703011071
/workspace/coverage/default/49.sram_ctrl_mem_walk.652642467
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3145486712
/workspace/coverage/default/49.sram_ctrl_partial_access.3450886036
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3137203457
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3424101052
/workspace/coverage/default/49.sram_ctrl_smoke.530994995
/workspace/coverage/default/49.sram_ctrl_stress_all.3431714541
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1357145295
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2461698119
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4037885782
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2527672591
/workspace/coverage/default/5.sram_ctrl_alert_test.1809861341
/workspace/coverage/default/5.sram_ctrl_bijection.2933012783
/workspace/coverage/default/5.sram_ctrl_executable.1209670482
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3683234780
/workspace/coverage/default/5.sram_ctrl_max_throughput.2658579644
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2800070899
/workspace/coverage/default/5.sram_ctrl_mem_walk.111572483
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1230346915
/workspace/coverage/default/5.sram_ctrl_partial_access.2600501989
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1125629521
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2824295015
/workspace/coverage/default/5.sram_ctrl_regwen.161224333
/workspace/coverage/default/5.sram_ctrl_smoke.2546549921
/workspace/coverage/default/5.sram_ctrl_stress_all.2044489563
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1016655456
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2541363059
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.32368813
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2627714341
/workspace/coverage/default/6.sram_ctrl_alert_test.3893730425
/workspace/coverage/default/6.sram_ctrl_bijection.210287448
/workspace/coverage/default/6.sram_ctrl_executable.269098833
/workspace/coverage/default/6.sram_ctrl_lc_escalation.143285060
/workspace/coverage/default/6.sram_ctrl_max_throughput.2783215435
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.181893264
/workspace/coverage/default/6.sram_ctrl_mem_walk.4116611381
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3458743672
/workspace/coverage/default/6.sram_ctrl_partial_access.1865022978
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2276483641
/workspace/coverage/default/6.sram_ctrl_ram_cfg.923396665
/workspace/coverage/default/6.sram_ctrl_regwen.2366927203
/workspace/coverage/default/6.sram_ctrl_smoke.3478334996
/workspace/coverage/default/6.sram_ctrl_stress_all.2340812641
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.669957523
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2322148194
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.636912179
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3810524068
/workspace/coverage/default/7.sram_ctrl_alert_test.3361918009
/workspace/coverage/default/7.sram_ctrl_executable.3632298626
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2259944165
/workspace/coverage/default/7.sram_ctrl_max_throughput.685082080
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.59534287
/workspace/coverage/default/7.sram_ctrl_mem_walk.4216698906
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4100220132
/workspace/coverage/default/7.sram_ctrl_partial_access.2458330108
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3860774813
/workspace/coverage/default/7.sram_ctrl_ram_cfg.444351127
/workspace/coverage/default/7.sram_ctrl_regwen.2809381998
/workspace/coverage/default/7.sram_ctrl_smoke.1410831808
/workspace/coverage/default/7.sram_ctrl_stress_all.438243931
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.283554564
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.394236857
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.690322033
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1706101862
/workspace/coverage/default/8.sram_ctrl_alert_test.3737626430
/workspace/coverage/default/8.sram_ctrl_bijection.672631759
/workspace/coverage/default/8.sram_ctrl_executable.4178396570
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3402291246
/workspace/coverage/default/8.sram_ctrl_max_throughput.1237269915
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.786910171
/workspace/coverage/default/8.sram_ctrl_mem_walk.3338605406
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1492812187
/workspace/coverage/default/8.sram_ctrl_partial_access.1314987023
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.699547746
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1248357787
/workspace/coverage/default/8.sram_ctrl_regwen.1902136573
/workspace/coverage/default/8.sram_ctrl_smoke.4689079
/workspace/coverage/default/8.sram_ctrl_stress_all.1088177355
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1300274666
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1513879540
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4053245085
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2436392145
/workspace/coverage/default/9.sram_ctrl_alert_test.1309481388
/workspace/coverage/default/9.sram_ctrl_bijection.2800332307
/workspace/coverage/default/9.sram_ctrl_executable.2512038227
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3123110386
/workspace/coverage/default/9.sram_ctrl_max_throughput.3000082912
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1584810269
/workspace/coverage/default/9.sram_ctrl_mem_walk.1189030151
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1863422254
/workspace/coverage/default/9.sram_ctrl_partial_access.2104897382
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1223729996
/workspace/coverage/default/9.sram_ctrl_ram_cfg.4066682790
/workspace/coverage/default/9.sram_ctrl_regwen.4264036744
/workspace/coverage/default/9.sram_ctrl_smoke.1998149972
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1474932964
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1039523721
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.104151461

Total test records in report: 1026

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/7.sram_ctrl_ram_cfg.444351127	Mar 10 02:00:46 PM PDT 24	Mar 10 02:00:51 PM PDT 24	1351092761 ps
T2	/workspace/coverage/default/46.sram_ctrl_partial_access.2165885829	Mar 10 02:05:49 PM PDT 24	Mar 10 02:06:11 PM PDT 24	6148703207 ps
T3	/workspace/coverage/default/23.sram_ctrl_bijection.2414713222	Mar 10 02:02:23 PM PDT 24	Mar 10 02:51:50 PM PDT 24	718563063410 ps
T4	/workspace/coverage/default/45.sram_ctrl_partial_access.1136337987	Mar 10 02:05:41 PM PDT 24	Mar 10 02:06:06 PM PDT 24	1231179819 ps
T5	/workspace/coverage/default/46.sram_ctrl_stress_all.1103546148	Mar 10 02:06:08 PM PDT 24	Mar 10 02:36:58 PM PDT 24	135148050095 ps
T8	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.536355681	Mar 10 02:00:54 PM PDT 24	Mar 10 02:02:27 PM PDT 24	6124151020 ps
T9	/workspace/coverage/default/23.sram_ctrl_ram_cfg.3920391747	Mar 10 02:02:24 PM PDT 24	Mar 10 02:02:27 PM PDT 24	347359692 ps
T10	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.85830957	Mar 10 02:04:07 PM PDT 24	Mar 10 02:09:50 PM PDT 24	15222464480 ps
T11	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.223919937	Mar 10 02:01:32 PM PDT 24	Mar 10 02:05:30 PM PDT 24	9537287228 ps
T12	/workspace/coverage/default/1.sram_ctrl_partial_access.2883458314	Mar 10 02:00:29 PM PDT 24	Mar 10 02:00:38 PM PDT 24	378836022 ps
T17	/workspace/coverage/default/25.sram_ctrl_ram_cfg.3572018073	Mar 10 02:02:36 PM PDT 24	Mar 10 02:02:40 PM PDT 24	362108247 ps
T14	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3794730842	Mar 10 02:05:07 PM PDT 24	Mar 10 02:10:15 PM PDT 24	8949197011 ps
T15	/workspace/coverage/default/49.sram_ctrl_smoke.530994995	Mar 10 02:06:26 PM PDT 24	Mar 10 02:06:41 PM PDT 24	1014432700 ps
T16	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1960845165	Mar 10 02:02:49 PM PDT 24	Mar 10 02:06:51 PM PDT 24	3024644954 ps
T102	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3704919480	Mar 10 02:02:02 PM PDT 24	Mar 10 02:04:31 PM PDT 24	1538443419 ps
T155	/workspace/coverage/default/31.sram_ctrl_ram_cfg.4180331514	Mar 10 02:03:24 PM PDT 24	Mar 10 02:03:28 PM PDT 24	1404880343 ps
T24	/workspace/coverage/default/21.sram_ctrl_alert_test.3068584544	Mar 10 02:02:08 PM PDT 24	Mar 10 02:02:09 PM PDT 24	31506897 ps
T25	/workspace/coverage/default/7.sram_ctrl_alert_test.3361918009	Mar 10 02:00:50 PM PDT 24	Mar 10 02:00:51 PM PDT 24	49718070 ps
T156	/workspace/coverage/default/27.sram_ctrl_mem_walk.1280804765	Mar 10 02:02:55 PM PDT 24	Mar 10 02:05:39 PM PDT 24	13786469780 ps
T18	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1785751914	Mar 10 02:01:17 PM PDT 24	Mar 10 02:24:00 PM PDT 24	30645429824 ps
T79	/workspace/coverage/default/10.sram_ctrl_max_throughput.989324971	Mar 10 02:00:54 PM PDT 24	Mar 10 02:01:12 PM PDT 24	6293799019 ps
T13	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.718495335	Mar 10 02:02:56 PM PDT 24	Mar 10 02:04:12 PM PDT 24	2647726154 ps
T80	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2276483641	Mar 10 02:00:47 PM PDT 24	Mar 10 02:10:14 PM PDT 24	23531110685 ps
T74	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.4036112794	Mar 10 02:01:53 PM PDT 24	Mar 10 02:05:30 PM PDT 24	28767613157 ps
T75	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.894646314	Mar 10 02:05:47 PM PDT 24	Mar 10 02:06:53 PM PDT 24	945767517 ps
T81	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.547084733	Mar 10 02:03:52 PM PDT 24	Mar 10 02:06:11 PM PDT 24	1438757511 ps
T76	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.55908143	Mar 10 02:02:06 PM PDT 24	Mar 10 02:03:09 PM PDT 24	996225959 ps
T82	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.636912179	Mar 10 02:00:47 PM PDT 24	Mar 10 02:01:15 PM PDT 24	717480982 ps
T83	/workspace/coverage/default/6.sram_ctrl_smoke.3478334996	Mar 10 02:00:42 PM PDT 24	Mar 10 02:00:48 PM PDT 24	6828613844 ps
T97	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1223729996	Mar 10 02:00:52 PM PDT 24	Mar 10 02:07:02 PM PDT 24	33415281776 ps
T98	/workspace/coverage/default/36.sram_ctrl_multiple_keys.3061608374	Mar 10 02:04:06 PM PDT 24	Mar 10 02:26:24 PM PDT 24	10888182812 ps
T19	/workspace/coverage/default/37.sram_ctrl_regwen.296764725	Mar 10 02:04:25 PM PDT 24	Mar 10 02:11:35 PM PDT 24	7721621744 ps
T77	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2541363059	Mar 10 02:00:46 PM PDT 24	Mar 10 02:03:19 PM PDT 24	6090580382 ps
T20	/workspace/coverage/default/27.sram_ctrl_regwen.3178657944	Mar 10 02:02:55 PM PDT 24	Mar 10 02:24:15 PM PDT 24	74559644565 ps
T78	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.394236857	Mar 10 02:00:45 PM PDT 24	Mar 10 02:03:13 PM PDT 24	5671198761 ps
T157	/workspace/coverage/default/25.sram_ctrl_max_throughput.1723945555	Mar 10 02:02:37 PM PDT 24	Mar 10 02:02:45 PM PDT 24	2797317540 ps
T134	/workspace/coverage/default/37.sram_ctrl_partial_access.2561556524	Mar 10 02:04:25 PM PDT 24	Mar 10 02:04:30 PM PDT 24	1691367239 ps
T21	/workspace/coverage/default/47.sram_ctrl_executable.2424579324	Mar 10 02:06:11 PM PDT 24	Mar 10 02:26:21 PM PDT 24	71807421911 ps
T158	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3424411580	Mar 10 02:01:33 PM PDT 24	Mar 10 02:02:07 PM PDT 24	744973517 ps
T154	/workspace/coverage/default/18.sram_ctrl_smoke.1910539819	Mar 10 02:01:46 PM PDT 24	Mar 10 02:01:55 PM PDT 24	1508321564 ps
T135	/workspace/coverage/default/42.sram_ctrl_partial_access.184987872	Mar 10 02:05:12 PM PDT 24	Mar 10 02:05:32 PM PDT 24	620591673 ps
T136	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.875839650	Mar 10 02:05:42 PM PDT 24	Mar 10 02:11:10 PM PDT 24	150217290352 ps
T61	/workspace/coverage/default/1.sram_ctrl_regwen.3309093776	Mar 10 02:00:34 PM PDT 24	Mar 10 02:17:45 PM PDT 24	4877525861 ps
T147	/workspace/coverage/default/19.sram_ctrl_multiple_keys.1987396689	Mar 10 02:01:46 PM PDT 24	Mar 10 02:08:41 PM PDT 24	6900188334 ps
T26	/workspace/coverage/default/48.sram_ctrl_alert_test.2294631574	Mar 10 02:06:24 PM PDT 24	Mar 10 02:06:25 PM PDT 24	17218891 ps
T140	/workspace/coverage/default/11.sram_ctrl_alert_test.3653288933	Mar 10 02:01:09 PM PDT 24	Mar 10 02:01:09 PM PDT 24	21445516 ps
T159	/workspace/coverage/default/14.sram_ctrl_max_throughput.1245372414	Mar 10 02:01:20 PM PDT 24	Mar 10 02:01:41 PM PDT 24	750747773 ps
T160	/workspace/coverage/default/44.sram_ctrl_ram_cfg.680505970	Mar 10 02:05:37 PM PDT 24	Mar 10 02:05:41 PM PDT 24	1350250686 ps
T151	/workspace/coverage/default/31.sram_ctrl_bijection.3044564038	Mar 10 02:03:24 PM PDT 24	Mar 10 02:11:00 PM PDT 24	14065484419 ps
T139	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2461698119	Mar 10 02:06:25 PM PDT 24	Mar 10 02:11:04 PM PDT 24	44409477139 ps
T141	/workspace/coverage/default/46.sram_ctrl_multiple_keys.1081510371	Mar 10 02:05:49 PM PDT 24	Mar 10 02:28:02 PM PDT 24	27119461805 ps
T161	/workspace/coverage/default/21.sram_ctrl_smoke.2989436973	Mar 10 02:02:03 PM PDT 24	Mar 10 02:02:16 PM PDT 24	857126342 ps
T152	/workspace/coverage/default/24.sram_ctrl_partial_access.2152233256	Mar 10 02:02:32 PM PDT 24	Mar 10 02:05:15 PM PDT 24	886473473 ps
T162	/workspace/coverage/default/46.sram_ctrl_ram_cfg.4036355720	Mar 10 02:05:58 PM PDT 24	Mar 10 02:06:02 PM PDT 24	871082566 ps
T163	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.16689607	Mar 10 02:02:13 PM PDT 24	Mar 10 02:03:23 PM PDT 24	15222724406 ps
T90	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1890115533	Mar 10 02:01:21 PM PDT 24	Mar 10 02:02:35 PM PDT 24	11064818328 ps
T91	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1208354672	Mar 10 02:01:48 PM PDT 24	Mar 10 02:04:07 PM PDT 24	1629314433 ps
T164	/workspace/coverage/default/35.sram_ctrl_mem_walk.2372375414	Mar 10 02:04:15 PM PDT 24	Mar 10 02:08:20 PM PDT 24	3945152964 ps
T165	/workspace/coverage/default/46.sram_ctrl_max_throughput.1881911948	Mar 10 02:05:56 PM PDT 24	Mar 10 02:06:26 PM PDT 24	1448208650 ps
T166	/workspace/coverage/default/36.sram_ctrl_smoke.1830590090	Mar 10 02:04:15 PM PDT 24	Mar 10 02:06:44 PM PDT 24	5040067165 ps
T137	/workspace/coverage/default/49.sram_ctrl_executable.2741618332	Mar 10 02:06:32 PM PDT 24	Mar 10 02:08:30 PM PDT 24	30112638021 ps
T92	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1015718544	Mar 10 02:03:46 PM PDT 24	Mar 10 02:06:19 PM PDT 24	17356740386 ps
T22	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3498977973	Mar 10 02:02:42 PM PDT 24	Mar 10 02:20:22 PM PDT 24	10686248697 ps
T146	/workspace/coverage/default/17.sram_ctrl_max_throughput.1093198465	Mar 10 02:01:36 PM PDT 24	Mar 10 02:02:10 PM PDT 24	726912134 ps
T167	/workspace/coverage/default/11.sram_ctrl_mem_walk.206780634	Mar 10 02:01:00 PM PDT 24	Mar 10 02:03:47 PM PDT 24	21542160925 ps
T33	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2857903647	Mar 10 02:01:40 PM PDT 24	Mar 10 02:01:56 PM PDT 24	2126068472 ps
T55	/workspace/coverage/default/32.sram_ctrl_bijection.692287523	Mar 10 02:03:30 PM PDT 24	Mar 10 02:25:37 PM PDT 24	330825679881 ps
T56	/workspace/coverage/default/39.sram_ctrl_smoke.1258254557	Mar 10 02:04:37 PM PDT 24	Mar 10 02:05:54 PM PDT 24	423411897 ps
T57	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.527560868	Mar 10 02:03:19 PM PDT 24	Mar 10 02:09:08 PM PDT 24	49177712694 ps
T6	/workspace/coverage/default/6.sram_ctrl_stress_all.2340812641	Mar 10 02:00:59 PM PDT 24	Mar 10 03:07:23 PM PDT 24	507919422598 ps
T30	/workspace/coverage/default/16.sram_ctrl_regwen.2120547112	Mar 10 02:01:32 PM PDT 24	Mar 10 02:10:26 PM PDT 24	9138327725 ps
T7	/workspace/coverage/default/13.sram_ctrl_lc_escalation.19402474	Mar 10 02:01:15 PM PDT 24	Mar 10 02:05:37 PM PDT 24	15148883063 ps
T58	/workspace/coverage/default/43.sram_ctrl_mem_walk.2209341231	Mar 10 02:05:28 PM PDT 24	Mar 10 02:10:37 PM PDT 24	93822051760 ps
T59	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.690322033	Mar 10 02:00:46 PM PDT 24	Mar 10 02:01:51 PM PDT 24	2158589162 ps
T60	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3208436085	Mar 10 02:04:47 PM PDT 24	Mar 10 02:05:32 PM PDT 24	797686951 ps
T62	/workspace/coverage/default/2.sram_ctrl_lc_escalation.2395449144	Mar 10 02:00:34 PM PDT 24	Mar 10 02:05:08 PM PDT 24	30172390905 ps
T143	/workspace/coverage/default/4.sram_ctrl_bijection.2799359429	Mar 10 02:00:54 PM PDT 24	Mar 10 02:27:39 PM PDT 24	99724799634 ps
T148	/workspace/coverage/default/23.sram_ctrl_multiple_keys.3186128387	Mar 10 02:02:21 PM PDT 24	Mar 10 02:24:28 PM PDT 24	8236653594 ps
T47	/workspace/coverage/default/14.sram_ctrl_stress_all.4113701647	Mar 10 02:01:20 PM PDT 24	Mar 10 04:32:36 PM PDT 24	643497244387 ps
T168	/workspace/coverage/default/33.sram_ctrl_max_throughput.866610224	Mar 10 02:03:40 PM PDT 24	Mar 10 02:04:06 PM PDT 24	5022621134 ps
T169	/workspace/coverage/default/12.sram_ctrl_max_throughput.4104605848	Mar 10 02:01:08 PM PDT 24	Mar 10 02:02:25 PM PDT 24	781492051 ps
T170	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.810194622	Mar 10 02:05:41 PM PDT 24	Mar 10 02:06:23 PM PDT 24	739183115 ps
T171	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3351781337	Mar 10 02:05:02 PM PDT 24	Mar 10 02:08:27 PM PDT 24	3818198331 ps
T93	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1439973074	Mar 10 02:06:12 PM PDT 24	Mar 10 02:07:32 PM PDT 24	11048806207 ps
T153	/workspace/coverage/default/15.sram_ctrl_alert_test.534464978	Mar 10 02:01:26 PM PDT 24	Mar 10 02:01:27 PM PDT 24	34986003 ps
T172	/workspace/coverage/default/35.sram_ctrl_bijection.530195816	Mar 10 02:04:05 PM PDT 24	Mar 10 02:22:57 PM PDT 24	51288684340 ps
T130	/workspace/coverage/default/45.sram_ctrl_executable.4075985953	Mar 10 02:05:50 PM PDT 24	Mar 10 02:20:33 PM PDT 24	25550936579 ps
T63	/workspace/coverage/default/35.sram_ctrl_lc_escalation.3059984264	Mar 10 02:04:03 PM PDT 24	Mar 10 02:06:22 PM PDT 24	16389268687 ps
T142	/workspace/coverage/default/15.sram_ctrl_lc_escalation.3185296598	Mar 10 02:01:24 PM PDT 24	Mar 10 02:10:11 PM PDT 24	41563099610 ps
T173	/workspace/coverage/default/17.sram_ctrl_smoke.2871455207	Mar 10 02:01:34 PM PDT 24	Mar 10 02:04:18 PM PDT 24	1658921564 ps
T174	/workspace/coverage/default/37.sram_ctrl_bijection.2237434044	Mar 10 02:04:25 PM PDT 24	Mar 10 02:54:18 PM PDT 24	638303058504 ps
T150	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.4044819909	Mar 10 02:02:09 PM PDT 24	Mar 10 02:06:56 PM PDT 24	35435307315 ps
T175	/workspace/coverage/default/3.sram_ctrl_bijection.3181940636	Mar 10 02:00:50 PM PDT 24	Mar 10 02:10:01 PM PDT 24	16410903674 ps
T144	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2904699267	Mar 10 02:04:33 PM PDT 24	Mar 10 02:08:41 PM PDT 24	18022128219 ps
T32	/workspace/coverage/default/0.sram_ctrl_lc_escalation.3014069049	Mar 10 02:00:33 PM PDT 24	Mar 10 02:03:11 PM PDT 24	9152197264 ps
T34	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.585598235	Mar 10 02:01:45 PM PDT 24	Mar 10 02:01:53 PM PDT 24	494501174 ps
T149	/workspace/coverage/default/12.sram_ctrl_alert_test.1668484521	Mar 10 02:01:11 PM PDT 24	Mar 10 02:01:12 PM PDT 24	19800743 ps
T145	/workspace/coverage/default/9.sram_ctrl_alert_test.1309481388	Mar 10 02:00:53 PM PDT 24	Mar 10 02:00:55 PM PDT 24	66848378 ps
T138	/workspace/coverage/default/33.sram_ctrl_bijection.2374225892	Mar 10 02:03:41 PM PDT 24	Mar 10 02:32:43 PM PDT 24	111112630457 ps
T176	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2371188826	Mar 10 02:06:23 PM PDT 24	Mar 10 02:08:33 PM PDT 24	1499031264 ps
T35	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3316788280	Mar 10 02:02:30 PM PDT 24	Mar 10 02:04:36 PM PDT 24	1423153281 ps
T48	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1599211796	Mar 10 02:04:25 PM PDT 24	Mar 10 02:04:38 PM PDT 24	848126977 ps
T177	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.2868899455	Mar 10 02:00:44 PM PDT 24	Mar 10 02:04:12 PM PDT 24	3181596604 ps
T49	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4288853573	Mar 10 02:03:46 PM PDT 24	Mar 10 02:04:07 PM PDT 24	1270854690 ps
T178	/workspace/coverage/default/6.sram_ctrl_mem_walk.4116611381	Mar 10 02:00:45 PM PDT 24	Mar 10 02:05:05 PM PDT 24	15753006450 ps
T179	/workspace/coverage/default/15.sram_ctrl_mem_walk.3165481590	Mar 10 02:01:25 PM PDT 24	Mar 10 02:04:04 PM PDT 24	68921464039 ps
T180	/workspace/coverage/default/36.sram_ctrl_ram_cfg.663862812	Mar 10 02:04:14 PM PDT 24	Mar 10 02:04:18 PM PDT 24	366209114 ps
T181	/workspace/coverage/default/18.sram_ctrl_regwen.3123778319	Mar 10 02:01:46 PM PDT 24	Mar 10 02:04:15 PM PDT 24	7278356894 ps
T182	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.667799220	Mar 10 02:06:15 PM PDT 24	Mar 10 02:10:54 PM PDT 24	4040385916 ps
T183	/workspace/coverage/default/26.sram_ctrl_smoke.2878695682	Mar 10 02:02:34 PM PDT 24	Mar 10 02:02:56 PM PDT 24	1075072205 ps
T184	/workspace/coverage/default/13.sram_ctrl_stress_all.890362531	Mar 10 02:01:20 PM PDT 24	Mar 10 02:34:31 PM PDT 24	108913854767 ps
T50	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1595643752	Mar 10 02:03:11 PM PDT 24	Mar 10 02:03:29 PM PDT 24	1126412843 ps
T185	/workspace/coverage/default/41.sram_ctrl_max_throughput.345622333	Mar 10 02:05:01 PM PDT 24	Mar 10 02:07:09 PM PDT 24	758679359 ps
T31	/workspace/coverage/default/31.sram_ctrl_stress_all.4179982134	Mar 10 02:03:28 PM PDT 24	Mar 10 04:17:23 PM PDT 24	233670463549 ps
T186	/workspace/coverage/default/11.sram_ctrl_stress_all.65140489	Mar 10 02:00:59 PM PDT 24	Mar 10 02:16:58 PM PDT 24	23543637152 ps
T187	/workspace/coverage/default/20.sram_ctrl_alert_test.1381337994	Mar 10 02:01:59 PM PDT 24	Mar 10 02:01:59 PM PDT 24	205032476 ps
T188	/workspace/coverage/default/10.sram_ctrl_smoke.2101452970	Mar 10 02:00:52 PM PDT 24	Mar 10 02:01:19 PM PDT 24	5048288274 ps
T189	/workspace/coverage/default/34.sram_ctrl_alert_test.1626275868	Mar 10 02:03:57 PM PDT 24	Mar 10 02:03:59 PM PDT 24	33818863 ps
T190	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3215555555	Mar 10 02:00:34 PM PDT 24	Mar 10 02:00:53 PM PDT 24	2196410150 ps
T191	/workspace/coverage/default/20.sram_ctrl_partial_access.1273213248	Mar 10 02:01:52 PM PDT 24	Mar 10 02:02:46 PM PDT 24	1858197965 ps
T94	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2479917305	Mar 10 02:05:10 PM PDT 24	Mar 10 02:06:21 PM PDT 24	7115905513 ps
T192	/workspace/coverage/default/26.sram_ctrl_max_throughput.2911776938	Mar 10 02:02:46 PM PDT 24	Mar 10 02:03:11 PM PDT 24	743230392 ps
T193	/workspace/coverage/default/38.sram_ctrl_mem_walk.1443407106	Mar 10 02:04:40 PM PDT 24	Mar 10 02:09:23 PM PDT 24	13788511663 ps
T132	/workspace/coverage/default/33.sram_ctrl_executable.969528971	Mar 10 02:03:49 PM PDT 24	Mar 10 02:16:17 PM PDT 24	21960862094 ps
T23	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.4019486098	Mar 10 02:03:03 PM PDT 24	Mar 10 02:25:09 PM PDT 24	32403618659 ps
T194	/workspace/coverage/default/9.sram_ctrl_lc_escalation.3123110386	Mar 10 02:00:59 PM PDT 24	Mar 10 02:04:35 PM PDT 24	20279779694 ps
T51	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1825065184	Mar 10 02:06:26 PM PDT 24	Mar 10 02:08:02 PM PDT 24	8102932342 ps
T133	/workspace/coverage/default/27.sram_ctrl_stress_all.2861070417	Mar 10 02:02:58 PM PDT 24	Mar 10 03:11:40 PM PDT 24	692712841829 ps
T195	/workspace/coverage/default/5.sram_ctrl_smoke.2546549921	Mar 10 02:00:42 PM PDT 24	Mar 10 02:00:54 PM PDT 24	3051808226 ps
T52	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.809266321	Mar 10 02:01:58 PM PDT 24	Mar 10 02:02:51 PM PDT 24	6738805064 ps
T196	/workspace/coverage/default/20.sram_ctrl_bijection.3343593476	Mar 10 02:01:53 PM PDT 24	Mar 10 02:19:10 PM PDT 24	49197025270 ps
T197	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.4221623848	Mar 10 02:02:24 PM PDT 24	Mar 10 02:02:41 PM PDT 24	2934709779 ps
T198	/workspace/coverage/default/39.sram_ctrl_multiple_keys.1704199026	Mar 10 02:04:39 PM PDT 24	Mar 10 02:07:04 PM PDT 24	28365214971 ps
T53	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2223897782	Mar 10 02:03:27 PM PDT 24	Mar 10 02:03:45 PM PDT 24	670820422 ps
T199	/workspace/coverage/default/16.sram_ctrl_multiple_keys.2646448814	Mar 10 02:01:26 PM PDT 24	Mar 10 02:07:18 PM PDT 24	17627014137 ps
T200	/workspace/coverage/default/26.sram_ctrl_stress_all.2298063736	Mar 10 02:02:50 PM PDT 24	Mar 10 02:26:59 PM PDT 24	64787884407 ps
T131	/workspace/coverage/default/39.sram_ctrl_stress_all.4285846505	Mar 10 02:04:47 PM PDT 24	Mar 10 04:39:47 PM PDT 24	848717305313 ps
T201	/workspace/coverage/default/39.sram_ctrl_lc_escalation.3144211764	Mar 10 02:04:46 PM PDT 24	Mar 10 02:05:55 PM PDT 24	4687724788 ps
T202	/workspace/coverage/default/22.sram_ctrl_regwen.419526187	Mar 10 02:02:14 PM PDT 24	Mar 10 02:25:10 PM PDT 24	15476630632 ps
T203	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2640230461	Mar 10 02:00:54 PM PDT 24	Mar 10 02:01:09 PM PDT 24	1291916377 ps
T204	/workspace/coverage/default/6.sram_ctrl_executable.269098833	Mar 10 02:00:46 PM PDT 24	Mar 10 02:07:30 PM PDT 24	3677428287 ps
T205	/workspace/coverage/default/8.sram_ctrl_smoke.4689079	Mar 10 02:00:49 PM PDT 24	Mar 10 02:02:49 PM PDT 24	975315454 ps
T206	/workspace/coverage/default/40.sram_ctrl_partial_access.1651903965	Mar 10 02:04:54 PM PDT 24	Mar 10 02:05:16 PM PDT 24	1459398355 ps
T207	/workspace/coverage/default/26.sram_ctrl_mem_walk.2695332124	Mar 10 02:02:46 PM PDT 24	Mar 10 02:07:58 PM PDT 24	41361964088 ps
T208	/workspace/coverage/default/46.sram_ctrl_regwen.1120470633	Mar 10 02:05:57 PM PDT 24	Mar 10 02:10:15 PM PDT 24	1164437384 ps
T209	/workspace/coverage/default/33.sram_ctrl_multiple_keys.1761508157	Mar 10 02:03:40 PM PDT 24	Mar 10 02:08:20 PM PDT 24	41705337511 ps
T210	/workspace/coverage/default/36.sram_ctrl_stress_all.746142138	Mar 10 02:04:21 PM PDT 24	Mar 10 03:10:48 PM PDT 24	318273508364 ps
T54	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3898790858	Mar 10 02:01:03 PM PDT 24	Mar 10 02:01:14 PM PDT 24	338818037 ps
T211	/workspace/coverage/default/30.sram_ctrl_max_throughput.2268422848	Mar 10 02:03:18 PM PDT 24	Mar 10 02:05:52 PM PDT 24	3052513671 ps
T212	/workspace/coverage/default/35.sram_ctrl_stress_all.1058832229	Mar 10 02:04:07 PM PDT 24	Mar 10 03:11:54 PM PDT 24	113926355670 ps
T101	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.267297280	Mar 10 02:05:28 PM PDT 24	Mar 10 02:06:21 PM PDT 24	2241011468 ps
T213	/workspace/coverage/default/2.sram_ctrl_regwen.4262771018	Mar 10 02:00:33 PM PDT 24	Mar 10 02:00:45 PM PDT 24	1144118260 ps
T214	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2474046679	Mar 10 02:01:41 PM PDT 24	Mar 10 02:04:24 PM PDT 24	8742373348 ps
T215	/workspace/coverage/default/30.sram_ctrl_mem_walk.3990983789	Mar 10 02:03:23 PM PDT 24	Mar 10 02:07:27 PM PDT 24	7888916999 ps
T216	/workspace/coverage/default/0.sram_ctrl_multiple_keys.390081593	Mar 10 02:00:24 PM PDT 24	Mar 10 02:18:01 PM PDT 24	7567242599 ps
T217	/workspace/coverage/default/7.sram_ctrl_stress_all.438243931	Mar 10 02:00:50 PM PDT 24	Mar 10 02:39:41 PM PDT 24	95835347134 ps
T218	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2158906039	Mar 10 02:06:25 PM PDT 24	Mar 10 02:09:06 PM PDT 24	4431003825 ps
T219	/workspace/coverage/default/40.sram_ctrl_stress_all.1185834300	Mar 10 02:04:58 PM PDT 24	Mar 10 02:12:43 PM PDT 24	11127360942 ps
T220	/workspace/coverage/default/31.sram_ctrl_executable.2347199026	Mar 10 02:03:23 PM PDT 24	Mar 10 02:05:20 PM PDT 24	29637022901 ps
T221	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.356844898	Mar 10 02:05:16 PM PDT 24	Mar 10 02:14:01 PM PDT 24	196067868140 ps
T222	/workspace/coverage/default/10.sram_ctrl_alert_test.10699951	Mar 10 02:00:55 PM PDT 24	Mar 10 02:00:56 PM PDT 24	48162022 ps
T223	/workspace/coverage/default/4.sram_ctrl_max_throughput.3767521998	Mar 10 02:00:46 PM PDT 24	Mar 10 02:02:01 PM PDT 24	747077581 ps
T224	/workspace/coverage/default/37.sram_ctrl_executable.20566918	Mar 10 02:04:23 PM PDT 24	Mar 10 02:07:10 PM PDT 24	7195720518 ps
T225	/workspace/coverage/default/49.sram_ctrl_alert_test.1762019436	Mar 10 02:06:35 PM PDT 24	Mar 10 02:06:36 PM PDT 24	37046348 ps
T226	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.657918908	Mar 10 02:04:59 PM PDT 24	Mar 10 02:07:05 PM PDT 24	6234819052 ps
T227	/workspace/coverage/default/45.sram_ctrl_multiple_keys.2580052879	Mar 10 02:05:42 PM PDT 24	Mar 10 02:19:12 PM PDT 24	28902440523 ps
T228	/workspace/coverage/default/23.sram_ctrl_smoke.2639871337	Mar 10 02:02:21 PM PDT 24	Mar 10 02:03:49 PM PDT 24	17466098656 ps
T229	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1181712631	Mar 10 02:05:22 PM PDT 24	Mar 10 02:06:58 PM PDT 24	1561957055 ps
T230	/workspace/coverage/default/15.sram_ctrl_multiple_keys.2109169494	Mar 10 02:01:22 PM PDT 24	Mar 10 02:05:03 PM PDT 24	2389094477 ps
T231	/workspace/coverage/default/10.sram_ctrl_stress_all.700051721	Mar 10 02:00:57 PM PDT 24	Mar 10 02:55:04 PM PDT 24	56639483950 ps
T232	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2800070899	Mar 10 02:00:41 PM PDT 24	Mar 10 02:01:58 PM PDT 24	11855340630 ps
T233	/workspace/coverage/default/4.sram_ctrl_mem_walk.2783624302	Mar 10 02:00:45 PM PDT 24	Mar 10 02:05:30 PM PDT 24	26511045476 ps
T234	/workspace/coverage/default/23.sram_ctrl_partial_access.4282262311	Mar 10 02:02:22 PM PDT 24	Mar 10 02:02:35 PM PDT 24	1615532255 ps
T235	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2427032233	Mar 10 02:03:13 PM PDT 24	Mar 10 02:04:54 PM PDT 24	3047549702 ps
T236	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1422711946	Mar 10 02:02:30 PM PDT 24	Mar 10 02:05:38 PM PDT 24	24188326230 ps
T237	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3137203457	Mar 10 02:06:28 PM PDT 24	Mar 10 02:11:31 PM PDT 24	6010787739 ps
T238	/workspace/coverage/default/45.sram_ctrl_alert_test.1224764494	Mar 10 02:05:45 PM PDT 24	Mar 10 02:05:47 PM PDT 24	49076190 ps
T239	/workspace/coverage/default/28.sram_ctrl_max_throughput.4105722838	Mar 10 02:03:00 PM PDT 24	Mar 10 02:03:09 PM PDT 24	4528767040 ps
T240	/workspace/coverage/default/37.sram_ctrl_lc_escalation.2037612718	Mar 10 02:04:19 PM PDT 24	Mar 10 02:06:09 PM PDT 24	6330322287 ps
T241	/workspace/coverage/default/37.sram_ctrl_mem_walk.1320499557	Mar 10 02:04:24 PM PDT 24	Mar 10 02:08:23 PM PDT 24	8041050999 ps
T242	/workspace/coverage/default/22.sram_ctrl_lc_escalation.3147917487	Mar 10 02:02:14 PM PDT 24	Mar 10 02:06:02 PM PDT 24	18691807459 ps
T27	/workspace/coverage/default/1.sram_ctrl_sec_cm.395429618	Mar 10 02:00:37 PM PDT 24	Mar 10 02:00:40 PM PDT 24	591922007 ps
T38	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4276122035	Mar 10 02:05:13 PM PDT 24	Mar 10 02:05:46 PM PDT 24	2077468338 ps
T39	/workspace/coverage/default/39.sram_ctrl_max_throughput.1874023053	Mar 10 02:04:44 PM PDT 24	Mar 10 02:06:58 PM PDT 24	5454382478 ps
T40	/workspace/coverage/default/2.sram_ctrl_mem_walk.1313588364	Mar 10 02:00:33 PM PDT 24	Mar 10 02:02:36 PM PDT 24	2058682788 ps
T41	/workspace/coverage/default/5.sram_ctrl_lc_escalation.3683234780	Mar 10 02:00:45 PM PDT 24	Mar 10 02:01:52 PM PDT 24	5847801878 ps
T42	/workspace/coverage/default/33.sram_ctrl_smoke.3391516067	Mar 10 02:03:41 PM PDT 24	Mar 10 02:04:00 PM PDT 24	3879868250 ps
T43	/workspace/coverage/default/13.sram_ctrl_partial_access.3095830552	Mar 10 02:01:11 PM PDT 24	Mar 10 02:01:18 PM PDT 24	709103588 ps
T44	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1988409228	Mar 10 02:02:45 PM PDT 24	Mar 10 02:04:50 PM PDT 24	14772239702 ps
T45	/workspace/coverage/default/7.sram_ctrl_regwen.2809381998	Mar 10 02:00:46 PM PDT 24	Mar 10 02:01:54 PM PDT 24	2823671211 ps
T46	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1905019861	Mar 10 02:01:08 PM PDT 24	Mar 10 02:05:50 PM PDT 24	7108810740 ps
T243	/workspace/coverage/default/12.sram_ctrl_partial_access.1067629210	Mar 10 02:01:05 PM PDT 24	Mar 10 02:01:14 PM PDT 24	453242326 ps
T244	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.551908315	Mar 10 02:05:04 PM PDT 24	Mar 10 02:17:06 PM PDT 24	75005889945 ps
T245	/workspace/coverage/default/35.sram_ctrl_multiple_keys.3680693738	Mar 10 02:03:56 PM PDT 24	Mar 10 02:05:44 PM PDT 24	14169723026 ps
T246	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4227083285	Mar 10 02:00:28 PM PDT 24	Mar 10 02:10:31 PM PDT 24	3542396282 ps
T247	/workspace/coverage/default/49.sram_ctrl_max_throughput.2000752993	Mar 10 02:06:24 PM PDT 24	Mar 10 02:07:00 PM PDT 24	3392571889 ps
T248	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3703011071	Mar 10 02:06:30 PM PDT 24	Mar 10 02:07:32 PM PDT 24	1459605679 ps
T249	/workspace/coverage/default/9.sram_ctrl_regwen.4264036744	Mar 10 02:00:52 PM PDT 24	Mar 10 02:20:46 PM PDT 24	91687445306 ps
T250	/workspace/coverage/default/31.sram_ctrl_partial_access.1305320448	Mar 10 02:03:22 PM PDT 24	Mar 10 02:03:45 PM PDT 24	1838343630 ps
T251	/workspace/coverage/default/45.sram_ctrl_mem_walk.2205515935	Mar 10 02:05:45 PM PDT 24	Mar 10 02:08:19 PM PDT 24	41355300708 ps
T252	/workspace/coverage/default/8.sram_ctrl_max_throughput.1237269915	Mar 10 02:00:49 PM PDT 24	Mar 10 02:00:55 PM PDT 24	903324992 ps
T253	/workspace/coverage/default/13.sram_ctrl_multiple_keys.638967530	Mar 10 02:01:11 PM PDT 24	Mar 10 02:05:49 PM PDT 24	22364226793 ps
T254	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1380850518	Mar 10 02:00:28 PM PDT 24	Mar 10 02:01:43 PM PDT 24	1159888033 ps
T255	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2627714341	Mar 10 02:00:43 PM PDT 24	Mar 10 02:19:03 PM PDT 24	67322820777 ps
T256	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2194896147	Mar 10 02:05:10 PM PDT 24	Mar 10 02:10:39 PM PDT 24	28266449967 ps
T257	/workspace/coverage/default/37.sram_ctrl_ram_cfg.1651560829	Mar 10 02:04:25 PM PDT 24	Mar 10 02:04:28 PM PDT 24	350285251 ps
T258	/workspace/coverage/default/0.sram_ctrl_partial_access.2087597994	Mar 10 02:00:33 PM PDT 24	Mar 10 02:02:52 PM PDT 24	2002443113 ps
T259	/workspace/coverage/default/32.sram_ctrl_multiple_keys.644569968	Mar 10 02:03:35 PM PDT 24	Mar 10 02:15:54 PM PDT 24	2989831855 ps
T260	/workspace/coverage/default/37.sram_ctrl_smoke.2287204274	Mar 10 02:04:19 PM PDT 24	Mar 10 02:04:27 PM PDT 24	578180426 ps
T261	/workspace/coverage/default/16.sram_ctrl_alert_test.3698576183	Mar 10 02:01:31 PM PDT 24	Mar 10 02:01:32 PM PDT 24	12795640 ps
T262	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1527818322	Mar 10 02:04:40 PM PDT 24	Mar 10 02:04:52 PM PDT 24	610215631 ps
T263	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.120400995	Mar 10 02:00:52 PM PDT 24	Mar 10 02:07:02 PM PDT 24	34925455538 ps
T264	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3166985771	Mar 10 02:00:34 PM PDT 24	Mar 10 02:08:17 PM PDT 24	69594287174 ps
T265	/workspace/coverage/default/27.sram_ctrl_ram_cfg.1139465855	Mar 10 02:02:56 PM PDT 24	Mar 10 02:03:00 PM PDT 24	346771645 ps
T266	/workspace/coverage/default/41.sram_ctrl_partial_access.1456376644	Mar 10 02:05:01 PM PDT 24	Mar 10 02:05:32 PM PDT 24	688091738 ps
T267	/workspace/coverage/default/9.sram_ctrl_smoke.1998149972	Mar 10 02:00:48 PM PDT 24	Mar 10 02:01:04 PM PDT 24	2348309351 ps
T268	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1357145295	Mar 10 02:06:31 PM PDT 24	Mar 10 02:06:46 PM PDT 24	1930291829 ps
T269	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4262206740	Mar 10 02:02:46 PM PDT 24	Mar 10 02:04:47 PM PDT 24	796457242 ps
T270	/workspace/coverage/default/19.sram_ctrl_ram_cfg.2094283271	Mar 10 02:01:47 PM PDT 24	Mar 10 02:01:50 PM PDT 24	694449248 ps
T271	/workspace/coverage/default/29.sram_ctrl_smoke.2822090881	Mar 10 02:03:09 PM PDT 24	Mar 10 02:03:23 PM PDT 24	3623924523 ps
T272	/workspace/coverage/default/42.sram_ctrl_alert_test.2839628800	Mar 10 02:05:16 PM PDT 24	Mar 10 02:05:17 PM PDT 24	10444943 ps
T273	/workspace/coverage/default/14.sram_ctrl_smoke.1786463122	Mar 10 02:01:21 PM PDT 24	Mar 10 02:01:58 PM PDT 24	2868223092 ps
T274	/workspace/coverage/default/47.sram_ctrl_multiple_keys.782546695	Mar 10 02:06:07 PM PDT 24	Mar 10 02:07:23 PM PDT 24	6118028591 ps
T275	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.104151461	Mar 10 02:00:51 PM PDT 24	Mar 10 02:03:07 PM PDT 24	4889461324 ps
T276	/workspace/coverage/default/6.sram_ctrl_bijection.210287448	Mar 10 02:00:54 PM PDT 24	Mar 10 02:14:38 PM PDT 24	264797542041 ps
T277	/workspace/coverage/default/26.sram_ctrl_regwen.890398900	Mar 10 02:02:45 PM PDT 24	Mar 10 02:22:49 PM PDT 24	7900459375 ps
T278	/workspace/coverage/default/42.sram_ctrl_max_throughput.3037968701	Mar 10 02:05:11 PM PDT 24	Mar 10 02:06:26 PM PDT 24	1576411990 ps
T279	/workspace/coverage/default/39.sram_ctrl_ram_cfg.1304784400	Mar 10 02:04:47 PM PDT 24	Mar 10 02:04:50 PM PDT 24	361884239 ps
T280	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3235950533	Mar 10 02:05:08 PM PDT 24	Mar 10 02:06:29 PM PDT 24	4845042748 ps
T281	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.209847528	Mar 10 02:02:15 PM PDT 24	Mar 10 02:09:30 PM PDT 24	77052396045 ps
T282	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1911008267	Mar 10 02:01:52 PM PDT 24	Mar 10 02:03:31 PM PDT 24	1909534766 ps
T283	/workspace/coverage/default/5.sram_ctrl_bijection.2933012783	Mar 10 02:00:50 PM PDT 24	Mar 10 02:18:22 PM PDT 24	230797845531 ps
T284	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1294011518	Mar 10 02:01:23 PM PDT 24	Mar 10 02:02:14 PM PDT 24	3038712609 ps
T285	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.836801059	Mar 10 02:04:47 PM PDT 24	Mar 10 02:15:46 PM PDT 24	14863674396 ps
T286	/workspace/coverage/default/23.sram_ctrl_mem_walk.331842743	Mar 10 02:02:27 PM PDT 24	Mar 10 02:04:33 PM PDT 24	1977886366 ps
T287	/workspace/coverage/default/32.sram_ctrl_partial_access.610383673	Mar 10 02:03:33 PM PDT 24	Mar 10 02:03:48 PM PDT 24	984274094 ps
T288	/workspace/coverage/default/4.sram_ctrl_ram_cfg.2226731980	Mar 10 02:00:37 PM PDT 24	Mar 10 02:00:41 PM PDT 24	1414567606 ps
T289	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.835302613	Mar 10 02:03:04 PM PDT 24	Mar 10 02:03:44 PM PDT 24	2878614759 ps
T290	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3799758862	Mar 10 02:02:49 PM PDT 24	Mar 10 02:03:16 PM PDT 24	729468089 ps
T291	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1168025769	Mar 10 02:03:56 PM PDT 24	Mar 10 02:06:04 PM PDT 24	10333664065 ps
T292	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1329271969	Mar 10 02:00:36 PM PDT 24	Mar 10 02:02:33 PM PDT 24	783577425 ps
T293	/workspace/coverage/default/12.sram_ctrl_smoke.958239389	Mar 10 02:01:01 PM PDT 24	Mar 10 02:01:10 PM PDT 24	2788346167 ps
T294	/workspace/coverage/default/21.sram_ctrl_lc_escalation.1125944587	Mar 10 02:02:04 PM PDT 24	Mar 10 02:02:09 PM PDT 24	2520037118 ps
T295	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.308037851	Mar 10 02:04:16 PM PDT 24	Mar 10 02:07:21 PM PDT 24	3414098100 ps
T296	/workspace/coverage/default/46.sram_ctrl_bijection.2525858023	Mar 10 02:05:52 PM PDT 24	Mar 10 02:36:24 PM PDT 24	26568259534 ps
T297	/workspace/coverage/default/20.sram_ctrl_lc_escalation.4096881427	Mar 10 02:01:57 PM PDT 24	Mar 10 02:05:50 PM PDT 24	14627548328 ps
T298	/workspace/coverage/default/30.sram_ctrl_bijection.4257241360	Mar 10 02:03:19 PM PDT 24	Mar 10 02:49:25 PM PDT 24	118568115762 ps
T299	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.59534287	Mar 10 02:00:46 PM PDT 24	Mar 10 02:03:29 PM PDT 24	55416145166 ps
T300	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3503367387	Mar 10 02:00:49 PM PDT 24	Mar 10 02:11:39 PM PDT 24	27302451811 ps
T301	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3590819069	Mar 10 02:05:45 PM PDT 24	Mar 10 02:05:55 PM PDT 24	407362333 ps