Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	140695655	1			T2	1603		T3	163840		T4	891
triple_byte_access	2852848	1			T2	1555		T4	701		T5	2620
halfword_access	4371429	1			T2	2209		T4	1143		T5	3989
byte_access	6101000	1			T2	2922		T4	1500		T5	5233
zero_access	1833005	1			T2	718		T4	341		T5	1382

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77590376

1

T2

4459

T3

819200

T4

2340

auto[1]

78263561

1

T2

4548

T3

819200

T4

2236

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69883852	1			T2	805		T3	819200		T4	453
auto[0]	triple_byte_access	1361759	1			T2	775		T4	355		T5	1337
auto[0]	halfword_access	2137055	1			T2	1093		T4	583		T5	1987
auto[0]	byte_access	3119629	1			T2	1442		T4	781		T5	2588
auto[0]	zero_access	1088081	1			T2	344		T4	168		T5	662
auto[1]	word_access	70811803	1			T2	798		T3	819200		T4	438
auto[1]	triple_byte_access	1491089	1			T2	780		T4	346		T5	1283
auto[1]	halfword_access	2234374	1			T2	1116		T4	560		T5	2002
auto[1]	byte_access	2981371	1			T2	1480		T4	719		T5	2645
auto[1]	zero_access	744924	1			T2	374		T4	173		T5	720