Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	328758436	1			T1	275251		T2	252112		T3	211991
instr_valid_dis	284814280	1			T1	275251		T2	252112		T3	14650
instr_en	34930664	1			T3	10450		T4	195660		T12	57088

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10542680	1			T3	531294		T4	41034		T19	146970
sram_ifetch_valid_disable	283901152	1			T1	275251		T2	252112		T3	934592
sram_ifetch_enable	34314604	1			T3	654024		T4	165610		T12	53830

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	328758436	1			T1	275251		T2	252112		T3	211991
hw_debug_en_valid_off	291067052	1			T1	275251		T2	252112		T3	757568
hw_debug_en_on	23473898	1			T3	684918		T4	276786		T12	209606

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	283901152	1			T1	275251		T2	252112		T3	934592
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	268983868	1			T1	275251		T2	252112		T3	220
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11064934	1			T4	74636		T12	57088		T19	42770
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4053594	1			T3	209156		T4	23384		T19	69062
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1485636	1			T4	4690		T19	69062		T45	17178
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1700868	1			T83	96006		T44	73142		T46	19982
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4420218	1			T3	255080		T4	17650		T19	77908
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1856216	1			T4	17650		T19	77908		T83	50486
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1787740	1			T31	54126		T129	31130		T32	86726
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10098128	1			T3	195246		T4	135904		T12	158146
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3581530	1			T12	81058		T19	100930		T46	11830
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4764786	1			T4	62918		T12	57088		T44	8758

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	19438342	1			T3	10450		T4	121024		T83	141092
lc_exec_en	8955552	1			T3	234592		T4	123232		T12	51460
valid_exec_dis	281257064	1			T1	275251		T2	252112		T3	336208
invalid_exec_dis	44857284	1			T3	118531		T4	206644		T12	53830