Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.41 100.00 97.91 100.00 100.00 99.72 99.70 98.52


Total tests in report: 1022
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.92 82.92 97.85 97.85 77.96 77.96 83.98 83.98 71.43 71.43 91.55 91.55 94.95 94.95 62.71 62.71 /workspace/coverage/default/21.sram_ctrl_stress_all.3614063456
89.65 6.73 99.16 1.31 84.66 6.69 85.40 1.42 100.00 28.57 96.06 4.51 94.95 0.00 67.35 4.64 /workspace/coverage/default/37.sram_ctrl_stress_all.2217797884
95.25 5.60 99.53 0.37 91.63 6.97 96.34 10.94 100.00 0.00 96.90 0.85 96.29 1.34 86.09 18.74 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3682445687
96.54 1.28 99.91 0.37 94.98 3.35 97.27 0.92 100.00 0.00 99.72 2.82 96.88 0.59 87.01 0.93 /workspace/coverage/default/0.sram_ctrl_sec_cm.808819348
97.37 0.83 99.91 0.00 95.40 0.42 97.27 0.00 100.00 0.00 99.72 0.00 96.88 0.00 92.39 5.38 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2182273553
97.93 0.56 99.91 0.00 96.79 1.39 99.08 1.81 100.00 0.00 99.72 0.00 97.62 0.74 92.39 0.00 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3663615876
98.35 0.42 99.91 0.00 96.79 0.00 99.08 0.00 100.00 0.00 99.72 0.00 97.77 0.15 95.18 2.78 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2574722015
98.59 0.24 99.91 0.00 97.07 0.28 99.15 0.07 100.00 0.00 99.72 0.00 99.11 1.34 95.18 0.00 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.55898235
98.80 0.21 99.91 0.00 97.21 0.14 99.15 0.00 100.00 0.00 99.72 0.00 99.11 0.00 96.47 1.30 /workspace/coverage/default/16.sram_ctrl_stress_all.1383318439
98.96 0.17 99.91 0.00 97.21 0.00 99.15 0.00 100.00 0.00 99.72 0.00 99.55 0.45 97.22 0.74 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.488157494
99.08 0.11 100.00 0.09 97.21 0.00 99.86 0.71 100.00 0.00 99.72 0.00 99.55 0.00 97.22 0.00 /workspace/coverage/default/10.sram_ctrl_ram_cfg.3539060576
99.19 0.11 100.00 0.00 97.21 0.00 99.86 0.00 100.00 0.00 99.72 0.00 99.55 0.00 97.96 0.74 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1230306514
99.26 0.07 100.00 0.00 97.63 0.42 99.93 0.07 100.00 0.00 99.72 0.00 99.55 0.00 97.96 0.00 /workspace/coverage/default/12.sram_ctrl_alert_test.2865457745
99.29 0.04 100.00 0.00 97.63 0.00 100.00 0.07 100.00 0.00 99.72 0.00 99.55 0.00 98.14 0.19 /workspace/coverage/default/9.sram_ctrl_stress_all.4261769106
99.32 0.03 100.00 0.00 97.63 0.00 100.00 0.00 100.00 0.00 99.72 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1528081942
99.35 0.03 100.00 0.00 97.63 0.00 100.00 0.00 100.00 0.00 99.72 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.294393558
99.37 0.02 100.00 0.00 97.63 0.00 100.00 0.00 100.00 0.00 99.72 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2500136528

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1929277226
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2069839213
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.502406795
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1136407256
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3511825272
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1935535117
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3132972716
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.687931228
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2007509104
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3914119720
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2023842522
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2689511758
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1603011012
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.526635516
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2011935212
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3317888183
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1626183214
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1132936150
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.933094029
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3236877215
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4163599108
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2385679318
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2191735654
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.255523260
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4176549948
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4104562528
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3601173343
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1305610055
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1348420122
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2697189005
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2429957661
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2300707599
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.328523829
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3976638285
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.139948985
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1165230069
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.923708325
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3414371992
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1299686583
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1979361817
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2034007781
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3070394372
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3931049705
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3233167092
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.536226170
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3381403327
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.761134950
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2486227846
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2595490266
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3076922923
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2442428491
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2995145307
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.606654711
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3884932591
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.888149746
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.559040788
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.46710993
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2419307098
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.726730864
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.113730553
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1407409600
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1767028063
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2848786460
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1438467193
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1084626822
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.601605227
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2329108194
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1114461843
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3662506487
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.552676775
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1989080012
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1693493816
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2218489054
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2499610906
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2728648148
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3648545735
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.547291395
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.125389413
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3653959251
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3753210954
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2530533000
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.429598158
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2181983817
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1157922882
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4079086587
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.732663454
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3028949587
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1099065169
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.223279032
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1255882116
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2588631110
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2101092299
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2408049922
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1927375673
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3099622719
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3990607937
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2383118354
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3478232715
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2451732109
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1959223865
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.685601956
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2877478553
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1255166173
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4126650769
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2707608698
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1978142302
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2892426451
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2841761659
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4205271553
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.108700881
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1879527861
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1073993552
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3245664119
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3333295613
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2201348742
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2038311822
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.541728920
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2964506474
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1270307446
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3733355292
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3644193988
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1151907391
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.657317110
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4098925293
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3364811288
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.595905723
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.793543880
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3691585258
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.840141092
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1790190872
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.4215235697
/workspace/coverage/default/0.sram_ctrl_alert_test.579878818
/workspace/coverage/default/0.sram_ctrl_bijection.4113113542
/workspace/coverage/default/0.sram_ctrl_executable.324514326
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2192796016
/workspace/coverage/default/0.sram_ctrl_max_throughput.801197263
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1049278652
/workspace/coverage/default/0.sram_ctrl_mem_walk.2846531072
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3804220263
/workspace/coverage/default/0.sram_ctrl_partial_access.4120497472
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3092308010
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3643973719
/workspace/coverage/default/0.sram_ctrl_regwen.1603387092
/workspace/coverage/default/0.sram_ctrl_smoke.242114014
/workspace/coverage/default/0.sram_ctrl_stress_all.2249631563
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3613766124
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3949857254
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2330068283
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.651758115
/workspace/coverage/default/1.sram_ctrl_alert_test.648297611
/workspace/coverage/default/1.sram_ctrl_bijection.2920823460
/workspace/coverage/default/1.sram_ctrl_executable.2068123200
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2850933946
/workspace/coverage/default/1.sram_ctrl_max_throughput.1326807660
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.734635913
/workspace/coverage/default/1.sram_ctrl_mem_walk.2297618774
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2909372340
/workspace/coverage/default/1.sram_ctrl_partial_access.609981406
/workspace/coverage/default/1.sram_ctrl_ram_cfg.998925445
/workspace/coverage/default/1.sram_ctrl_regwen.3773339838
/workspace/coverage/default/1.sram_ctrl_sec_cm.1023315892
/workspace/coverage/default/1.sram_ctrl_smoke.129861933
/workspace/coverage/default/1.sram_ctrl_stress_all.1603261949
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.865893549
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1819603518
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.448127841
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3725503247
/workspace/coverage/default/10.sram_ctrl_alert_test.838370127
/workspace/coverage/default/10.sram_ctrl_bijection.258121641
/workspace/coverage/default/10.sram_ctrl_executable.2349434899
/workspace/coverage/default/10.sram_ctrl_lc_escalation.424795843
/workspace/coverage/default/10.sram_ctrl_max_throughput.4018625836
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.615534993
/workspace/coverage/default/10.sram_ctrl_mem_walk.1315017248
/workspace/coverage/default/10.sram_ctrl_multiple_keys.365089322
/workspace/coverage/default/10.sram_ctrl_partial_access.3835884258
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2646330254
/workspace/coverage/default/10.sram_ctrl_regwen.1935408513
/workspace/coverage/default/10.sram_ctrl_smoke.2903141182
/workspace/coverage/default/10.sram_ctrl_stress_all.3356392083
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1309397711
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3048379266
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3718361461
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2235831727
/workspace/coverage/default/11.sram_ctrl_alert_test.1190270866
/workspace/coverage/default/11.sram_ctrl_bijection.1064262704
/workspace/coverage/default/11.sram_ctrl_executable.2433614745
/workspace/coverage/default/11.sram_ctrl_lc_escalation.532168471
/workspace/coverage/default/11.sram_ctrl_max_throughput.4273522457
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2255599293
/workspace/coverage/default/11.sram_ctrl_mem_walk.3641113729
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3664623227
/workspace/coverage/default/11.sram_ctrl_partial_access.4131399503
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4050690322
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3043830000
/workspace/coverage/default/11.sram_ctrl_regwen.444902077
/workspace/coverage/default/11.sram_ctrl_smoke.2363531564
/workspace/coverage/default/11.sram_ctrl_stress_all.499762090
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1445991384
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2456836317
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1870370757
/workspace/coverage/default/12.sram_ctrl_bijection.11449724
/workspace/coverage/default/12.sram_ctrl_executable.3102957296
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3350061145
/workspace/coverage/default/12.sram_ctrl_max_throughput.2574241495
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1122597071
/workspace/coverage/default/12.sram_ctrl_mem_walk.3817660547
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3282360976
/workspace/coverage/default/12.sram_ctrl_partial_access.2126410439
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.900240663
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3552656080
/workspace/coverage/default/12.sram_ctrl_regwen.3509565166
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/workspace/coverage/default/43.sram_ctrl_regwen.3657322480
/workspace/coverage/default/43.sram_ctrl_smoke.2621660574
/workspace/coverage/default/43.sram_ctrl_stress_all.569831717
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3676371702
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3741234213
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4179711713
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.803601566
/workspace/coverage/default/44.sram_ctrl_alert_test.1644558610
/workspace/coverage/default/44.sram_ctrl_bijection.3275006524
/workspace/coverage/default/44.sram_ctrl_executable.42405663
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3143244730
/workspace/coverage/default/44.sram_ctrl_max_throughput.4198813650
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3162998608
/workspace/coverage/default/44.sram_ctrl_mem_walk.1098493684
/workspace/coverage/default/44.sram_ctrl_multiple_keys.336427842
/workspace/coverage/default/44.sram_ctrl_partial_access.3124017629
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2655892545
/workspace/coverage/default/44.sram_ctrl_ram_cfg.344665095
/workspace/coverage/default/44.sram_ctrl_smoke.1199366886
/workspace/coverage/default/44.sram_ctrl_stress_all.3989163258
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2233543141
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.950318028
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4247268120
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2643299437
/workspace/coverage/default/45.sram_ctrl_alert_test.1006776703
/workspace/coverage/default/45.sram_ctrl_bijection.1008382611
/workspace/coverage/default/45.sram_ctrl_executable.1573797786
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2153807154
/workspace/coverage/default/45.sram_ctrl_max_throughput.1446259501
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1048539082
/workspace/coverage/default/45.sram_ctrl_mem_walk.3757175204
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3303197095
/workspace/coverage/default/45.sram_ctrl_partial_access.3871626123
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3058896996
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3364937927
/workspace/coverage/default/45.sram_ctrl_regwen.1738830086
/workspace/coverage/default/45.sram_ctrl_smoke.2645486110
/workspace/coverage/default/45.sram_ctrl_stress_all.2678219090
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.920194694
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.86617086
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.809878770
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3411112961
/workspace/coverage/default/46.sram_ctrl_alert_test.1758829208
/workspace/coverage/default/46.sram_ctrl_bijection.2457863625
/workspace/coverage/default/46.sram_ctrl_executable.1811254993
/workspace/coverage/default/46.sram_ctrl_max_throughput.732059677
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3114939298
/workspace/coverage/default/46.sram_ctrl_mem_walk.2676320711
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3291027294
/workspace/coverage/default/46.sram_ctrl_partial_access.1261512868
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3092776370
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3554683825
/workspace/coverage/default/46.sram_ctrl_regwen.1759968427
/workspace/coverage/default/46.sram_ctrl_smoke.2949542746
/workspace/coverage/default/46.sram_ctrl_stress_all.3254047840
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3998084799
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2122820532
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3532821256
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.904443306
/workspace/coverage/default/47.sram_ctrl_alert_test.429366072
/workspace/coverage/default/47.sram_ctrl_bijection.2647951617
/workspace/coverage/default/47.sram_ctrl_executable.1126620350
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3077968276
/workspace/coverage/default/47.sram_ctrl_max_throughput.382627023
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.412383100
/workspace/coverage/default/47.sram_ctrl_mem_walk.2427633983
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4238878740
/workspace/coverage/default/47.sram_ctrl_partial_access.2951094741
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1951508348
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3592678879
/workspace/coverage/default/47.sram_ctrl_regwen.2524095904
/workspace/coverage/default/47.sram_ctrl_smoke.2364764172
/workspace/coverage/default/47.sram_ctrl_stress_all.1370699989
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3196235399
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.4066085905
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3883297311
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1612759586
/workspace/coverage/default/48.sram_ctrl_alert_test.4010046326
/workspace/coverage/default/48.sram_ctrl_bijection.560725669
/workspace/coverage/default/48.sram_ctrl_executable.1297410580
/workspace/coverage/default/48.sram_ctrl_lc_escalation.393226993
/workspace/coverage/default/48.sram_ctrl_max_throughput.1068997248
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1451780378
/workspace/coverage/default/48.sram_ctrl_mem_walk.3553130939
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3713131028
/workspace/coverage/default/48.sram_ctrl_partial_access.1351396169
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2360763885
/workspace/coverage/default/48.sram_ctrl_ram_cfg.736371185
/workspace/coverage/default/48.sram_ctrl_smoke.2364898872
/workspace/coverage/default/48.sram_ctrl_stress_all.305064044
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.119269177
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3561496020
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2923382885
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3582448531
/workspace/coverage/default/49.sram_ctrl_alert_test.3192362441
/workspace/coverage/default/49.sram_ctrl_bijection.642845425
/workspace/coverage/default/49.sram_ctrl_max_throughput.2661905797
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3647935633
/workspace/coverage/default/49.sram_ctrl_mem_walk.1680224950
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1204570824
/workspace/coverage/default/49.sram_ctrl_partial_access.741488182
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1869827691
/workspace/coverage/default/49.sram_ctrl_ram_cfg.327157990
/workspace/coverage/default/49.sram_ctrl_regwen.818463987
/workspace/coverage/default/49.sram_ctrl_smoke.2385325153
/workspace/coverage/default/49.sram_ctrl_stress_all.3307782691
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.507243079
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1425457825
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3369054134
/workspace/coverage/default/5.sram_ctrl_alert_test.364480879
/workspace/coverage/default/5.sram_ctrl_bijection.4180445201
/workspace/coverage/default/5.sram_ctrl_executable.3657091492
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3030351671
/workspace/coverage/default/5.sram_ctrl_max_throughput.1872581077
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3846546277
/workspace/coverage/default/5.sram_ctrl_mem_walk.621180869
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3346160363
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4270975085
/workspace/coverage/default/5.sram_ctrl_ram_cfg.657844727
/workspace/coverage/default/5.sram_ctrl_regwen.1933543421
/workspace/coverage/default/5.sram_ctrl_smoke.1547481060
/workspace/coverage/default/5.sram_ctrl_stress_all.2466713184
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1170389907
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4010485586
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1143981847
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3329200654
/workspace/coverage/default/6.sram_ctrl_alert_test.2555867059
/workspace/coverage/default/6.sram_ctrl_bijection.3413150396
/workspace/coverage/default/6.sram_ctrl_executable.3925077106
/workspace/coverage/default/6.sram_ctrl_lc_escalation.497911701
/workspace/coverage/default/6.sram_ctrl_max_throughput.2800978229
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2263948705
/workspace/coverage/default/6.sram_ctrl_mem_walk.1339997379
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1412098577
/workspace/coverage/default/6.sram_ctrl_partial_access.2228467521
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4100632397
/workspace/coverage/default/6.sram_ctrl_ram_cfg.711231182
/workspace/coverage/default/6.sram_ctrl_regwen.1509536117
/workspace/coverage/default/6.sram_ctrl_smoke.1290145386
/workspace/coverage/default/6.sram_ctrl_stress_all.2531310676
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1918323730
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2998850741
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4054053711
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3486178766
/workspace/coverage/default/7.sram_ctrl_alert_test.4036325129
/workspace/coverage/default/7.sram_ctrl_bijection.2201941985
/workspace/coverage/default/7.sram_ctrl_executable.2661366320
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1330801257
/workspace/coverage/default/7.sram_ctrl_max_throughput.3342821470
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1193198478
/workspace/coverage/default/7.sram_ctrl_mem_walk.2030867688
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4138891274
/workspace/coverage/default/7.sram_ctrl_partial_access.1299553268
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3223093868
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2043266677
/workspace/coverage/default/7.sram_ctrl_regwen.2966776202
/workspace/coverage/default/7.sram_ctrl_smoke.2277982495
/workspace/coverage/default/7.sram_ctrl_stress_all.1915074799
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1715597040
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1622083335
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.842512193
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2007942598
/workspace/coverage/default/8.sram_ctrl_alert_test.398667282
/workspace/coverage/default/8.sram_ctrl_bijection.719134764
/workspace/coverage/default/8.sram_ctrl_executable.1287026783
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3923672018
/workspace/coverage/default/8.sram_ctrl_max_throughput.900366905
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2817931023
/workspace/coverage/default/8.sram_ctrl_mem_walk.2545948932
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3517838511
/workspace/coverage/default/8.sram_ctrl_partial_access.2865377264
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3447787156
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2846246068
/workspace/coverage/default/8.sram_ctrl_regwen.885418567
/workspace/coverage/default/8.sram_ctrl_smoke.1484767852
/workspace/coverage/default/8.sram_ctrl_stress_all.2612358645
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2043699106
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2480151648
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3249290944
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2295834585
/workspace/coverage/default/9.sram_ctrl_alert_test.3812516706
/workspace/coverage/default/9.sram_ctrl_bijection.3402338590
/workspace/coverage/default/9.sram_ctrl_executable.2743530706
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2142372111
/workspace/coverage/default/9.sram_ctrl_max_throughput.2803200048
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.164835187
/workspace/coverage/default/9.sram_ctrl_mem_walk.350578451
/workspace/coverage/default/9.sram_ctrl_multiple_keys.714699997
/workspace/coverage/default/9.sram_ctrl_partial_access.4063659347
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2820619225
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2203992475
/workspace/coverage/default/9.sram_ctrl_regwen.1549662183
/workspace/coverage/default/9.sram_ctrl_smoke.3143679893
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3952533551
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1922618217
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1415156821



Total test records in report: 1022
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/25.sram_ctrl_bijection.2165531488 Mar 12 02:24:10 PM PDT 24 Mar 12 02:56:22 PM PDT 24 29475009854 ps
T2 /workspace/coverage/default/46.sram_ctrl_multiple_keys.3291027294 Mar 12 02:30:30 PM PDT 24 Mar 12 02:47:59 PM PDT 24 8312390468 ps
T3 /workspace/coverage/default/21.sram_ctrl_stress_all.3614063456 Mar 12 02:22:59 PM PDT 24 Mar 12 04:20:14 PM PDT 24 36899341785 ps
T4 /workspace/coverage/default/11.sram_ctrl_executable.2433614745 Mar 12 02:19:32 PM PDT 24 Mar 12 02:43:47 PM PDT 24 9970499329 ps
T10 /workspace/coverage/default/11.sram_ctrl_mem_walk.3641113729 Mar 12 02:19:41 PM PDT 24 Mar 12 02:25:08 PM PDT 24 71658407219 ps
T11 /workspace/coverage/default/38.sram_ctrl_max_throughput.1416889246 Mar 12 02:28:02 PM PDT 24 Mar 12 02:28:18 PM PDT 24 841452022 ps
T12 /workspace/coverage/default/39.sram_ctrl_executable.1181924496 Mar 12 02:28:23 PM PDT 24 Mar 12 02:36:24 PM PDT 24 43423234592 ps
T13 /workspace/coverage/default/8.sram_ctrl_mem_walk.2545948932 Mar 12 02:18:29 PM PDT 24 Mar 12 02:23:56 PM PDT 24 14036245360 ps
T14 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3663615876 Mar 12 02:28:51 PM PDT 24 Mar 12 02:39:32 PM PDT 24 13269082151 ps
T15 /workspace/coverage/default/1.sram_ctrl_bijection.2920823460 Mar 12 02:14:59 PM PDT 24 Mar 12 02:51:34 PM PDT 24 32135842741 ps
T19 /workspace/coverage/default/4.sram_ctrl_regwen.1492048652 Mar 12 02:16:29 PM PDT 24 Mar 12 02:29:52 PM PDT 24 5571236141 ps
T20 /workspace/coverage/default/13.sram_ctrl_smoke.1213481065 Mar 12 02:20:09 PM PDT 24 Mar 12 02:20:29 PM PDT 24 3894086955 ps
T21 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.236739733 Mar 12 02:15:30 PM PDT 24 Mar 12 02:15:53 PM PDT 24 1473091343 ps
T8 /workspace/coverage/default/0.sram_ctrl_sec_cm.808819348 Mar 12 02:14:47 PM PDT 24 Mar 12 02:14:51 PM PDT 24 653346199 ps
T22 /workspace/coverage/default/16.sram_ctrl_partial_access.744640465 Mar 12 02:21:20 PM PDT 24 Mar 12 02:21:36 PM PDT 24 1098646620 ps
T34 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3682445687 Mar 12 02:31:46 PM PDT 24 Mar 12 02:32:11 PM PDT 24 2653214297 ps
T18 /workspace/coverage/default/5.sram_ctrl_mem_walk.621180869 Mar 12 02:17:08 PM PDT 24 Mar 12 02:22:46 PM PDT 24 74648100680 ps
T26 /workspace/coverage/default/46.sram_ctrl_alert_test.1758829208 Mar 12 02:30:47 PM PDT 24 Mar 12 02:30:49 PM PDT 24 14587320 ps
T23 /workspace/coverage/default/10.sram_ctrl_smoke.2903141182 Mar 12 02:18:57 PM PDT 24 Mar 12 02:19:12 PM PDT 24 2163158751 ps
T16 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2574722015 Mar 12 02:14:59 PM PDT 24 Mar 12 02:18:40 PM PDT 24 42222321264 ps
T17 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4049382993 Mar 12 02:29:09 PM PDT 24 Mar 12 02:38:01 PM PDT 24 116713175874 ps
T42 /workspace/coverage/default/11.sram_ctrl_bijection.1064262704 Mar 12 02:19:21 PM PDT 24 Mar 12 02:30:28 PM PDT 24 434333933594 ps
T43 /workspace/coverage/default/29.sram_ctrl_multiple_keys.3343759473 Mar 12 02:25:14 PM PDT 24 Mar 12 02:48:14 PM PDT 24 54181509576 ps
T54 /workspace/coverage/default/17.sram_ctrl_smoke.2308713259 Mar 12 02:21:30 PM PDT 24 Mar 12 02:21:46 PM PDT 24 1027676796 ps
T55 /workspace/coverage/default/5.sram_ctrl_max_throughput.1872581077 Mar 12 02:16:56 PM PDT 24 Mar 12 02:17:07 PM PDT 24 705274183 ps
T90 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.228745153 Mar 12 02:28:45 PM PDT 24 Mar 12 02:36:25 PM PDT 24 19007342721 ps
T24 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.68568918 Mar 12 02:23:41 PM PDT 24 Mar 12 02:30:10 PM PDT 24 6240740096 ps
T83 /workspace/coverage/default/25.sram_ctrl_executable.3416065125 Mar 12 02:24:17 PM PDT 24 Mar 12 02:42:59 PM PDT 24 57568842405 ps
T5 /workspace/coverage/default/36.sram_ctrl_lc_escalation.3405510077 Mar 12 02:27:31 PM PDT 24 Mar 12 02:27:55 PM PDT 24 4087013509 ps
T84 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3705187133 Mar 12 02:25:03 PM PDT 24 Mar 12 02:25:23 PM PDT 24 1494604716 ps
T85 /workspace/coverage/default/28.sram_ctrl_partial_access.2809664653 Mar 12 02:25:02 PM PDT 24 Mar 12 02:27:25 PM PDT 24 5398442131 ps
T37 /workspace/coverage/default/38.sram_ctrl_ram_cfg.1991193843 Mar 12 02:28:26 PM PDT 24 Mar 12 02:28:29 PM PDT 24 1206195009 ps
T44 /workspace/coverage/default/1.sram_ctrl_stress_all.1603261949 Mar 12 02:15:16 PM PDT 24 Mar 12 04:10:48 PM PDT 24 278961800358 ps
T35 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2733151552 Mar 12 02:16:03 PM PDT 24 Mar 12 02:16:19 PM PDT 24 461918559 ps
T27 /workspace/coverage/default/43.sram_ctrl_alert_test.2502714033 Mar 12 02:29:48 PM PDT 24 Mar 12 02:29:48 PM PDT 24 50418777 ps
T86 /workspace/coverage/default/47.sram_ctrl_multiple_keys.4238878740 Mar 12 02:30:54 PM PDT 24 Mar 12 02:38:12 PM PDT 24 27142234005 ps
T94 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1869827691 Mar 12 02:31:37 PM PDT 24 Mar 12 02:38:48 PM PDT 24 34502957142 ps
T132 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3201875891 Mar 12 02:20:45 PM PDT 24 Mar 12 02:21:56 PM PDT 24 1176896300 ps
T45 /workspace/coverage/default/32.sram_ctrl_executable.1782730459 Mar 12 02:26:25 PM PDT 24 Mar 12 02:41:50 PM PDT 24 241651278677 ps
T46 /workspace/coverage/default/0.sram_ctrl_regwen.1603387092 Mar 12 02:14:37 PM PDT 24 Mar 12 02:27:35 PM PDT 24 8795321126 ps
T133 /workspace/coverage/default/14.sram_ctrl_mem_walk.4142098394 Mar 12 02:20:48 PM PDT 24 Mar 12 02:23:20 PM PDT 24 17970943335 ps
T134 /workspace/coverage/default/29.sram_ctrl_max_throughput.2027688393 Mar 12 02:25:28 PM PDT 24 Mar 12 02:26:53 PM PDT 24 3112524674 ps
T135 /workspace/coverage/default/49.sram_ctrl_bijection.642845425 Mar 12 02:31:27 PM PDT 24 Mar 12 02:48:13 PM PDT 24 62274143673 ps
T95 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4238100106 Mar 12 02:28:04 PM PDT 24 Mar 12 02:34:24 PM PDT 24 111818055846 ps
T130 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3290840332 Mar 12 02:24:55 PM PDT 24 Mar 12 02:37:06 PM PDT 24 12029266778 ps
T38 /workspace/coverage/default/35.sram_ctrl_ram_cfg.1869707605 Mar 12 02:27:23 PM PDT 24 Mar 12 02:27:28 PM PDT 24 1972393703 ps
T36 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.9982232 Mar 12 02:24:47 PM PDT 24 Mar 12 02:27:23 PM PDT 24 9165996131 ps
T136 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.842512193 Mar 12 02:17:57 PM PDT 24 Mar 12 02:18:41 PM PDT 24 1510283396 ps
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T28 /workspace/coverage/default/23.sram_ctrl_alert_test.3772180876 Mar 12 02:23:47 PM PDT 24 Mar 12 02:23:48 PM PDT 24 44575920 ps
T138 /workspace/coverage/default/37.sram_ctrl_bijection.3878631352 Mar 12 02:28:23 PM PDT 24 Mar 12 03:01:48 PM PDT 24 424812321328 ps
T139 /workspace/coverage/default/25.sram_ctrl_max_throughput.3048161240 Mar 12 02:24:17 PM PDT 24 Mar 12 02:24:31 PM PDT 24 2762834892 ps
T140 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.692318427 Mar 12 02:21:23 PM PDT 24 Mar 12 02:21:56 PM PDT 24 2274997172 ps
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T96 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2169883913 Mar 12 02:22:48 PM PDT 24 Mar 12 02:30:24 PM PDT 24 102822963272 ps
T97 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1622367629 Mar 12 02:26:05 PM PDT 24 Mar 12 02:34:05 PM PDT 24 70649443725 ps
T47 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.488157494 Mar 12 02:19:42 PM PDT 24 Mar 12 02:20:01 PM PDT 24 821493627 ps
T114 /workspace/coverage/default/16.sram_ctrl_mem_walk.775697278 Mar 12 02:21:21 PM PDT 24 Mar 12 02:26:45 PM PDT 24 21505977116 ps
T98 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4066085905 Mar 12 02:30:59 PM PDT 24 Mar 12 02:36:01 PM PDT 24 21808829488 ps
T9 /workspace/coverage/default/15.sram_ctrl_lc_escalation.3989427836 Mar 12 02:21:11 PM PDT 24 Mar 12 02:21:30 PM PDT 24 15637249919 ps
T39 /workspace/coverage/default/48.sram_ctrl_ram_cfg.736371185 Mar 12 02:31:17 PM PDT 24 Mar 12 02:31:20 PM PDT 24 711937656 ps
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T115 /workspace/coverage/default/47.sram_ctrl_partial_access.2951094741 Mar 12 02:30:59 PM PDT 24 Mar 12 02:32:12 PM PDT 24 1151110070 ps
T116 /workspace/coverage/default/4.sram_ctrl_multiple_keys.3624002865 Mar 12 02:16:20 PM PDT 24 Mar 12 02:25:01 PM PDT 24 25724316755 ps
T56 /workspace/coverage/default/8.sram_ctrl_regwen.885418567 Mar 12 02:18:21 PM PDT 24 Mar 12 02:29:01 PM PDT 24 50515027003 ps
T25 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2500136528 Mar 12 02:21:58 PM PDT 24 Mar 12 02:42:20 PM PDT 24 10613517760 ps
T73 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2007942598 Mar 12 02:18:21 PM PDT 24 Mar 12 02:18:55 PM PDT 24 1383065482 ps
T99 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2493728058 Mar 12 02:22:34 PM PDT 24 Mar 12 02:25:45 PM PDT 24 4601023326 ps
T74 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3846546277 Mar 12 02:17:07 PM PDT 24 Mar 12 02:18:43 PM PDT 24 37837680478 ps
T141 /workspace/coverage/default/48.sram_ctrl_partial_access.1351396169 Mar 12 02:31:11 PM PDT 24 Mar 12 02:31:35 PM PDT 24 630290818 ps
T142 /workspace/coverage/default/25.sram_ctrl_ram_cfg.4150547131 Mar 12 02:24:16 PM PDT 24 Mar 12 02:24:20 PM PDT 24 1349986404 ps
T143 /workspace/coverage/default/34.sram_ctrl_bijection.1106705530 Mar 12 02:26:52 PM PDT 24 Mar 12 02:35:42 PM PDT 24 97008821266 ps
T144 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2360197102 Mar 12 02:26:24 PM PDT 24 Mar 12 02:26:31 PM PDT 24 1395490746 ps
T75 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.803601566 Mar 12 02:29:59 PM PDT 24 Mar 12 02:52:22 PM PDT 24 19464366238 ps
T145 /workspace/coverage/default/7.sram_ctrl_smoke.2277982495 Mar 12 02:17:50 PM PDT 24 Mar 12 02:18:01 PM PDT 24 939690091 ps
T100 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.4212448818 Mar 12 02:20:36 PM PDT 24 Mar 12 02:23:59 PM PDT 24 3945933954 ps
T146 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.448127841 Mar 12 02:15:12 PM PDT 24 Mar 12 02:16:21 PM PDT 24 770447042 ps
T147 /workspace/coverage/default/26.sram_ctrl_max_throughput.3459348683 Mar 12 02:24:32 PM PDT 24 Mar 12 02:25:48 PM PDT 24 4065457351 ps
T57 /workspace/coverage/default/9.sram_ctrl_stress_all.4261769106 Mar 12 02:19:00 PM PDT 24 Mar 12 02:48:12 PM PDT 24 54241265988 ps
T148 /workspace/coverage/default/3.sram_ctrl_ram_cfg.1752229146 Mar 12 02:16:05 PM PDT 24 Mar 12 02:16:09 PM PDT 24 1404324250 ps
T149 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2318625222 Mar 12 02:21:36 PM PDT 24 Mar 12 02:21:46 PM PDT 24 2874866964 ps
T150 /workspace/coverage/default/31.sram_ctrl_smoke.4059100661 Mar 12 02:26:02 PM PDT 24 Mar 12 02:26:50 PM PDT 24 1629569160 ps
T48 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1812374962 Mar 12 02:29:30 PM PDT 24 Mar 12 02:30:07 PM PDT 24 9004538254 ps
T151 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1819603518 Mar 12 02:14:58 PM PDT 24 Mar 12 02:20:52 PM PDT 24 6584938291 ps
T152 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2051982630 Mar 12 02:21:10 PM PDT 24 Mar 12 02:21:19 PM PDT 24 1384720551 ps
T153 /workspace/coverage/default/23.sram_ctrl_multiple_keys.3867904398 Mar 12 02:23:26 PM PDT 24 Mar 12 02:33:30 PM PDT 24 5585328609 ps
T154 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2367018129 Mar 12 02:24:31 PM PDT 24 Mar 12 02:31:28 PM PDT 24 58102303724 ps
T76 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1451780378 Mar 12 02:31:22 PM PDT 24 Mar 12 02:33:43 PM PDT 24 1568690479 ps
T7 /workspace/coverage/default/11.sram_ctrl_stress_all.499762090 Mar 12 02:19:42 PM PDT 24 Mar 12 03:22:07 PM PDT 24 32202057788 ps
T155 /workspace/coverage/default/1.sram_ctrl_max_throughput.1326807660 Mar 12 02:15:09 PM PDT 24 Mar 12 02:15:28 PM PDT 24 2483056746 ps
T77 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3791439802 Mar 12 02:27:23 PM PDT 24 Mar 12 02:43:07 PM PDT 24 31501349750 ps
T31 /workspace/coverage/default/16.sram_ctrl_stress_all.1383318439 Mar 12 02:21:20 PM PDT 24 Mar 12 03:38:51 PM PDT 24 47024014451 ps
T156 /workspace/coverage/default/8.sram_ctrl_partial_access.2865377264 Mar 12 02:18:22 PM PDT 24 Mar 12 02:18:46 PM PDT 24 4292465967 ps
T157 /workspace/coverage/default/8.sram_ctrl_bijection.719134764 Mar 12 02:18:13 PM PDT 24 Mar 12 02:41:31 PM PDT 24 62504082127 ps
T129 /workspace/coverage/default/19.sram_ctrl_executable.3583345187 Mar 12 02:22:27 PM PDT 24 Mar 12 02:34:36 PM PDT 24 39921507815 ps
T158 /workspace/coverage/default/48.sram_ctrl_executable.1297410580 Mar 12 02:31:17 PM PDT 24 Mar 12 02:52:44 PM PDT 24 26740399627 ps
T32 /workspace/coverage/default/18.sram_ctrl_stress_all.655837218 Mar 12 02:22:09 PM PDT 24 Mar 12 03:16:53 PM PDT 24 60708275486 ps
T159 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1581441695 Mar 12 02:21:20 PM PDT 24 Mar 12 02:28:44 PM PDT 24 17798738413 ps
T160 /workspace/coverage/default/16.sram_ctrl_regwen.1137712592 Mar 12 02:21:20 PM PDT 24 Mar 12 02:31:33 PM PDT 24 44589980896 ps
T78 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1999728061 Mar 12 02:26:45 PM PDT 24 Mar 12 02:29:12 PM PDT 24 18931939784 ps
T161 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3807058576 Mar 12 02:25:48 PM PDT 24 Mar 12 02:31:19 PM PDT 24 84230018249 ps
T162 /workspace/coverage/default/5.sram_ctrl_multiple_keys.3346160363 Mar 12 02:16:45 PM PDT 24 Mar 12 02:17:40 PM PDT 24 3562007904 ps
T163 /workspace/coverage/default/36.sram_ctrl_max_throughput.4009654815 Mar 12 02:27:31 PM PDT 24 Mar 12 02:29:25 PM PDT 24 781121377 ps
T164 /workspace/coverage/default/29.sram_ctrl_partial_access.4133120192 Mar 12 02:25:27 PM PDT 24 Mar 12 02:25:51 PM PDT 24 1492008173 ps
T165 /workspace/coverage/default/10.sram_ctrl_ram_cfg.3539060576 Mar 12 02:19:21 PM PDT 24 Mar 12 02:19:24 PM PDT 24 1420842327 ps
T29 /workspace/coverage/default/1.sram_ctrl_sec_cm.1023315892 Mar 12 02:15:15 PM PDT 24 Mar 12 02:15:18 PM PDT 24 804200678 ps
T166 /workspace/coverage/default/0.sram_ctrl_partial_access.4120497472 Mar 12 02:14:30 PM PDT 24 Mar 12 02:15:33 PM PDT 24 1235846807 ps
T167 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1539158909 Mar 12 02:28:16 PM PDT 24 Mar 12 02:39:29 PM PDT 24 38620025184 ps
T79 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2774435753 Mar 12 02:23:21 PM PDT 24 Mar 12 02:35:18 PM PDT 24 93388470928 ps
T168 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2646330254 Mar 12 02:19:09 PM PDT 24 Mar 12 02:22:52 PM PDT 24 8728972111 ps
T49 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3002887094 Mar 12 02:28:36 PM PDT 24 Mar 12 02:28:50 PM PDT 24 1754039968 ps
T50 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2515462139 Mar 12 02:20:52 PM PDT 24 Mar 12 02:21:14 PM PDT 24 2905306101 ps
T169 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1244036681 Mar 12 02:27:30 PM PDT 24 Mar 12 02:27:36 PM PDT 24 1290243973 ps
T170 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4179711713 Mar 12 02:29:35 PM PDT 24 Mar 12 02:30:12 PM PDT 24 2685239315 ps
T171 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3713816357 Mar 12 02:27:07 PM PDT 24 Mar 12 02:27:11 PM PDT 24 2392263001 ps
T172 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1415156821 Mar 12 02:18:44 PM PDT 24 Mar 12 02:18:57 PM PDT 24 727069382 ps
T87 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.4118174655 Mar 12 02:28:03 PM PDT 24 Mar 12 02:46:40 PM PDT 24 95411444343 ps
T173 /workspace/coverage/default/43.sram_ctrl_ram_cfg.2406123448 Mar 12 02:29:49 PM PDT 24 Mar 12 02:29:52 PM PDT 24 1352776721 ps
T174 /workspace/coverage/default/28.sram_ctrl_mem_walk.3973726683 Mar 12 02:25:13 PM PDT 24 Mar 12 02:27:17 PM PDT 24 14097256496 ps
T175 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.969430859 Mar 12 02:25:28 PM PDT 24 Mar 12 02:29:50 PM PDT 24 14242712623 ps
T176 /workspace/coverage/default/3.sram_ctrl_multiple_keys.2991692264 Mar 12 02:15:51 PM PDT 24 Mar 12 02:29:19 PM PDT 24 41557959314 ps
T177 /workspace/coverage/default/13.sram_ctrl_mem_walk.1340866672 Mar 12 02:20:23 PM PDT 24 Mar 12 02:25:52 PM PDT 24 71238786145 ps
T178 /workspace/coverage/default/7.sram_ctrl_stress_all.1915074799 Mar 12 02:18:06 PM PDT 24 Mar 12 03:18:54 PM PDT 24 32310385615 ps
T33 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2425085772 Mar 12 02:20:46 PM PDT 24 Mar 12 02:22:09 PM PDT 24 260853939291 ps
T51 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2043699106 Mar 12 02:18:28 PM PDT 24 Mar 12 02:18:46 PM PDT 24 1222159937 ps
T179 /workspace/coverage/default/19.sram_ctrl_lc_escalation.528359830 Mar 12 02:22:18 PM PDT 24 Mar 12 02:23:21 PM PDT 24 10263928681 ps
T180 /workspace/coverage/default/44.sram_ctrl_lc_escalation.3143244730 Mar 12 02:29:57 PM PDT 24 Mar 12 02:31:31 PM PDT 24 66796754710 ps
T181 /workspace/coverage/default/17.sram_ctrl_partial_access.2604221754 Mar 12 02:21:37 PM PDT 24 Mar 12 02:21:54 PM PDT 24 14133888045 ps
T88 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3162998608 Mar 12 02:30:11 PM PDT 24 Mar 12 02:32:54 PM PDT 24 4558241955 ps
T182 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1907295352 Mar 12 02:26:39 PM PDT 24 Mar 12 02:29:31 PM PDT 24 819044007 ps
T183 /workspace/coverage/default/14.sram_ctrl_regwen.2668660399 Mar 12 02:20:43 PM PDT 24 Mar 12 02:33:43 PM PDT 24 1630341688 ps
T89 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1856798759 Mar 12 02:22:25 PM PDT 24 Mar 12 02:25:07 PM PDT 24 17490281681 ps
T184 /workspace/coverage/default/10.sram_ctrl_stress_all.3356392083 Mar 12 02:19:21 PM PDT 24 Mar 12 02:40:17 PM PDT 24 60041980371 ps
T185 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1134780155 Mar 12 02:22:35 PM PDT 24 Mar 12 02:24:07 PM PDT 24 3131109950 ps
T52 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3534818158 Mar 12 02:23:00 PM PDT 24 Mar 12 02:23:49 PM PDT 24 4182508738 ps
T186 /workspace/coverage/default/48.sram_ctrl_max_throughput.1068997248 Mar 12 02:31:08 PM PDT 24 Mar 12 02:33:21 PM PDT 24 811981365 ps
T187 /workspace/coverage/default/45.sram_ctrl_partial_access.3871626123 Mar 12 02:30:20 PM PDT 24 Mar 12 02:30:41 PM PDT 24 1369926074 ps
T53 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.671737021 Mar 12 02:27:11 PM PDT 24 Mar 12 02:30:30 PM PDT 24 4160389956 ps
T188 /workspace/coverage/default/44.sram_ctrl_smoke.1199366886 Mar 12 02:29:45 PM PDT 24 Mar 12 02:32:14 PM PDT 24 925295443 ps
T189 /workspace/coverage/default/31.sram_ctrl_regwen.3437538916 Mar 12 02:26:13 PM PDT 24 Mar 12 02:39:35 PM PDT 24 12313520459 ps
T190 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.950318028 Mar 12 02:29:51 PM PDT 24 Mar 12 02:33:04 PM PDT 24 33053651180 ps
T191 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.86617086 Mar 12 02:30:22 PM PDT 24 Mar 12 02:34:20 PM PDT 24 3921130364 ps
T192 /workspace/coverage/default/32.sram_ctrl_smoke.1991895367 Mar 12 02:26:20 PM PDT 24 Mar 12 02:26:26 PM PDT 24 2116958603 ps
T193 /workspace/coverage/default/42.sram_ctrl_regwen.1698866319 Mar 12 02:29:24 PM PDT 24 Mar 12 02:41:42 PM PDT 24 2440248185 ps
T194 /workspace/coverage/default/22.sram_ctrl_lc_escalation.1766260663 Mar 12 02:23:17 PM PDT 24 Mar 12 02:25:03 PM PDT 24 88295280102 ps
T195 /workspace/coverage/default/13.sram_ctrl_ram_cfg.1368950958 Mar 12 02:20:24 PM PDT 24 Mar 12 02:20:27 PM PDT 24 679467137 ps
T196 /workspace/coverage/default/24.sram_ctrl_multiple_keys.4276318757 Mar 12 02:23:55 PM PDT 24 Mar 12 02:30:41 PM PDT 24 6221462823 ps
T197 /workspace/coverage/default/30.sram_ctrl_bijection.4031435431 Mar 12 02:25:41 PM PDT 24 Mar 12 03:02:56 PM PDT 24 123488233395 ps
T198 /workspace/coverage/default/17.sram_ctrl_regwen.1475838447 Mar 12 02:21:37 PM PDT 24 Mar 12 02:40:34 PM PDT 24 39012012904 ps
T199 /workspace/coverage/default/37.sram_ctrl_mem_walk.3982912510 Mar 12 02:28:02 PM PDT 24 Mar 12 02:32:38 PM PDT 24 27582043401 ps
T200 /workspace/coverage/default/8.sram_ctrl_executable.1287026783 Mar 12 02:18:21 PM PDT 24 Mar 12 02:33:43 PM PDT 24 44184866476 ps
T201 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2715911404 Mar 12 02:26:37 PM PDT 24 Mar 12 02:32:12 PM PDT 24 12572938409 ps
T202 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3362976888 Mar 12 02:21:12 PM PDT 24 Mar 12 02:21:41 PM PDT 24 789297935 ps
T203 /workspace/coverage/default/47.sram_ctrl_smoke.2364764172 Mar 12 02:30:56 PM PDT 24 Mar 12 02:31:07 PM PDT 24 3469079094 ps
T204 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3668496425 Mar 12 02:25:28 PM PDT 24 Mar 12 02:26:44 PM PDT 24 852647804 ps
T205 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3829754713 Mar 12 02:15:32 PM PDT 24 Mar 12 02:19:02 PM PDT 24 2052579239 ps
T206 /workspace/coverage/default/34.sram_ctrl_mem_walk.2533384561 Mar 12 02:27:09 PM PDT 24 Mar 12 02:29:54 PM PDT 24 39757815579 ps
T207 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3249290944 Mar 12 02:18:22 PM PDT 24 Mar 12 02:18:31 PM PDT 24 699288366 ps
T208 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2230034435 Mar 12 02:24:23 PM PDT 24 Mar 12 02:29:47 PM PDT 24 21328168829 ps
T209 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.562509098 Mar 12 02:21:01 PM PDT 24 Mar 12 02:26:59 PM PDT 24 6349825132 ps
T210 /workspace/coverage/default/26.sram_ctrl_multiple_keys.270628031 Mar 12 02:24:23 PM PDT 24 Mar 12 02:27:19 PM PDT 24 12185657780 ps
T211 /workspace/coverage/default/30.sram_ctrl_smoke.3602961629 Mar 12 02:25:40 PM PDT 24 Mar 12 02:26:11 PM PDT 24 667422722 ps
T212 /workspace/coverage/default/36.sram_ctrl_smoke.315099589 Mar 12 02:27:40 PM PDT 24 Mar 12 02:27:57 PM PDT 24 1774015315 ps
T213 /workspace/coverage/default/6.sram_ctrl_stress_all.2531310676 Mar 12 02:17:50 PM PDT 24 Mar 12 03:13:07 PM PDT 24 325738814427 ps
T214 /workspace/coverage/default/38.sram_ctrl_bijection.1773293314 Mar 12 02:28:03 PM PDT 24 Mar 12 02:57:13 PM PDT 24 26300995503 ps
T215 /workspace/coverage/default/25.sram_ctrl_stress_all.2157669149 Mar 12 02:24:23 PM PDT 24 Mar 12 02:58:43 PM PDT 24 12611048594 ps
T216 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.266351192 Mar 12 02:26:22 PM PDT 24 Mar 12 02:41:37 PM PDT 24 15107972602 ps
T217 /workspace/coverage/default/2.sram_ctrl_regwen.2296503850 Mar 12 02:15:42 PM PDT 24 Mar 12 02:33:47 PM PDT 24 99316304560 ps
T218 /workspace/coverage/default/49.sram_ctrl_mem_walk.1680224950 Mar 12 02:31:37 PM PDT 24 Mar 12 02:36:24 PM PDT 24 72431566077 ps
T219 /workspace/coverage/default/18.sram_ctrl_executable.1892116088 Mar 12 02:22:02 PM PDT 24 Mar 12 02:23:17 PM PDT 24 2820894381 ps
T220 /workspace/coverage/default/22.sram_ctrl_max_throughput.226717663 Mar 12 02:23:20 PM PDT 24 Mar 12 02:25:24 PM PDT 24 768499321 ps
T221 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3741034054 Mar 12 02:28:11 PM PDT 24 Mar 12 02:28:17 PM PDT 24 715887552 ps
T222 /workspace/coverage/default/11.sram_ctrl_max_throughput.4273522457 Mar 12 02:19:32 PM PDT 24 Mar 12 02:21:06 PM PDT 24 831171659 ps
T223 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.4180685810 Mar 12 02:27:23 PM PDT 24 Mar 12 02:28:46 PM PDT 24 2447971682 ps
T224 /workspace/coverage/default/42.sram_ctrl_bijection.1519222502 Mar 12 02:29:21 PM PDT 24 Mar 12 02:47:06 PM PDT 24 16768376919 ps
T225 /workspace/coverage/default/23.sram_ctrl_partial_access.1910062968 Mar 12 02:23:34 PM PDT 24 Mar 12 02:23:57 PM PDT 24 1420770504 ps
T226 /workspace/coverage/default/23.sram_ctrl_regwen.3833237204 Mar 12 02:23:40 PM PDT 24 Mar 12 02:58:44 PM PDT 24 17409722860 ps
T227 /workspace/coverage/default/41.sram_ctrl_executable.2727692771 Mar 12 02:29:08 PM PDT 24 Mar 12 02:33:21 PM PDT 24 13373219031 ps
T228 /workspace/coverage/default/12.sram_ctrl_alert_test.2865457745 Mar 12 02:20:09 PM PDT 24 Mar 12 02:20:10 PM PDT 24 49215169 ps
T229 /workspace/coverage/default/35.sram_ctrl_executable.3951751706 Mar 12 02:27:23 PM PDT 24 Mar 12 02:42:01 PM PDT 24 30097482270 ps
T230 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1770493449 Mar 12 02:27:14 PM PDT 24 Mar 12 02:32:03 PM PDT 24 8331701945 ps
T231 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3345235165 Mar 12 02:15:52 PM PDT 24 Mar 12 02:15:56 PM PDT 24 2795144251 ps
T232 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2124070767 Mar 12 02:20:51 PM PDT 24 Mar 12 02:23:18 PM PDT 24 5295632583 ps
T233 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1346758264 Mar 12 02:25:14 PM PDT 24 Mar 12 02:25:28 PM PDT 24 1250485470 ps
T234 /workspace/coverage/default/1.sram_ctrl_executable.2068123200 Mar 12 02:15:09 PM PDT 24 Mar 12 02:45:43 PM PDT 24 9813313398 ps
T235 /workspace/coverage/default/24.sram_ctrl_bijection.1116507645 Mar 12 02:23:55 PM PDT 24 Mar 12 02:49:25 PM PDT 24 22854806006 ps
T236 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2617201586 Mar 12 02:29:19 PM PDT 24 Mar 12 02:29:50 PM PDT 24 4526884705 ps
T106 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.865893549 Mar 12 02:15:15 PM PDT 24 Mar 12 02:16:51 PM PDT 24 15174882938 ps
T237 /workspace/coverage/default/41.sram_ctrl_alert_test.3856679908 Mar 12 02:29:14 PM PDT 24 Mar 12 02:29:16 PM PDT 24 15313362 ps
T238 /workspace/coverage/default/17.sram_ctrl_max_throughput.3924884626 Mar 12 02:21:39 PM PDT 24 Mar 12 02:22:16 PM PDT 24 3010495850 ps
T239 /workspace/coverage/default/7.sram_ctrl_mem_walk.2030867688 Mar 12 02:18:05 PM PDT 24 Mar 12 02:22:14 PM PDT 24 15763668557 ps
T240 /workspace/coverage/default/46.sram_ctrl_partial_access.1261512868 Mar 12 02:30:36 PM PDT 24 Mar 12 02:31:28 PM PDT 24 1578666073 ps
T241 /workspace/coverage/default/40.sram_ctrl_mem_walk.2919515706 Mar 12 02:28:58 PM PDT 24 Mar 12 02:33:41 PM PDT 24 13909401068 ps
T242 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1106792857 Mar 12 02:28:15 PM PDT 24 Mar 12 02:31:44 PM PDT 24 3294094048 ps
T30 /workspace/coverage/default/3.sram_ctrl_sec_cm.226461796 Mar 12 02:16:12 PM PDT 24 Mar 12 02:16:15 PM PDT 24 528040772 ps
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T294 /workspace/coverage/default/14.sram_ctrl_alert_test.180918178 Mar 12 02:20:53 PM PDT 24 Mar 12 02:20:53 PM PDT 24 47274357 ps
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