Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	135260718	1			T1	137625		T2	114563		T3	506190
triple_byte_access	2742131	1			T2	2211		T3	10114		T4	2038
halfword_access	4208326	1			T2	3533		T3	15232		T4	3094
byte_access	5885979	1			T2	4607		T3	20237		T4	4129
zero_access	1781449	1			T2	1142		T3	5069		T4	1046

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74727100

1

T1

688128

T2

63295

T3

301208

auto[1]

75151503

1

T1

688128

T2

62761

T3

255634

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	67271985	1			T1	688128		T2	57518		T3	273955
auto[0]	triple_byte_access	1309136	1			T2	1151		T3	5506		T4	1233
auto[0]	halfword_access	2059535	1			T2	1746		T3	8160		T4	1927
auto[0]	byte_access	3020982	1			T2	2303		T3	10903		T4	2572
auto[0]	zero_access	1065462	1			T2	577		T3	2684		T4	678
auto[1]	word_access	67988733	1			T1	688128		T2	57045		T3	232235
auto[1]	triple_byte_access	1432995	1			T2	1060		T3	4608		T4	805
auto[1]	halfword_access	2148791	1			T2	1787		T3	7072		T4	1167
auto[1]	byte_access	2864997	1			T2	2304		T3	9334		T4	1557
auto[1]	zero_access	715987	1			T2	565		T3	2385		T4	368