Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	339528398	1			T1	107097		T2	314112		T3	522878
instr_valid_dis	301664454	1			T1	107097		T2	314112		T3	522878
instr_en	29929806	1			T14	126900		T26	435918		T47	159036

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9259720	1			T1	82158		T2	96178		T14	69952
sram_ifetch_valid_disable	297475941	1			T1	766550		T2	135448		T3	522878
sram_ifetch_enable	32792737	1			T1	222266		T2	82486		T14	312

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	339528398	1			T1	107097		T2	314112		T3	522878
hw_debug_en_valid_off	299516237	1			T1	853072		T2	193888		T3	522878
hw_debug_en_on	27804007	1			T1	164350		T2	83956		T14	126238

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	297475941	1			T1	766550		T2	135448		T3	522878
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	284070152	1			T1	766550		T2	135448		T3	522878
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10340967	1			T14	56948		T26	121922		T6	178044
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3875260	1			T1	69300		T2	48530		T14	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1453528	1			T1	69300		T2	48530		T47	80
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1479642	1			T14	20000		T47	88586		T135	7032
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3677770	1			T1	2742		T2	47648		T14	49952
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1493752	1			T1	2742		T2	47648		T135	16544
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1738640	1			T14	49952		T26	31250		T133	38862
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11445458	1			T1	37890		T2	1158		T14	75974
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4287008	1			T1	37890		T2	1158		T14	19026
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5831402	1			T14	56948		T26	82898		T6	178044

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15505353	1			T26	250032		T47	70450		T6	78920
lc_exec_en	12680779	1			T1	123718		T2	35150		T14	312
valid_exec_dis	296296147	1			T1	907490		T2	199636		T3	522878
invalid_exec_dis	42052457	1			T1	304424		T2	178664		T14	70264