Name |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.354340155 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3120391750 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.790070313 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3789003913 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.33932931 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2170177158 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1225136436 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3286034153 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1605733737 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3779800442 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1385267796 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3837609347 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3640090069 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2235701325 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.965415573 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3921157839 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1720455699 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3701146530 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2635205170 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3127516278 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3799529389 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2314346964 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1887797380 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2493535874 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3284195303 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4229705492 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2624002926 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.893362494 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2696679816 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4081280252 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.610779493 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.444318858 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.301367070 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1344033229 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.826574632 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3233419758 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.348146454 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3185851349 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2647122579 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1110765602 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1129088130 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3759322883 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3875309543 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1813380278 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3611697316 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2194154886 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3065347986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2445735280 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3520896518 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2875425771 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4211530207 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.208358488 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1627197220 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1467182481 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.744634476 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2149706344 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4077437842 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.52643610 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2607644401 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4244794486 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3171534415 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4129475918 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.299896063 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1008855135 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3830431905 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.44894564 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4041648682 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2050527642 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3851193844 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2597780773 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1727463974 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1250656464 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1569175823 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2857041072 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3716435971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.219291362 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1378886645 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3599919082 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2333119518 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.84810915 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3041604926 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3890807655 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.589131541 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3249657894 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2166388470 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.824304281 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1578372637 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.166892281 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4293059669 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3250279325 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1850170226 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3359933566 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3196139238 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.63563047 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3335887238 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2482892324 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.855009047 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2911928414 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.676009109 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1526287889 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1874849119 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.370210935 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1452179075 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2299648431 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2602898565 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.979496446 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2804802328 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3849582789 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3909481107 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.551565895 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.971761539 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1114894045 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1525396642 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.362894028 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2496181547 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1196547333 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2039667983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1792109509 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2731452510 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.810328564 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3778085897 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2745559885 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3468656626 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4038453169 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1994803425 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1637034013 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2442185014 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4165358351 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2087467031 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.413567566 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2733154348 |
/workspace/coverage/default/0.sram_ctrl_bijection.4141676899 |
/workspace/coverage/default/0.sram_ctrl_executable.3945199606 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1233250358 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3647271048 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1855534582 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2129799956 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3692299340 |
/workspace/coverage/default/0.sram_ctrl_partial_access.505840467 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2613546964 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.574771321 |
/workspace/coverage/default/0.sram_ctrl_regwen.2718250647 |
/workspace/coverage/default/0.sram_ctrl_smoke.3578665375 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3629933797 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.108102345 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1381676531 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3691522338 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2112129272 |
/workspace/coverage/default/1.sram_ctrl_alert_test.3047392558 |
/workspace/coverage/default/1.sram_ctrl_bijection.2473966461 |
/workspace/coverage/default/1.sram_ctrl_executable.1973333844 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2388536727 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.4039147183 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1290392320 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2421843297 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1494373910 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.509837143 |
/workspace/coverage/default/1.sram_ctrl_regwen.246133539 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.656647996 |
/workspace/coverage/default/1.sram_ctrl_smoke.336010772 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.602560273 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2979748513 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.926467553 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.490421099 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2861176370 |
/workspace/coverage/default/10.sram_ctrl_bijection.3751142342 |
/workspace/coverage/default/10.sram_ctrl_executable.703906206 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1226981901 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.1314708744 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.899088715 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.1889596061 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3786605030 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1492836369 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.527223959 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1745698421 |
/workspace/coverage/default/10.sram_ctrl_regwen.3167744046 |
/workspace/coverage/default/10.sram_ctrl_smoke.1492899707 |
/workspace/coverage/default/10.sram_ctrl_stress_all.4018649251 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.25285954 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.57523339 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1855281304 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3884095576 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1969225009 |
/workspace/coverage/default/11.sram_ctrl_bijection.3772541596 |
/workspace/coverage/default/11.sram_ctrl_executable.3895021064 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1416846027 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1501490940 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1234074671 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3297213580 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4163902162 |
/workspace/coverage/default/11.sram_ctrl_partial_access.968657252 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2000426665 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3048919605 |
/workspace/coverage/default/11.sram_ctrl_regwen.337209179 |
/workspace/coverage/default/11.sram_ctrl_smoke.3909886745 |
/workspace/coverage/default/11.sram_ctrl_stress_all.3661811159 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1484484792 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3644348976 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2746370372 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2029028225 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3148001613 |
/workspace/coverage/default/12.sram_ctrl_bijection.3368066880 |
/workspace/coverage/default/12.sram_ctrl_executable.3036238519 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3114114192 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3048400218 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.646909138 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.861709340 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.441435685 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2734860931 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3400126622 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1433774534 |
/workspace/coverage/default/12.sram_ctrl_regwen.3674087747 |
/workspace/coverage/default/12.sram_ctrl_smoke.2753137544 |
/workspace/coverage/default/12.sram_ctrl_stress_all.4073688348 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2001563822 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1497543840 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1149588445 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1653521375 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3378471982 |
/workspace/coverage/default/13.sram_ctrl_bijection.3610004911 |
/workspace/coverage/default/13.sram_ctrl_executable.35853482 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.720989631 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1847796964 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1543496623 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.1576690448 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2214575505 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1551947592 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.492975648 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2424611994 |
/workspace/coverage/default/13.sram_ctrl_regwen.2813601739 |
/workspace/coverage/default/13.sram_ctrl_smoke.1960386904 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2364745974 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4284979850 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1963325160 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1919316486 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.861487453 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1835162205 |
/workspace/coverage/default/14.sram_ctrl_bijection.167222333 |
/workspace/coverage/default/14.sram_ctrl_executable.1858223334 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2482292093 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.108326379 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3352000903 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.4109387530 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2887719390 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1553042331 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3303618248 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.4266596833 |
/workspace/coverage/default/14.sram_ctrl_regwen.3973497698 |
/workspace/coverage/default/14.sram_ctrl_smoke.730022151 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2298723501 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2718184675 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1867240248 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1991762871 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1874275207 |
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/workspace/coverage/default/44.sram_ctrl_mem_walk.510350028 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3258072778 |
/workspace/coverage/default/44.sram_ctrl_partial_access.3670990770 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1656617669 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1358478845 |
/workspace/coverage/default/44.sram_ctrl_regwen.1286454420 |
/workspace/coverage/default/44.sram_ctrl_smoke.1744103784 |
/workspace/coverage/default/44.sram_ctrl_stress_all.2660107609 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4158288208 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3087245656 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2270564853 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1551236222 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1551192832 |
/workspace/coverage/default/45.sram_ctrl_bijection.2009240161 |
/workspace/coverage/default/45.sram_ctrl_executable.2844132690 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1101764219 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2169447254 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3743622333 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3952725077 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.4244743198 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3236388242 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2987151428 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.485673659 |
/workspace/coverage/default/45.sram_ctrl_regwen.1475337765 |
/workspace/coverage/default/45.sram_ctrl_smoke.3582842041 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3869484362 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3368764303 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3668475252 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1949466695 |
/workspace/coverage/default/46.sram_ctrl_alert_test.4290488942 |
/workspace/coverage/default/46.sram_ctrl_bijection.2328420468 |
/workspace/coverage/default/46.sram_ctrl_executable.3275389183 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2503787464 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1953970343 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3683678049 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3209732518 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3001397091 |
/workspace/coverage/default/46.sram_ctrl_partial_access.478722884 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1162728887 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.192976943 |
/workspace/coverage/default/46.sram_ctrl_regwen.716617527 |
/workspace/coverage/default/46.sram_ctrl_smoke.1113407578 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3640942098 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4166534138 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3654520649 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.971915094 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1334916064 |
/workspace/coverage/default/47.sram_ctrl_alert_test.2563986794 |
/workspace/coverage/default/47.sram_ctrl_bijection.3816403837 |
/workspace/coverage/default/47.sram_ctrl_executable.1527225668 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2029256140 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.4196405279 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1460451146 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2248377137 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2759039318 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2801346277 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1211950635 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2980214844 |
/workspace/coverage/default/47.sram_ctrl_regwen.1020509312 |
/workspace/coverage/default/47.sram_ctrl_smoke.1570470571 |
/workspace/coverage/default/47.sram_ctrl_stress_all.513935777 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1726977335 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1463050809 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2291464403 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3156110044 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2792077699 |
/workspace/coverage/default/48.sram_ctrl_bijection.1142433851 |
/workspace/coverage/default/48.sram_ctrl_executable.3993053948 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2462414097 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3551241098 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.400580317 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.683019269 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.997327607 |
/workspace/coverage/default/48.sram_ctrl_partial_access.4104964996 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2409185331 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.458905455 |
/workspace/coverage/default/48.sram_ctrl_regwen.3422266366 |
/workspace/coverage/default/48.sram_ctrl_smoke.4041031036 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3602327812 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3346503141 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1519550580 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.295057510 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2197020720 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3717954940 |
/workspace/coverage/default/49.sram_ctrl_bijection.2151006894 |
/workspace/coverage/default/49.sram_ctrl_executable.3494339068 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3509987888 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3010299574 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1385459776 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.597130001 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.198651492 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2719933838 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2409080287 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3249883378 |
/workspace/coverage/default/49.sram_ctrl_regwen.814461360 |
/workspace/coverage/default/49.sram_ctrl_smoke.3754249840 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3826384674 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.62427590 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2395833551 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3303911327 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2674416729 |
/workspace/coverage/default/5.sram_ctrl_alert_test.963661649 |
/workspace/coverage/default/5.sram_ctrl_bijection.3779936623 |
/workspace/coverage/default/5.sram_ctrl_executable.606510102 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2984134059 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.4162494484 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2129709703 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.3002391670 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1190297458 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3159624883 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1530948177 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2906211982 |
/workspace/coverage/default/5.sram_ctrl_regwen.1310425640 |
/workspace/coverage/default/5.sram_ctrl_smoke.3346826535 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1787179756 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2822232866 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2612228196 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1192133781 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2479322441 |
/workspace/coverage/default/6.sram_ctrl_bijection.1234970509 |
/workspace/coverage/default/6.sram_ctrl_executable.3138946269 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2235966843 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3138712286 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1893925665 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2765898104 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2589368537 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1047314612 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2867090897 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2348529630 |
/workspace/coverage/default/6.sram_ctrl_regwen.4223378744 |
/workspace/coverage/default/6.sram_ctrl_smoke.2553823298 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2932393505 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3249900988 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.69253637 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2196226754 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.133547947 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1637447133 |
/workspace/coverage/default/7.sram_ctrl_bijection.2622498127 |
/workspace/coverage/default/7.sram_ctrl_executable.2546130537 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2800683776 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2978866803 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4223513038 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3189817457 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4078860670 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3879681086 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2028210442 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.732043501 |
/workspace/coverage/default/7.sram_ctrl_regwen.3681832141 |
/workspace/coverage/default/7.sram_ctrl_smoke.1212367256 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2074664771 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2980987222 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.696675557 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1462585782 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3293590365 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2492793479 |
/workspace/coverage/default/8.sram_ctrl_bijection.201399898 |
/workspace/coverage/default/8.sram_ctrl_executable.355629489 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4285316373 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1981052293 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2282989511 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.3151755996 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3356203609 |
/workspace/coverage/default/8.sram_ctrl_partial_access.273799102 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2497788357 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1065585389 |
/workspace/coverage/default/8.sram_ctrl_regwen.1525524333 |
/workspace/coverage/default/8.sram_ctrl_smoke.3874351528 |
/workspace/coverage/default/8.sram_ctrl_stress_all.4189520539 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2801921431 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1748892314 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.408465395 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.841585266 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3184839852 |
/workspace/coverage/default/9.sram_ctrl_bijection.3081318961 |
/workspace/coverage/default/9.sram_ctrl_executable.4083259370 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2735155544 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2731009235 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2901148167 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.603075910 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1925022611 |
/workspace/coverage/default/9.sram_ctrl_partial_access.549366361 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2752501149 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3581085775 |
/workspace/coverage/default/9.sram_ctrl_regwen.3848570368 |
/workspace/coverage/default/9.sram_ctrl_smoke.192160381 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3337827296 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3360459030 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.632799593 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3209525738 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/22.sram_ctrl_stress_all.3511880643 |
|
|
Mar 14 12:51:30 PM PDT 24 |
Mar 14 01:43:01 PM PDT 24 |
68570792329 ps |
T2 |
/workspace/coverage/default/34.sram_ctrl_regwen.3567083044 |
|
|
Mar 14 12:52:45 PM PDT 24 |
Mar 14 01:09:21 PM PDT 24 |
16350027342 ps |
T3 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.509837143 |
|
|
Mar 14 12:50:24 PM PDT 24 |
Mar 14 12:58:02 PM PDT 24 |
25445511373 ps |
T8 |
/workspace/coverage/default/31.sram_ctrl_partial_access.4009824918 |
|
|
Mar 14 12:52:24 PM PDT 24 |
Mar 14 12:52:40 PM PDT 24 |
732449623 ps |
T4 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.4039875772 |
|
|
Mar 14 12:52:36 PM PDT 24 |
Mar 14 12:53:47 PM PDT 24 |
2533703936 ps |
T9 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2901148167 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 12:53:07 PM PDT 24 |
6734364398 ps |
T5 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3040447690 |
|
|
Mar 14 12:51:45 PM PDT 24 |
Mar 14 12:52:38 PM PDT 24 |
26066981214 ps |
T10 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.4209897765 |
|
|
Mar 14 12:52:46 PM PDT 24 |
Mar 14 12:55:24 PM PDT 24 |
21080995089 ps |
T11 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3509402284 |
|
|
Mar 14 12:53:03 PM PDT 24 |
Mar 14 12:56:02 PM PDT 24 |
9143265317 ps |
T12 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1553042331 |
|
|
Mar 14 12:50:59 PM PDT 24 |
Mar 14 12:51:05 PM PDT 24 |
429641567 ps |
T72 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2469270275 |
|
|
Mar 14 12:52:27 PM PDT 24 |
Mar 14 12:54:32 PM PDT 24 |
4029988435 ps |
T73 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.4109387530 |
|
|
Mar 14 12:51:15 PM PDT 24 |
Mar 14 12:53:20 PM PDT 24 |
10391928801 ps |
T18 |
/workspace/coverage/default/31.sram_ctrl_bijection.3056204470 |
|
|
Mar 14 12:52:26 PM PDT 24 |
Mar 14 01:27:27 PM PDT 24 |
127022667376 ps |
T14 |
/workspace/coverage/default/7.sram_ctrl_executable.2546130537 |
|
|
Mar 14 12:50:43 PM PDT 24 |
Mar 14 12:55:15 PM PDT 24 |
31224021331 ps |
T30 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2773123096 |
|
|
Mar 14 12:52:13 PM PDT 24 |
Mar 14 12:52:23 PM PDT 24 |
308462894 ps |
T15 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.956673409 |
|
|
Mar 14 12:50:47 PM PDT 24 |
Mar 14 01:01:22 PM PDT 24 |
22242662823 ps |
T25 |
/workspace/coverage/default/1.sram_ctrl_regwen.246133539 |
|
|
Mar 14 12:50:28 PM PDT 24 |
Mar 14 12:56:34 PM PDT 24 |
2263320950 ps |
T57 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1802970369 |
|
|
Mar 14 12:51:10 PM PDT 24 |
Mar 14 01:00:42 PM PDT 24 |
48467578151 ps |
T58 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.4101164722 |
|
|
Mar 14 12:53:53 PM PDT 24 |
Mar 14 12:56:19 PM PDT 24 |
1564847972 ps |
T31 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1782430454 |
|
|
Mar 14 12:53:28 PM PDT 24 |
Mar 14 12:53:40 PM PDT 24 |
614441600 ps |
T59 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1977247965 |
|
|
Mar 14 12:51:25 PM PDT 24 |
Mar 14 12:53:33 PM PDT 24 |
2061131460 ps |
T26 |
/workspace/coverage/default/45.sram_ctrl_regwen.1475337765 |
|
|
Mar 14 12:54:16 PM PDT 24 |
Mar 14 01:15:13 PM PDT 24 |
19707151778 ps |
T13 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3203857133 |
|
|
Mar 14 12:53:24 PM PDT 24 |
Mar 14 01:11:43 PM PDT 24 |
24316290597 ps |
T33 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2424611994 |
|
|
Mar 14 12:51:16 PM PDT 24 |
Mar 14 12:51:19 PM PDT 24 |
365359734 ps |
T16 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1991762871 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 01:21:01 PM PDT 24 |
76895707490 ps |
T143 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2069954189 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 12:51:22 PM PDT 24 |
3008030295 ps |
T32 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1757454109 |
|
|
Mar 14 12:54:01 PM PDT 24 |
Mar 14 12:54:23 PM PDT 24 |
2714386589 ps |
T17 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2209960086 |
|
|
Mar 14 12:50:27 PM PDT 24 |
Mar 14 01:10:30 PM PDT 24 |
17699927413 ps |
T98 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2752501149 |
|
|
Mar 14 12:51:04 PM PDT 24 |
Mar 14 12:58:29 PM PDT 24 |
19560109174 ps |
T47 |
/workspace/coverage/default/4.sram_ctrl_executable.609660009 |
|
|
Mar 14 12:50:41 PM PDT 24 |
Mar 14 01:15:58 PM PDT 24 |
37261867866 ps |
T6 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2267231420 |
|
|
Mar 14 12:52:14 PM PDT 24 |
Mar 14 01:36:39 PM PDT 24 |
26026421935 ps |
T117 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1462585782 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 12:53:27 PM PDT 24 |
3105777099 ps |
T34 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.4040006100 |
|
|
Mar 14 12:51:15 PM PDT 24 |
Mar 14 12:51:18 PM PDT 24 |
1404741118 ps |
T118 |
/workspace/coverage/default/17.sram_ctrl_bijection.2129644828 |
|
|
Mar 14 12:51:15 PM PDT 24 |
Mar 14 01:10:12 PM PDT 24 |
66901185333 ps |
T99 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1566749303 |
|
|
Mar 14 12:53:43 PM PDT 24 |
Mar 14 12:56:25 PM PDT 24 |
3860533807 ps |
T19 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1170394348 |
|
|
Mar 14 12:50:49 PM PDT 24 |
Mar 14 12:50:49 PM PDT 24 |
11904783 ps |
T100 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2718184675 |
|
|
Mar 14 12:51:14 PM PDT 24 |
Mar 14 12:53:53 PM PDT 24 |
2864859343 ps |
T7 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1926209379 |
|
|
Mar 14 12:50:30 PM PDT 24 |
Mar 14 12:51:55 PM PDT 24 |
31472077354 ps |
T144 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2296433566 |
|
|
Mar 14 12:51:56 PM PDT 24 |
Mar 14 12:54:32 PM PDT 24 |
28792666629 ps |
T60 |
/workspace/coverage/default/7.sram_ctrl_regwen.3681832141 |
|
|
Mar 14 12:50:55 PM PDT 24 |
Mar 14 12:55:01 PM PDT 24 |
8776572689 ps |
T145 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1911364089 |
|
|
Mar 14 12:51:21 PM PDT 24 |
Mar 14 12:51:58 PM PDT 24 |
2497038658 ps |
T48 |
/workspace/coverage/default/37.sram_ctrl_regwen.1786688314 |
|
|
Mar 14 12:53:03 PM PDT 24 |
Mar 14 01:00:31 PM PDT 24 |
7309847599 ps |
T79 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2280214053 |
|
|
Mar 14 12:52:14 PM PDT 24 |
Mar 14 01:19:57 PM PDT 24 |
142200441626 ps |
T61 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2029256140 |
|
|
Mar 14 12:54:39 PM PDT 24 |
Mar 14 12:55:30 PM PDT 24 |
15050365488 ps |
T80 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1334916064 |
|
|
Mar 14 12:54:37 PM PDT 24 |
Mar 14 01:06:38 PM PDT 24 |
4415331545 ps |
T133 |
/workspace/coverage/default/38.sram_ctrl_executable.3901035170 |
|
|
Mar 14 12:53:17 PM PDT 24 |
Mar 14 12:56:41 PM PDT 24 |
23919326026 ps |
T50 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3685809907 |
|
|
Mar 14 12:51:22 PM PDT 24 |
Mar 14 12:51:46 PM PDT 24 |
8228026153 ps |
T146 |
/workspace/coverage/default/45.sram_ctrl_bijection.2009240161 |
|
|
Mar 14 12:54:14 PM PDT 24 |
Mar 14 01:12:33 PM PDT 24 |
254064673391 ps |
T147 |
/workspace/coverage/default/34.sram_ctrl_smoke.3295300064 |
|
|
Mar 14 12:52:45 PM PDT 24 |
Mar 14 12:53:06 PM PDT 24 |
1461039223 ps |
T148 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2023844571 |
|
|
Mar 14 12:52:27 PM PDT 24 |
Mar 14 12:53:34 PM PDT 24 |
8306376397 ps |
T142 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.859868458 |
|
|
Mar 14 12:52:49 PM PDT 24 |
Mar 14 12:52:57 PM PDT 24 |
3734990400 ps |
T101 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2802979987 |
|
|
Mar 14 12:51:55 PM PDT 24 |
Mar 14 12:56:09 PM PDT 24 |
3556108839 ps |
T149 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2809258229 |
|
|
Mar 14 12:51:39 PM PDT 24 |
Mar 14 12:52:56 PM PDT 24 |
815542344 ps |
T150 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1381387811 |
|
|
Mar 14 12:51:12 PM PDT 24 |
Mar 14 01:27:57 PM PDT 24 |
54783475278 ps |
T151 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1192133781 |
|
|
Mar 14 12:50:50 PM PDT 24 |
Mar 14 12:50:59 PM PDT 24 |
1385096293 ps |
T35 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1113887221 |
|
|
Mar 14 12:51:15 PM PDT 24 |
Mar 14 12:51:18 PM PDT 24 |
4167713962 ps |
T51 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2283958710 |
|
|
Mar 14 12:53:15 PM PDT 24 |
Mar 14 12:57:13 PM PDT 24 |
7044975135 ps |
T81 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.1222287926 |
|
|
Mar 14 12:52:26 PM PDT 24 |
Mar 14 01:01:31 PM PDT 24 |
6637016503 ps |
T20 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2801166524 |
|
|
Mar 14 12:52:39 PM PDT 24 |
Mar 14 12:52:40 PM PDT 24 |
50262503 ps |
T82 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1551236222 |
|
|
Mar 14 12:54:17 PM PDT 24 |
Mar 14 01:07:03 PM PDT 24 |
11565699996 ps |
T21 |
/workspace/coverage/default/1.sram_ctrl_alert_test.3047392558 |
|
|
Mar 14 12:50:30 PM PDT 24 |
Mar 14 12:50:30 PM PDT 24 |
15608514 ps |
T83 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1510835976 |
|
|
Mar 14 12:53:53 PM PDT 24 |
Mar 14 01:17:27 PM PDT 24 |
20373478103 ps |
T52 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3184757382 |
|
|
Mar 14 12:51:32 PM PDT 24 |
Mar 14 12:51:59 PM PDT 24 |
2909402904 ps |
T152 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.4181533385 |
|
|
Mar 14 12:50:30 PM PDT 24 |
Mar 14 12:59:43 PM PDT 24 |
29506386879 ps |
T153 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1700666252 |
|
|
Mar 14 12:51:15 PM PDT 24 |
Mar 14 01:09:07 PM PDT 24 |
64903850025 ps |
T154 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3184839852 |
|
|
Mar 14 12:50:57 PM PDT 24 |
Mar 14 12:50:58 PM PDT 24 |
15546996 ps |
T155 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3493674159 |
|
|
Mar 14 12:50:32 PM PDT 24 |
Mar 14 12:50:36 PM PDT 24 |
358207510 ps |
T102 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3166144398 |
|
|
Mar 14 12:52:57 PM PDT 24 |
Mar 14 12:58:15 PM PDT 24 |
17732464103 ps |
T156 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.1427641883 |
|
|
Mar 14 12:51:16 PM PDT 24 |
Mar 14 12:53:15 PM PDT 24 |
3178371772 ps |
T157 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1233250358 |
|
|
Mar 14 12:50:45 PM PDT 24 |
Mar 14 12:51:24 PM PDT 24 |
17092094974 ps |
T103 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.163095420 |
|
|
Mar 14 12:51:32 PM PDT 24 |
Mar 14 12:57:57 PM PDT 24 |
109507155420 ps |
T158 |
/workspace/coverage/default/48.sram_ctrl_smoke.4041031036 |
|
|
Mar 14 12:54:49 PM PDT 24 |
Mar 14 12:55:10 PM PDT 24 |
1643455739 ps |
T159 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1551192832 |
|
|
Mar 14 12:54:24 PM PDT 24 |
Mar 14 12:54:25 PM PDT 24 |
25099472 ps |
T160 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3264651103 |
|
|
Mar 14 12:53:16 PM PDT 24 |
Mar 14 12:59:39 PM PDT 24 |
5558839011 ps |
T161 |
/workspace/coverage/default/2.sram_ctrl_partial_access.2835744339 |
|
|
Mar 14 12:50:33 PM PDT 24 |
Mar 14 12:50:41 PM PDT 24 |
3056498459 ps |
T162 |
/workspace/coverage/default/22.sram_ctrl_smoke.2034571242 |
|
|
Mar 14 12:51:27 PM PDT 24 |
Mar 14 12:51:44 PM PDT 24 |
1342527000 ps |
T163 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.295057510 |
|
|
Mar 14 12:54:48 PM PDT 24 |
Mar 14 12:54:57 PM PDT 24 |
2842116651 ps |
T164 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3248366393 |
|
|
Mar 14 12:51:39 PM PDT 24 |
Mar 14 12:58:25 PM PDT 24 |
13068056916 ps |
T93 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1855534582 |
|
|
Mar 14 12:50:25 PM PDT 24 |
Mar 14 12:52:51 PM PDT 24 |
36229316842 ps |
T165 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2820410904 |
|
|
Mar 14 12:51:38 PM PDT 24 |
Mar 14 12:53:12 PM PDT 24 |
1667281955 ps |
T166 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.2902129747 |
|
|
Mar 14 12:53:14 PM PDT 24 |
Mar 14 12:55:55 PM PDT 24 |
28734634736 ps |
T167 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1711710550 |
|
|
Mar 14 12:51:50 PM PDT 24 |
Mar 14 01:05:10 PM PDT 24 |
15062358343 ps |
T168 |
/workspace/coverage/default/38.sram_ctrl_smoke.1643455595 |
|
|
Mar 14 12:53:16 PM PDT 24 |
Mar 14 12:55:22 PM PDT 24 |
2862283939 ps |
T169 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3786605030 |
|
|
Mar 14 12:50:55 PM PDT 24 |
Mar 14 01:15:48 PM PDT 24 |
43121821544 ps |
T119 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2563054384 |
|
|
Mar 14 12:52:39 PM PDT 24 |
Mar 14 12:53:01 PM PDT 24 |
12669865587 ps |
T170 |
/workspace/coverage/default/8.sram_ctrl_smoke.3874351528 |
|
|
Mar 14 12:50:48 PM PDT 24 |
Mar 14 12:51:13 PM PDT 24 |
687169365 ps |
T53 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.272541888 |
|
|
Mar 14 12:51:16 PM PDT 24 |
Mar 14 12:51:24 PM PDT 24 |
2973734999 ps |
T171 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2070492806 |
|
|
Mar 14 12:52:47 PM PDT 24 |
Mar 14 12:52:49 PM PDT 24 |
37422790 ps |
T172 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2623310038 |
|
|
Mar 14 12:52:46 PM PDT 24 |
Mar 14 12:53:00 PM PDT 24 |
1417182271 ps |
T173 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2733154348 |
|
|
Mar 14 12:50:31 PM PDT 24 |
Mar 14 12:50:32 PM PDT 24 |
36627720 ps |
T135 |
/workspace/coverage/default/36.sram_ctrl_stress_all.4016526712 |
|
|
Mar 14 12:53:04 PM PDT 24 |
Mar 14 01:22:06 PM PDT 24 |
87662548588 ps |
T94 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.513980389 |
|
|
Mar 14 12:53:37 PM PDT 24 |
Mar 14 12:55:42 PM PDT 24 |
6273632721 ps |
T174 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2471673350 |
|
|
Mar 14 12:51:55 PM PDT 24 |
Mar 14 12:54:52 PM PDT 24 |
3153761493 ps |
T175 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4123402106 |
|
|
Mar 14 12:51:43 PM PDT 24 |
Mar 14 12:57:50 PM PDT 24 |
16076531110 ps |
T176 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3297213580 |
|
|
Mar 14 12:51:02 PM PDT 24 |
Mar 14 12:55:48 PM PDT 24 |
14351345349 ps |
T177 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1339044332 |
|
|
Mar 14 12:51:29 PM PDT 24 |
Mar 14 12:54:43 PM PDT 24 |
7308282606 ps |
T178 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.104042137 |
|
|
Mar 14 12:52:17 PM PDT 24 |
Mar 14 12:57:58 PM PDT 24 |
9135037064 ps |
T139 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1793097799 |
|
|
Mar 14 12:50:30 PM PDT 24 |
Mar 14 12:58:08 PM PDT 24 |
81810642655 ps |
T138 |
/workspace/coverage/default/21.sram_ctrl_regwen.4216727911 |
|
|
Mar 14 12:51:21 PM PDT 24 |
Mar 14 01:00:26 PM PDT 24 |
8781934159 ps |
T179 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.910572526 |
|
|
Mar 14 12:53:42 PM PDT 24 |
Mar 14 01:04:00 PM PDT 24 |
9835116867 ps |
T54 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1150828497 |
|
|
Mar 14 12:53:53 PM PDT 24 |
Mar 14 12:58:45 PM PDT 24 |
3783016175 ps |
T55 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3872438075 |
|
|
Mar 14 12:53:28 PM PDT 24 |
Mar 14 12:54:02 PM PDT 24 |
2695633021 ps |
T180 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.732043501 |
|
|
Mar 14 12:50:55 PM PDT 24 |
Mar 14 12:50:58 PM PDT 24 |
654726273 ps |
T140 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1211950635 |
|
|
Mar 14 12:54:37 PM PDT 24 |
Mar 14 12:58:48 PM PDT 24 |
10726867704 ps |
T181 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3425898865 |
|
|
Mar 14 12:53:36 PM PDT 24 |
Mar 14 12:53:40 PM PDT 24 |
4202475304 ps |
T182 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3720606564 |
|
|
Mar 14 12:51:48 PM PDT 24 |
Mar 14 12:56:56 PM PDT 24 |
21114085278 ps |
T183 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1300902117 |
|
|
Mar 14 12:51:55 PM PDT 24 |
Mar 14 12:52:10 PM PDT 24 |
3082795818 ps |
T184 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1875169832 |
|
|
Mar 14 12:53:22 PM PDT 24 |
Mar 14 12:56:07 PM PDT 24 |
86169077355 ps |
T185 |
/workspace/coverage/default/43.sram_ctrl_executable.1142940573 |
|
|
Mar 14 12:54:03 PM PDT 24 |
Mar 14 01:07:23 PM PDT 24 |
30589941237 ps |
T186 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2527503538 |
|
|
Mar 14 12:52:45 PM PDT 24 |
Mar 14 12:52:52 PM PDT 24 |
708347173 ps |
T187 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.133547947 |
|
|
Mar 14 12:50:52 PM PDT 24 |
Mar 14 01:09:33 PM PDT 24 |
11338742853 ps |
T136 |
/workspace/coverage/default/40.sram_ctrl_regwen.4038502131 |
|
|
Mar 14 12:53:36 PM PDT 24 |
Mar 14 01:18:37 PM PDT 24 |
5921651159 ps |
T188 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2264584890 |
|
|
Mar 14 12:52:45 PM PDT 24 |
Mar 14 12:55:55 PM PDT 24 |
7636415530 ps |
T189 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1835162205 |
|
|
Mar 14 12:51:09 PM PDT 24 |
Mar 14 12:51:09 PM PDT 24 |
20449125 ps |
T190 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1748892314 |
|
|
Mar 14 12:50:54 PM PDT 24 |
Mar 14 12:53:35 PM PDT 24 |
2378666546 ps |
T191 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.121880152 |
|
|
Mar 14 12:51:48 PM PDT 24 |
Mar 14 12:53:03 PM PDT 24 |
9339235248 ps |
T192 |
/workspace/coverage/default/31.sram_ctrl_regwen.1011361079 |
|
|
Mar 14 12:52:27 PM PDT 24 |
Mar 14 01:03:10 PM PDT 24 |
121506865933 ps |
T193 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.3151755996 |
|
|
Mar 14 12:50:57 PM PDT 24 |
Mar 14 12:53:44 PM PDT 24 |
43104773846 ps |
T194 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.4038706000 |
|
|
Mar 14 12:51:14 PM PDT 24 |
Mar 14 12:58:56 PM PDT 24 |
19112126692 ps |
T195 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2710334637 |
|
|
Mar 14 12:52:41 PM PDT 24 |
Mar 14 12:53:22 PM PDT 24 |
2826871100 ps |
T196 |
/workspace/coverage/default/11.sram_ctrl_regwen.337209179 |
|
|
Mar 14 12:51:00 PM PDT 24 |
Mar 14 12:58:02 PM PDT 24 |
5615565540 ps |
T27 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3480322869 |
|
|
Mar 14 12:52:38 PM PDT 24 |
Mar 14 12:53:31 PM PDT 24 |
8408472124 ps |
T197 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4223513038 |
|
|
Mar 14 12:50:49 PM PDT 24 |
Mar 14 12:53:17 PM PDT 24 |
18135525763 ps |
T198 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.1300070380 |
|
|
Mar 14 12:52:48 PM PDT 24 |
Mar 14 01:04:41 PM PDT 24 |
75448870669 ps |
T137 |
/workspace/coverage/default/29.sram_ctrl_regwen.2831192201 |
|
|
Mar 14 12:52:14 PM PDT 24 |
Mar 14 01:19:33 PM PDT 24 |
13581092515 ps |
T199 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1177012233 |
|
|
Mar 14 12:52:37 PM PDT 24 |
Mar 14 12:52:40 PM PDT 24 |
351136748 ps |
T200 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1637447133 |
|
|
Mar 14 12:50:54 PM PDT 24 |
Mar 14 12:50:55 PM PDT 24 |
19795346 ps |
T201 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1991810384 |
|
|
Mar 14 12:51:18 PM PDT 24 |
Mar 14 12:55:16 PM PDT 24 |
4110541883 ps |
T202 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1286688055 |
|
|
Mar 14 12:51:12 PM PDT 24 |
Mar 14 12:55:39 PM PDT 24 |
9035212977 ps |
T203 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.482692377 |
|
|
Mar 14 12:52:46 PM PDT 24 |
Mar 14 12:52:49 PM PDT 24 |
358943932 ps |
T204 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3691522338 |
|
|
Mar 14 12:50:30 PM PDT 24 |
Mar 14 12:52:36 PM PDT 24 |
3071355013 ps |
T205 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.4108246514 |
|
|
Mar 14 12:52:05 PM PDT 24 |
Mar 14 12:54:20 PM PDT 24 |
3313821734 ps |
T206 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1551947592 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 12:51:19 PM PDT 24 |
937623355 ps |
T134 |
/workspace/coverage/default/37.sram_ctrl_executable.4088021213 |
|
|
Mar 14 12:53:04 PM PDT 24 |
Mar 14 01:13:42 PM PDT 24 |
63595375456 ps |
T56 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.25285954 |
|
|
Mar 14 12:50:58 PM PDT 24 |
Mar 14 12:52:33 PM PDT 24 |
9580366231 ps |
T207 |
/workspace/coverage/default/31.sram_ctrl_smoke.1591819291 |
|
|
Mar 14 12:52:26 PM PDT 24 |
Mar 14 12:52:44 PM PDT 24 |
1715225577 ps |
T208 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.4101576947 |
|
|
Mar 14 12:51:21 PM PDT 24 |
Mar 14 12:52:11 PM PDT 24 |
2227457842 ps |
T108 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.805543025 |
|
|
Mar 14 12:50:37 PM PDT 24 |
Mar 14 12:51:20 PM PDT 24 |
2103871504 ps |
T209 |
/workspace/coverage/default/33.sram_ctrl_executable.2491276750 |
|
|
Mar 14 12:52:37 PM PDT 24 |
Mar 14 01:13:31 PM PDT 24 |
18294727128 ps |
T210 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1290392320 |
|
|
Mar 14 12:50:23 PM PDT 24 |
Mar 14 12:53:06 PM PDT 24 |
21505860019 ps |
T211 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1494373910 |
|
|
Mar 14 12:50:35 PM PDT 24 |
Mar 14 12:50:58 PM PDT 24 |
5987837518 ps |
T212 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2942642545 |
|
|
Mar 14 12:51:42 PM PDT 24 |
Mar 14 12:52:04 PM PDT 24 |
2055492584 ps |
T213 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.749739059 |
|
|
Mar 14 12:53:46 PM PDT 24 |
Mar 14 01:08:42 PM PDT 24 |
26698227198 ps |
T214 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1971056894 |
|
|
Mar 14 12:51:17 PM PDT 24 |
Mar 14 12:52:29 PM PDT 24 |
769302058 ps |
T215 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.841769192 |
|
|
Mar 14 12:52:14 PM PDT 24 |
Mar 14 12:56:15 PM PDT 24 |
3948422816 ps |
T216 |
/workspace/coverage/default/3.sram_ctrl_smoke.466420985 |
|
|
Mar 14 12:50:37 PM PDT 24 |
Mar 14 12:52:42 PM PDT 24 |
8077771721 ps |
T217 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.528699336 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 12:52:04 PM PDT 24 |
38495227630 ps |
T218 |
/workspace/coverage/default/41.sram_ctrl_smoke.4008419917 |
|
|
Mar 14 12:53:45 PM PDT 24 |
Mar 14 12:54:43 PM PDT 24 |
1047129463 ps |
T219 |
/workspace/coverage/default/42.sram_ctrl_bijection.2896906021 |
|
|
Mar 14 12:53:44 PM PDT 24 |
Mar 14 01:12:36 PM PDT 24 |
622516026730 ps |
T220 |
/workspace/coverage/default/45.sram_ctrl_executable.2844132690 |
|
|
Mar 14 12:54:15 PM PDT 24 |
Mar 14 01:17:37 PM PDT 24 |
53822763378 ps |
T221 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3002078713 |
|
|
Mar 14 12:53:24 PM PDT 24 |
Mar 14 12:53:25 PM PDT 24 |
13669728 ps |
T222 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1855281304 |
|
|
Mar 14 12:50:59 PM PDT 24 |
Mar 14 12:52:50 PM PDT 24 |
3121590438 ps |
T223 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2395833551 |
|
|
Mar 14 12:54:59 PM PDT 24 |
Mar 14 01:00:09 PM PDT 24 |
3827037972 ps |
T224 |
/workspace/coverage/default/3.sram_ctrl_bijection.2444779369 |
|
|
Mar 14 12:50:33 PM PDT 24 |
Mar 14 01:15:58 PM PDT 24 |
197415706845 ps |
T225 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2135533374 |
|
|
Mar 14 12:51:14 PM PDT 24 |
Mar 14 12:54:24 PM PDT 24 |
29281503101 ps |
T226 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.121015669 |
|
|
Mar 14 12:52:49 PM PDT 24 |
Mar 14 12:55:13 PM PDT 24 |
11051830792 ps |
T227 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1047314612 |
|
|
Mar 14 12:50:36 PM PDT 24 |
Mar 14 12:51:00 PM PDT 24 |
1148766473 ps |
T228 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2381334355 |
|
|
Mar 14 12:51:11 PM PDT 24 |
Mar 14 12:52:46 PM PDT 24 |
3194640654 ps |
T229 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1049485764 |
|
|
Mar 14 12:50:33 PM PDT 24 |
Mar 14 12:50:43 PM PDT 24 |
693508996 ps |
T28 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1226981901 |
|
|
Mar 14 12:50:55 PM PDT 24 |
Mar 14 12:51:56 PM PDT 24 |
10326623976 ps |
T49 |
/workspace/coverage/default/14.sram_ctrl_stress_all.1001522647 |
|
|
Mar 14 12:51:13 PM PDT 24 |
Mar 14 01:41:17 PM PDT 24 |
391507949789 ps |
T230 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.1576690448 |
|
|
Mar 14 12:51:09 PM PDT 24 |
Mar 14 12:57:07 PM PDT 24 |
275207198420 ps |
T231 |
/workspace/coverage/default/32.sram_ctrl_bijection.2696733508 |
|
|
Mar 14 12:52:37 PM PDT 24 |
Mar 14 01:22:29 PM PDT 24 |
34094741315 ps |
T232 |
/workspace/coverage/default/33.sram_ctrl_bijection.477238973 |
|
|
Mar 14 12:52:39 PM PDT 24 |
Mar 14 01:16:46 PM PDT 24 |
79059774311 ps |
T233 |
/workspace/coverage/default/14.sram_ctrl_smoke.730022151 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 12:51:10 PM PDT 24 |
683440860 ps |
T234 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4278456533 |
|
|
Mar 14 12:52:44 PM PDT 24 |
Mar 14 12:54:33 PM PDT 24 |
1210487240 ps |
T235 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2169447254 |
|
|
Mar 14 12:54:15 PM PDT 24 |
Mar 14 12:55:32 PM PDT 24 |
774237659 ps |
T236 |
/workspace/coverage/default/44.sram_ctrl_bijection.2656905921 |
|
|
Mar 14 12:54:03 PM PDT 24 |
Mar 14 01:15:03 PM PDT 24 |
79237814081 ps |
T237 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1688553163 |
|
|
Mar 14 12:52:38 PM PDT 24 |
Mar 14 01:18:37 PM PDT 24 |
23020236431 ps |
T238 |
/workspace/coverage/default/24.sram_ctrl_executable.1381722434 |
|
|
Mar 14 12:51:45 PM PDT 24 |
Mar 14 12:59:39 PM PDT 24 |
20651328836 ps |
T239 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2039849370 |
|
|
Mar 14 12:51:40 PM PDT 24 |
Mar 14 01:10:34 PM PDT 24 |
16164224146 ps |
T240 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1034200525 |
|
|
Mar 14 12:50:46 PM PDT 24 |
Mar 14 12:51:03 PM PDT 24 |
2272381343 ps |
T241 |
/workspace/coverage/default/48.sram_ctrl_bijection.1142433851 |
|
|
Mar 14 12:54:48 PM PDT 24 |
Mar 14 01:19:54 PM PDT 24 |
40989116885 ps |
T242 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1605039507 |
|
|
Mar 14 12:50:34 PM PDT 24 |
Mar 14 01:05:40 PM PDT 24 |
18817965346 ps |
T141 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1162728887 |
|
|
Mar 14 12:54:22 PM PDT 24 |
Mar 14 01:01:45 PM PDT 24 |
22302163764 ps |
T243 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2270564853 |
|
|
Mar 14 12:54:06 PM PDT 24 |
Mar 14 12:56:34 PM PDT 24 |
13018152544 ps |
T29 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2735155544 |
|
|
Mar 14 12:50:55 PM PDT 24 |
Mar 14 12:51:57 PM PDT 24 |
41322108662 ps |
T244 |
/workspace/coverage/default/22.sram_ctrl_alert_test.1489116501 |
|
|
Mar 14 12:51:37 PM PDT 24 |
Mar 14 12:51:38 PM PDT 24 |
24238626 ps |
T245 |
/workspace/coverage/default/38.sram_ctrl_regwen.213596081 |
|
|
Mar 14 12:53:15 PM PDT 24 |
Mar 14 01:09:15 PM PDT 24 |
3603225834 ps |
T246 |
/workspace/coverage/default/4.sram_ctrl_regwen.2666243104 |
|
|
Mar 14 12:50:33 PM PDT 24 |
Mar 14 01:03:12 PM PDT 24 |
19225428848 ps |
T247 |
/workspace/coverage/default/24.sram_ctrl_bijection.795597869 |
|
|
Mar 14 12:51:43 PM PDT 24 |
Mar 14 01:28:26 PM PDT 24 |
96754718396 ps |
T248 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1359655421 |
|
|
Mar 14 12:52:45 PM PDT 24 |
Mar 14 12:55:10 PM PDT 24 |
2649771639 ps |
T249 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3138165210 |
|
|
Mar 14 12:52:15 PM PDT 24 |
Mar 14 12:53:16 PM PDT 24 |
946362066 ps |
T250 |
/workspace/coverage/default/37.sram_ctrl_smoke.3239167581 |
|
|
Mar 14 12:53:03 PM PDT 24 |
Mar 14 12:53:12 PM PDT 24 |
1122509103 ps |
T251 |
/workspace/coverage/default/14.sram_ctrl_bijection.167222333 |
|
|
Mar 14 12:51:08 PM PDT 24 |
Mar 14 01:05:05 PM PDT 24 |
176495044711 ps |
T252 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2409080287 |
|
|
Mar 14 12:54:59 PM PDT 24 |
Mar 14 12:59:32 PM PDT 24 |
9709322820 ps |
T253 |
/workspace/coverage/default/43.sram_ctrl_stress_all.409786864 |
|
|
Mar 14 12:54:02 PM PDT 24 |
Mar 14 01:51:51 PM PDT 24 |
290299407414 ps |
T254 |
/workspace/coverage/default/12.sram_ctrl_smoke.2753137544 |
|
|
Mar 14 12:51:14 PM PDT 24 |
Mar 14 12:51:35 PM PDT 24 |
1779449499 ps |
T255 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.428581208 |
|
|
Mar 14 12:51:44 PM PDT 24 |
Mar 14 12:55:59 PM PDT 24 |
16424995143 ps |
T256 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2437584412 |
|
|
Mar 14 12:51:21 PM PDT 24 |
Mar 14 12:54:39 PM PDT 24 |
3072171412 ps |
T257 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3293590365 |
|
|
Mar 14 12:50:53 PM PDT 24 |
Mar 14 01:01:11 PM PDT 24 |
40015081033 ps |
T258 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.47792232 |
|
|
Mar 14 12:52:38 PM PDT 24 |
Mar 14 12:53:54 PM PDT 24 |
2981343406 ps |
T259 |
/workspace/coverage/default/22.sram_ctrl_regwen.1262974269 |
|
|
Mar 14 12:51:28 PM PDT 24 |
Mar 14 12:57:30 PM PDT 24 |
5137332260 ps |
T260 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2150965752 |
|
|
Mar 14 12:52:06 PM PDT 24 |
Mar 14 12:53:31 PM PDT 24 |
785032820 ps |
T261 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1237936195 |
|
|
Mar 14 12:51:47 PM PDT 24 |
Mar 14 12:52:13 PM PDT 24 |
1522463117 ps |
T262 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3629933797 |
|
|
Mar 14 12:50:25 PM PDT 24 |
Mar 14 03:04:01 PM PDT 24 |
328894927109 ps |
T263 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.492975648 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 12:56:22 PM PDT 24 |
19179483727 ps |
T264 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1726977335 |
|
|
Mar 14 12:54:50 PM PDT 24 |
Mar 14 12:55:30 PM PDT 24 |
1414899349 ps |
T265 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3344536237 |
|
|
Mar 14 12:53:04 PM PDT 24 |
Mar 14 01:18:11 PM PDT 24 |
21744930175 ps |
T266 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3236388242 |
|
|
Mar 14 12:54:13 PM PDT 24 |
Mar 14 12:54:30 PM PDT 24 |
847045830 ps |
T267 |
/workspace/coverage/default/36.sram_ctrl_partial_access.663201089 |
|
|
Mar 14 12:52:57 PM PDT 24 |
Mar 14 12:54:51 PM PDT 24 |
1764631029 ps |
T268 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.514343158 |
|
|
Mar 14 12:51:42 PM PDT 24 |
Mar 14 01:16:05 PM PDT 24 |
67029316255 ps |
T269 |
/workspace/coverage/default/40.sram_ctrl_executable.1313916434 |
|
|
Mar 14 12:53:37 PM PDT 24 |
Mar 14 01:18:15 PM PDT 24 |
52097263247 ps |
T270 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.17640087 |
|
|
Mar 14 12:52:54 PM PDT 24 |
Mar 14 12:55:25 PM PDT 24 |
19858103859 ps |
T271 |
/workspace/coverage/default/20.sram_ctrl_smoke.1838256947 |
|
|
Mar 14 12:51:17 PM PDT 24 |
Mar 14 12:51:41 PM PDT 24 |
5815563448 ps |
T272 |
/workspace/coverage/default/15.sram_ctrl_executable.1813958076 |
|
|
Mar 14 12:51:12 PM PDT 24 |
Mar 14 01:16:41 PM PDT 24 |
21987681359 ps |
T273 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3997314864 |
|
|
Mar 14 12:53:15 PM PDT 24 |
Mar 14 12:55:44 PM PDT 24 |
3264429557 ps |
T274 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.113768684 |
|
|
Mar 14 12:51:17 PM PDT 24 |
Mar 14 12:56:02 PM PDT 24 |
21725433621 ps |
T275 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3250377191 |
|
|
Mar 14 12:51:09 PM PDT 24 |
Mar 14 12:51:10 PM PDT 24 |
17727778 ps |
T276 |
/workspace/coverage/default/33.sram_ctrl_regwen.3960553724 |
|
|
Mar 14 12:52:37 PM PDT 24 |
Mar 14 01:00:50 PM PDT 24 |
8153591023 ps |
T277 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1985506811 |
|
|
Mar 14 12:51:34 PM PDT 24 |
Mar 14 12:56:35 PM PDT 24 |
34804231849 ps |
T278 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3850490822 |
|
|
Mar 14 12:51:15 PM PDT 24 |
Mar 14 12:57:26 PM PDT 24 |
8054691522 ps |
T279 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3551241098 |
|
|
Mar 14 12:54:47 PM PDT 24 |
Mar 14 12:57:15 PM PDT 24 |
3178876042 ps |
T280 |
/workspace/coverage/default/35.sram_ctrl_executable.1453324091 |
|
|
Mar 14 12:52:46 PM PDT 24 |
Mar 14 12:53:43 PM PDT 24 |
16895622947 ps |
T281 |
/workspace/coverage/default/12.sram_ctrl_stress_all.4073688348 |
|
|
Mar 14 12:51:09 PM PDT 24 |
Mar 14 02:35:29 PM PDT 24 |
1214754552103 ps |
T282 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3148001613 |
|
|
Mar 14 12:51:08 PM PDT 24 |
Mar 14 12:51:08 PM PDT 24 |
94231199 ps |
T283 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3581085775 |
|
|
Mar 14 12:50:53 PM PDT 24 |
Mar 14 12:50:56 PM PDT 24 |
694439449 ps |
T284 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2112129272 |
|
|
Mar 14 12:50:31 PM PDT 24 |
Mar 14 01:12:39 PM PDT 24 |
50527585199 ps |
T285 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2801921431 |
|
|
Mar 14 12:50:55 PM PDT 24 |
Mar 14 12:51:04 PM PDT 24 |
375270310 ps |
T286 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3048919605 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 12:51:08 PM PDT 24 |
346609390 ps |
T287 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3852464995 |
|
|
Mar 14 12:51:10 PM PDT 24 |
Mar 14 12:54:32 PM PDT 24 |
13000340359 ps |
T288 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.198651492 |
|
|
Mar 14 12:54:58 PM PDT 24 |
Mar 14 01:17:28 PM PDT 24 |
32617021710 ps |
T289 |
/workspace/coverage/default/19.sram_ctrl_bijection.357596772 |
|
|
Mar 14 12:51:18 PM PDT 24 |
Mar 14 01:19:05 PM PDT 24 |
24216776777 ps |
T290 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2277992275 |
|
|
Mar 14 12:50:45 PM PDT 24 |
Mar 14 02:02:34 PM PDT 24 |
737538063911 ps |
T291 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.485673659 |
|
|
Mar 14 12:54:13 PM PDT 24 |
Mar 14 12:54:16 PM PDT 24 |
708345116 ps |
T292 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4169249847 |
|
|
Mar 14 12:51:47 PM PDT 24 |
Mar 14 12:51:53 PM PDT 24 |
205213819 ps |
T293 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.651730415 |
|
|
Mar 14 12:51:44 PM PDT 24 |
Mar 14 01:06:12 PM PDT 24 |
35892031253 ps |
T294 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1569870397 |
|
|
Mar 14 12:51:39 PM PDT 24 |
Mar 14 12:52:40 PM PDT 24 |
9893372324 ps |
T295 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3348402669 |
|
|
Mar 14 12:54:00 PM PDT 24 |
Mar 14 12:55:01 PM PDT 24 |
15190313543 ps |
T296 |
/workspace/coverage/default/34.sram_ctrl_alert_test.4089826477 |
|
|
Mar 14 12:52:46 PM PDT 24 |
Mar 14 12:52:47 PM PDT 24 |
12798772 ps |
T297 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.861709340 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 12:53:10 PM PDT 24 |
8967275460 ps |
T298 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1745698421 |
|
|
Mar 14 12:51:01 PM PDT 24 |
Mar 14 12:51:04 PM PDT 24 |
363469848 ps |
T299 |
/workspace/coverage/default/18.sram_ctrl_bijection.1353916623 |
|
|
Mar 14 12:51:14 PM PDT 24 |
Mar 14 01:13:42 PM PDT 24 |
20008452292 ps |
T300 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.334282437 |
|
|
Mar 14 12:51:11 PM PDT 24 |
Mar 14 12:55:17 PM PDT 24 |
16448240480 ps |
T301 |
/workspace/coverage/default/0.sram_ctrl_partial_access.505840467 |
|
|
Mar 14 12:50:24 PM PDT 24 |
Mar 14 12:50:35 PM PDT 24 |
468585130 ps |
T302 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.103716017 |
|
|
Mar 14 12:53:53 PM PDT 24 |
Mar 14 12:54:56 PM PDT 24 |
963745339 ps |
T303 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.52108652 |
|
|
Mar 14 12:53:03 PM PDT 24 |
Mar 14 01:05:38 PM PDT 24 |
32493383686 ps |
T304 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.4257977012 |
|
|
Mar 14 12:51:20 PM PDT 24 |
Mar 14 12:53:58 PM PDT 24 |
9115967972 ps |
T305 |
/workspace/coverage/default/19.sram_ctrl_executable.3332647363 |
|
|
Mar 14 12:51:14 PM PDT 24 |
Mar 14 01:06:34 PM PDT 24 |
12003755996 ps |
T306 |
/workspace/coverage/default/25.sram_ctrl_stress_all.3908232661 |
|
|
Mar 14 12:51:50 PM PDT 24 |
Mar 14 02:09:38 PM PDT 24 |
76105900735 ps |
T307 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3743622333 |
|
|
Mar 14 12:54:12 PM PDT 24 |
Mar 14 12:56:45 PM PDT 24 |
15586615034 ps |
T308 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1519013848 |
|
|
Mar 14 12:52:05 PM PDT 24 |
Mar 14 12:58:26 PM PDT 24 |
117267882551 ps |
T309 |
/workspace/coverage/default/24.sram_ctrl_smoke.2075899722 |
|
|
Mar 14 12:51:35 PM PDT 24 |
Mar 14 12:51:57 PM PDT 24 |
5814866444 ps |
T310 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2978866803 |
|
|
Mar 14 12:50:49 PM PDT 24 |
Mar 14 12:51:44 PM PDT 24 |
14687185561 ps |
T311 |
/workspace/coverage/default/43.sram_ctrl_smoke.3444765603 |
|
|
Mar 14 12:53:54 PM PDT 24 |
Mar 14 12:54:01 PM PDT 24 |
2714130795 ps |
T312 |
/workspace/coverage/default/28.sram_ctrl_alert_test.511002676 |
|
|
Mar 14 12:52:04 PM PDT 24 |
Mar 14 12:52:06 PM PDT 24 |
16997186 ps |
T313 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2910370784 |
|
|
Mar 14 12:54:03 PM PDT 24 |
Mar 14 12:54:04 PM PDT 24 |
104602128 ps |
T314 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.1324331006 |
|
|
Mar 14 12:53:15 PM PDT 24 |
Mar 14 12:53:19 PM PDT 24 |
1412514222 ps |
T315 |
/workspace/coverage/default/30.sram_ctrl_partial_access.349996102 |
|
|
Mar 14 12:52:14 PM PDT 24 |
Mar 14 12:52:35 PM PDT 24 |
959194813 ps |
T316 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4078860670 |
|
|
Mar 14 12:50:51 PM PDT 24 |
Mar 14 12:51:31 PM PDT 24 |
5419559371 ps |