Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	141470811	1			T1	365941		T2	61744		T3	47717
triple_byte_access	2767163	1			T1	7265		T2	1261		T3	42847
halfword_access	4236074	1			T1	10854		T2	1820		T3	64204
byte_access	5909991	1			T1	14617		T2	2403		T3	85583
zero_access	1764492	1			T1	3566		T2	585		T3	21088

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77882099

1

T1

203102

T2

36334

T3

130562

auto[1]

78266432

1

T1

199141

T2

31479

T3

130877

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70416740	1			T1	184825		T2	33126		T3	23848
auto[0]	triple_byte_access	1325881	1			T1	3674		T2	668		T3	21482
auto[0]	halfword_access	2072913	1			T1	5495		T2	1012		T3	32182
auto[0]	byte_access	3023090	1			T1	7331		T2	1220		T3	42687
auto[0]	zero_access	1043475	1			T1	1777		T2	308		T3	10363
auto[1]	word_access	71054071	1			T1	181116		T2	28618		T3	23869
auto[1]	triple_byte_access	1441282	1			T1	3591		T2	593		T3	21365
auto[1]	halfword_access	2163161	1			T1	5359		T2	808		T3	32022
auto[1]	byte_access	2886901	1			T1	7286		T2	1183		T3	42896
auto[1]	zero_access	721017	1			T1	1789		T2	277		T3	10725