Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	338542708	1			T1	7652		T2	12776		T3	196606
instr_valid_dis	295486822	1			T1	7652		T2	12776		T3	196606
instr_en	30877938	1			T8	118676		T27	79962		T44	40084

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12440578	1			T8	145576		T27	15894		T31	105190
sram_ifetch_valid_disable	296921459	1			T1	7652		T2	12776		T3	196606
sram_ifetch_enable	29180671	1			T8	460672		T27	49752		T32	176964

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	338542708	1			T1	7652		T2	12776		T3	196606
hw_debug_en_valid_off	297225275	1			T1	7652		T2	12776		T3	196606
hw_debug_en_on	25769727	1			T8	496720		T27	18488		T31	105190

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	296921459	1			T1	7652		T2	12776		T3	196606
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	278439146	1			T1	7652		T2	12776		T3	196606
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13355755	1			T8	13548		T27	14316		T32	100806
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4550650	1			T8	43780		T44	40084		T28	7364
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1463210	1			T8	43780		T116	14082		T124	25846
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1975040	1			T44	40084		T116	3434		T123	57424
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3726752	1			T8	56864		T31	105190		T117	4596
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1284928	1			T8	40616		T31	105190		T116	33094
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1182052	1			T8	16248		T117	4596		T116	47684
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13255654	1			T8	224774		T32	96730		T33	187540
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3805648	1			T8	187018		T28	104098		T116	16386
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6378314	1			T8	13548		T32	96730		T33	187540

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11351393	1			T8	62520		T27	49752		T32	28640
lc_exec_en	8787321	1			T8	215082		T27	18488		T32	92890
valid_exec_dis	290812111	1			T1	7652		T2	12776		T3	196606
invalid_exec_dis	41621249	1			T8	606248		T27	65646		T31	105190