Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.41 100.00 97.91 100.00 100.00 99.72 99.70 98.52


Total tests in report: 1035
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.41 83.41 97.39 97.39 78.80 78.80 83.59 83.59 100.00 100.00 91.83 91.83 94.95 94.95 37.29 37.29 /workspace/coverage/default/8.sram_ctrl_lc_escalation.310041631
91.49 8.08 98.97 1.59 89.82 11.02 93.18 9.59 100.00 0.00 95.49 3.66 96.73 1.78 66.23 28.94 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3878097422
94.13 2.64 99.53 0.56 93.44 3.63 94.25 1.07 100.00 0.00 97.75 2.25 96.73 0.00 77.18 10.95 /workspace/coverage/default/24.sram_ctrl_stress_all.2025253389
95.40 1.28 99.53 0.00 93.44 0.00 95.95 1.70 100.00 0.00 97.75 0.00 96.73 0.00 84.42 7.24 /workspace/coverage/default/8.sram_ctrl_multiple_keys.1424760682
96.45 1.05 99.72 0.19 94.14 0.70 96.16 0.21 100.00 0.00 98.59 0.85 96.73 0.00 89.80 5.38 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3860996138
97.27 0.82 99.91 0.19 96.23 2.09 96.88 0.71 100.00 0.00 99.44 0.85 97.33 0.59 91.09 1.30 /workspace/coverage/default/1.sram_ctrl_sec_cm.2599736386
97.71 0.45 99.91 0.00 96.23 0.00 96.88 0.00 100.00 0.00 99.44 0.00 97.47 0.15 94.06 2.97 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1850456605
98.07 0.36 99.91 0.00 96.51 0.28 98.37 1.49 100.00 0.00 99.44 0.00 98.22 0.74 94.06 0.00 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4018396532
98.39 0.32 99.91 0.00 96.51 0.00 98.93 0.57 100.00 0.00 99.44 0.00 98.22 0.00 95.73 1.67 /workspace/coverage/default/22.sram_ctrl_stress_all.2480686730
98.59 0.20 99.91 0.00 96.79 0.28 99.01 0.07 100.00 0.00 99.44 0.00 99.26 1.04 95.73 0.00 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1195271672
98.75 0.16 99.91 0.00 97.21 0.42 99.08 0.07 100.00 0.00 99.72 0.28 99.26 0.00 96.10 0.37 /workspace/coverage/default/3.sram_ctrl_stress_all.3586735167
98.89 0.14 100.00 0.09 97.21 0.00 99.79 0.71 100.00 0.00 99.72 0.00 99.26 0.00 96.29 0.19 /workspace/coverage/default/24.sram_ctrl_ram_cfg.4240973108
99.00 0.11 100.00 0.00 97.63 0.42 99.93 0.14 100.00 0.00 99.72 0.00 99.26 0.00 96.47 0.19 /workspace/coverage/default/44.sram_ctrl_alert_test.2379704991
99.08 0.08 100.00 0.00 97.63 0.00 99.93 0.00 100.00 0.00 99.72 0.00 99.26 0.00 97.03 0.56 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.242439066
99.16 0.08 100.00 0.00 97.63 0.00 99.93 0.00 100.00 0.00 99.72 0.00 99.26 0.00 97.59 0.56 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1637851101
99.21 0.05 100.00 0.00 97.63 0.00 99.93 0.00 100.00 0.00 99.72 0.00 99.26 0.00 97.96 0.37 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1861414954
99.27 0.05 100.00 0.00 97.63 0.00 99.93 0.00 100.00 0.00 99.72 0.00 99.26 0.00 98.33 0.37 /workspace/coverage/default/48.sram_ctrl_stress_all.2278163967
99.31 0.04 100.00 0.00 97.63 0.00 99.93 0.00 100.00 0.00 99.72 0.00 99.55 0.30 98.33 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.316127233
99.34 0.03 100.00 0.00 97.63 0.00 100.00 0.07 100.00 0.00 99.72 0.00 99.70 0.15 98.33 0.00 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.680030270
99.37 0.03 100.00 0.00 97.63 0.00 100.00 0.00 100.00 0.00 99.72 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.626827313

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.963387964
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4189903538
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3374012892
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1780207942
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2067758529
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3266560593
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1641141998
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2699811154
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3876433279
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3800290913
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.753430079
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.414744065
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.928440636
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1673789302
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3006841958
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4265574740
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3848773344
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1260588096
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1809103141
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3040502454
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1212309538
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1703962411
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3393352611
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2968274597
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3897672407
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1609882713
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4272716936
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2458332352
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2021906225
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.563764170
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1132513381
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3498027771
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2053718404
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3112448968
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1147345825
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1362861638
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3851518416
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4221522889
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2568058352
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3422405881
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3289991264
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2842868787
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3655655446
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2587049171
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2193252556
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2806324457
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1178179418
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.682706164
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1394264722
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.623364177
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3725725497
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.395197659
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.339435688
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3255963278
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.532378679
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.178291799
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.189759605
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3426311369
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.65253012
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3613957587
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2846939222
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.497594891
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2329759291
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3191961323
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.455003872
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.461989358
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.996926161
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.154123289
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1930973894
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.358600256
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2105449743
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3446916548
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2478132555
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3068540550
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2530451632
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3162999152
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2090895528
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2284704939
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.749355322
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1014448007
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3848596694
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3079863531
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3135490227
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2267427500
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3976978425
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2526100880
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2680286845
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4176077316
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1744933710
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1211217746
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2542728465
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1150777984
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.264863133
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3022538236
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1115405377
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1912062575
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.503986672
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4030944333
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3722601722
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1849094306
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1481138207
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1305914969
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.648144183
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2397634483
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2805375666
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4057129399
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.765592562
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.273816052
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4033016957
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2836884110
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2582624664
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1000428462
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1898015198
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1381596808
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.953306894
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.872615938
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2066497801
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2303986411
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.21351457
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3143068999
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1880107631
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2366514305
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3486565588
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.811452082
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1494698502
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2249690765
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3118225071
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1160758494
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2054982418
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.680664237
/workspace/coverage/default/0.sram_ctrl_alert_test.1104417290
/workspace/coverage/default/0.sram_ctrl_bijection.4111683931
/workspace/coverage/default/0.sram_ctrl_executable.3612296145
/workspace/coverage/default/0.sram_ctrl_lc_escalation.963386635
/workspace/coverage/default/0.sram_ctrl_max_throughput.4080736380
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.967813017
/workspace/coverage/default/0.sram_ctrl_mem_walk.3130956206
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2014484180
/workspace/coverage/default/0.sram_ctrl_partial_access.155930200
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1357102042
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2871795957
/workspace/coverage/default/0.sram_ctrl_regwen.4003291729
/workspace/coverage/default/0.sram_ctrl_sec_cm.2341109096
/workspace/coverage/default/0.sram_ctrl_smoke.1725328594
/workspace/coverage/default/0.sram_ctrl_stress_all.2714831024
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.375271665
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2525945115
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.134938073
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2839608614
/workspace/coverage/default/1.sram_ctrl_alert_test.2467940803
/workspace/coverage/default/1.sram_ctrl_bijection.3208711933
/workspace/coverage/default/1.sram_ctrl_executable.2332249805
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2845888652
/workspace/coverage/default/1.sram_ctrl_max_throughput.1906735800
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.429978160
/workspace/coverage/default/1.sram_ctrl_mem_walk.2762665325
/workspace/coverage/default/1.sram_ctrl_partial_access.1807557957
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.186600799
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2923668012
/workspace/coverage/default/1.sram_ctrl_regwen.799896415
/workspace/coverage/default/1.sram_ctrl_smoke.3064908430
/workspace/coverage/default/1.sram_ctrl_stress_all.1052263451
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.887324382
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2109976
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2646248820
/workspace/coverage/default/10.sram_ctrl_alert_test.3066035087
/workspace/coverage/default/10.sram_ctrl_bijection.1000014756
/workspace/coverage/default/10.sram_ctrl_executable.1147763974
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2443895010
/workspace/coverage/default/10.sram_ctrl_max_throughput.1669135891
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2178437381
/workspace/coverage/default/10.sram_ctrl_mem_walk.622583496
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1277335366
/workspace/coverage/default/10.sram_ctrl_partial_access.1676414829
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2850983553
/workspace/coverage/default/10.sram_ctrl_ram_cfg.4110548932
/workspace/coverage/default/10.sram_ctrl_regwen.3651456994
/workspace/coverage/default/10.sram_ctrl_smoke.3815315550
/workspace/coverage/default/10.sram_ctrl_stress_all.1856715617
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1704154575
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2960893886
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.731791315
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2363228042
/workspace/coverage/default/11.sram_ctrl_alert_test.811611286
/workspace/coverage/default/11.sram_ctrl_executable.3436044485
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4020214996
/workspace/coverage/default/11.sram_ctrl_max_throughput.2278503263
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2410684489
/workspace/coverage/default/11.sram_ctrl_mem_walk.3075047571
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4232670854
/workspace/coverage/default/11.sram_ctrl_partial_access.2081247421
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.5957978
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2417462753
/workspace/coverage/default/11.sram_ctrl_regwen.987532902
/workspace/coverage/default/11.sram_ctrl_smoke.3958445009
/workspace/coverage/default/11.sram_ctrl_stress_all.3919375926
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3307293912
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.550361523
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1706945533
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2502907179
/workspace/coverage/default/12.sram_ctrl_alert_test.3222337504
/workspace/coverage/default/12.sram_ctrl_bijection.3086493890
/workspace/coverage/default/12.sram_ctrl_executable.1513164708
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/workspace/coverage/default/42.sram_ctrl_regwen.2726968104
/workspace/coverage/default/42.sram_ctrl_smoke.309540500
/workspace/coverage/default/42.sram_ctrl_stress_all.881948111
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.62848067
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.4061896570
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2458249925
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2407750269
/workspace/coverage/default/43.sram_ctrl_alert_test.2601140721
/workspace/coverage/default/43.sram_ctrl_bijection.3229015247
/workspace/coverage/default/43.sram_ctrl_executable.3564916546
/workspace/coverage/default/43.sram_ctrl_lc_escalation.418005214
/workspace/coverage/default/43.sram_ctrl_max_throughput.3917253254
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4279768771
/workspace/coverage/default/43.sram_ctrl_mem_walk.3945540172
/workspace/coverage/default/43.sram_ctrl_multiple_keys.376433794
/workspace/coverage/default/43.sram_ctrl_partial_access.3064314977
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4153763366
/workspace/coverage/default/43.sram_ctrl_ram_cfg.546216981
/workspace/coverage/default/43.sram_ctrl_regwen.3084810071
/workspace/coverage/default/43.sram_ctrl_smoke.3555611197
/workspace/coverage/default/43.sram_ctrl_stress_all.1792665995
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.422402299
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3122220704
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1450356193
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.22475521
/workspace/coverage/default/44.sram_ctrl_bijection.1037888177
/workspace/coverage/default/44.sram_ctrl_executable.3479260977
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1632658013
/workspace/coverage/default/44.sram_ctrl_max_throughput.3337140016
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2056847943
/workspace/coverage/default/44.sram_ctrl_mem_walk.498135719
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1711035551
/workspace/coverage/default/44.sram_ctrl_partial_access.2788856076
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1590290027
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1724223813
/workspace/coverage/default/44.sram_ctrl_regwen.1897503794
/workspace/coverage/default/44.sram_ctrl_smoke.3719776179
/workspace/coverage/default/44.sram_ctrl_stress_all.1792486615
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2563625953
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2554446593
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.655817620
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3285058481
/workspace/coverage/default/45.sram_ctrl_alert_test.1720636860
/workspace/coverage/default/45.sram_ctrl_bijection.2577624246
/workspace/coverage/default/45.sram_ctrl_executable.933812988
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3980593272
/workspace/coverage/default/45.sram_ctrl_max_throughput.3875576527
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3409551679
/workspace/coverage/default/45.sram_ctrl_mem_walk.1566100234
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2977913202
/workspace/coverage/default/45.sram_ctrl_partial_access.4275921655
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.565695505
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1441663212
/workspace/coverage/default/45.sram_ctrl_regwen.1096761635
/workspace/coverage/default/45.sram_ctrl_smoke.4195079510
/workspace/coverage/default/45.sram_ctrl_stress_all.2053174787
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2294953728
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3745932168
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3532946330
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3910128215
/workspace/coverage/default/46.sram_ctrl_alert_test.3210332110
/workspace/coverage/default/46.sram_ctrl_bijection.2948474206
/workspace/coverage/default/46.sram_ctrl_executable.1519046554
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3402336197
/workspace/coverage/default/46.sram_ctrl_max_throughput.2352368612
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.708576225
/workspace/coverage/default/46.sram_ctrl_mem_walk.3712182767
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3450139395
/workspace/coverage/default/46.sram_ctrl_partial_access.3234234635
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.489410853
/workspace/coverage/default/46.sram_ctrl_ram_cfg.332922073
/workspace/coverage/default/46.sram_ctrl_regwen.3080561671
/workspace/coverage/default/46.sram_ctrl_smoke.2131475514
/workspace/coverage/default/46.sram_ctrl_stress_all.2949816956
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1530574479
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.683091360
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2843477256
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3500009604
/workspace/coverage/default/47.sram_ctrl_alert_test.2150526615
/workspace/coverage/default/47.sram_ctrl_bijection.2427471349
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3280564275
/workspace/coverage/default/47.sram_ctrl_max_throughput.113709540
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1277708049
/workspace/coverage/default/47.sram_ctrl_mem_walk.4059217850
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4000838419
/workspace/coverage/default/47.sram_ctrl_partial_access.914598871
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1689895085
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3909761559
/workspace/coverage/default/47.sram_ctrl_regwen.1016061861
/workspace/coverage/default/47.sram_ctrl_smoke.3488470215
/workspace/coverage/default/47.sram_ctrl_stress_all.1741248837
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1041266266
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.913849549
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1186315290
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.372712675
/workspace/coverage/default/48.sram_ctrl_alert_test.1160673522
/workspace/coverage/default/48.sram_ctrl_bijection.2352114741
/workspace/coverage/default/48.sram_ctrl_executable.1458726381
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1801788306
/workspace/coverage/default/48.sram_ctrl_max_throughput.2164056778
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2402344069
/workspace/coverage/default/48.sram_ctrl_mem_walk.1566526379
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1375013332
/workspace/coverage/default/48.sram_ctrl_partial_access.1092732841
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1039513015
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3280668905
/workspace/coverage/default/48.sram_ctrl_regwen.3322397727
/workspace/coverage/default/48.sram_ctrl_smoke.3644313871
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.807287775
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2186340317
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.187358126
/workspace/coverage/default/49.sram_ctrl_alert_test.1169891645
/workspace/coverage/default/49.sram_ctrl_bijection.3217735258
/workspace/coverage/default/49.sram_ctrl_executable.1176970690
/workspace/coverage/default/49.sram_ctrl_lc_escalation.24077296
/workspace/coverage/default/49.sram_ctrl_max_throughput.743462332
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1699269579
/workspace/coverage/default/49.sram_ctrl_mem_walk.4213674530
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2908320194
/workspace/coverage/default/49.sram_ctrl_partial_access.1806271185
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.629971610
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3640322324
/workspace/coverage/default/49.sram_ctrl_regwen.2033950715
/workspace/coverage/default/49.sram_ctrl_smoke.3584919477
/workspace/coverage/default/49.sram_ctrl_stress_all.1162506239
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2936191241
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1102601680
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3898711747
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4198136994
/workspace/coverage/default/5.sram_ctrl_alert_test.4140879195
/workspace/coverage/default/5.sram_ctrl_bijection.211501794
/workspace/coverage/default/5.sram_ctrl_executable.242828163
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2062686391
/workspace/coverage/default/5.sram_ctrl_max_throughput.2463194129
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.715976788
/workspace/coverage/default/5.sram_ctrl_mem_walk.1602299910
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2493949247
/workspace/coverage/default/5.sram_ctrl_partial_access.1686625759
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2628993574
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1885860112
/workspace/coverage/default/5.sram_ctrl_regwen.2446467781
/workspace/coverage/default/5.sram_ctrl_smoke.1070319558
/workspace/coverage/default/5.sram_ctrl_stress_all.2095031310
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4231530631
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2498116798
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2933185899
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2176760122
/workspace/coverage/default/6.sram_ctrl_alert_test.2385440741
/workspace/coverage/default/6.sram_ctrl_bijection.3865107072
/workspace/coverage/default/6.sram_ctrl_executable.119635930
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2263984322
/workspace/coverage/default/6.sram_ctrl_max_throughput.1336299604
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1090373244
/workspace/coverage/default/6.sram_ctrl_mem_walk.469187832
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1382678246
/workspace/coverage/default/6.sram_ctrl_partial_access.968797797
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3417402028
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2286548817
/workspace/coverage/default/6.sram_ctrl_regwen.4017989501
/workspace/coverage/default/6.sram_ctrl_smoke.416042545
/workspace/coverage/default/6.sram_ctrl_stress_all.3985221439
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3268206990
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3628413806
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3906901657
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.867201389
/workspace/coverage/default/7.sram_ctrl_alert_test.3551470065
/workspace/coverage/default/7.sram_ctrl_bijection.3742858725
/workspace/coverage/default/7.sram_ctrl_executable.3234151743
/workspace/coverage/default/7.sram_ctrl_lc_escalation.4126109667
/workspace/coverage/default/7.sram_ctrl_max_throughput.2194169526
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3958843077
/workspace/coverage/default/7.sram_ctrl_mem_walk.350102745
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2423755251
/workspace/coverage/default/7.sram_ctrl_partial_access.152079633
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.287399135
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2038732229
/workspace/coverage/default/7.sram_ctrl_regwen.1400031174
/workspace/coverage/default/7.sram_ctrl_smoke.22456212
/workspace/coverage/default/7.sram_ctrl_stress_all.2528921977
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3095782935
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2843808128
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3547422576
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1120744247
/workspace/coverage/default/8.sram_ctrl_alert_test.860156656
/workspace/coverage/default/8.sram_ctrl_bijection.1170241803
/workspace/coverage/default/8.sram_ctrl_executable.812734510
/workspace/coverage/default/8.sram_ctrl_max_throughput.4002529361
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1245923938
/workspace/coverage/default/8.sram_ctrl_mem_walk.1578896105
/workspace/coverage/default/8.sram_ctrl_partial_access.2773671402
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4185667536
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3577473342
/workspace/coverage/default/8.sram_ctrl_regwen.1657054600
/workspace/coverage/default/8.sram_ctrl_smoke.1628436891
/workspace/coverage/default/8.sram_ctrl_stress_all.2950218901
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4184353204
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.4062335235
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2293648691
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2379777493
/workspace/coverage/default/9.sram_ctrl_alert_test.3612784986
/workspace/coverage/default/9.sram_ctrl_bijection.390657660
/workspace/coverage/default/9.sram_ctrl_executable.2334646781
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2567942877
/workspace/coverage/default/9.sram_ctrl_max_throughput.3584167563
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2334330460
/workspace/coverage/default/9.sram_ctrl_mem_walk.3663964640
/workspace/coverage/default/9.sram_ctrl_multiple_keys.930485682
/workspace/coverage/default/9.sram_ctrl_partial_access.4085206603
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3902069048
/workspace/coverage/default/9.sram_ctrl_ram_cfg.575337992
/workspace/coverage/default/9.sram_ctrl_regwen.1850239003
/workspace/coverage/default/9.sram_ctrl_smoke.433874426
/workspace/coverage/default/9.sram_ctrl_stress_all.1179400101
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2546558163
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4186490791
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3437110704



Total test records in report: 1035
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.sram_ctrl_partial_access.3449986127 Mar 17 03:06:25 PM PDT 24 Mar 17 03:06:50 PM PDT 24 950963391 ps
T2 /workspace/coverage/default/47.sram_ctrl_smoke.3488470215 Mar 17 03:11:50 PM PDT 24 Mar 17 03:12:08 PM PDT 24 2266652349 ps
T3 /workspace/coverage/default/47.sram_ctrl_mem_walk.4059217850 Mar 17 03:12:01 PM PDT 24 Mar 17 03:14:04 PM PDT 24 4301345718 ps
T5 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3878097422 Mar 17 03:06:50 PM PDT 24 Mar 17 03:07:05 PM PDT 24 437110479 ps
T9 /workspace/coverage/default/5.sram_ctrl_alert_test.4140879195 Mar 17 03:06:06 PM PDT 24 Mar 17 03:06:07 PM PDT 24 31320957 ps
T4 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1878688908 Mar 17 03:09:56 PM PDT 24 Mar 17 03:10:03 PM PDT 24 704444577 ps
T10 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1850456605 Mar 17 03:07:43 PM PDT 24 Mar 17 03:14:08 PM PDT 24 273029629398 ps
T11 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.614396203 Mar 17 03:08:03 PM PDT 24 Mar 17 03:09:21 PM PDT 24 2346776811 ps
T12 /workspace/coverage/default/29.sram_ctrl_alert_test.190319406 Mar 17 03:08:26 PM PDT 24 Mar 17 03:08:27 PM PDT 24 12388981 ps
T6 /workspace/coverage/default/8.sram_ctrl_lc_escalation.310041631 Mar 17 03:06:16 PM PDT 24 Mar 17 03:06:44 PM PDT 24 19624067736 ps
T13 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4161572620 Mar 17 03:06:05 PM PDT 24 Mar 17 03:06:49 PM PDT 24 1506077969 ps
T14 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4018396532 Mar 17 03:12:23 PM PDT 24 Mar 17 03:17:10 PM PDT 24 6177072735 ps
T15 /workspace/coverage/default/0.sram_ctrl_mem_walk.3130956206 Mar 17 03:05:56 PM PDT 24 Mar 17 03:07:58 PM PDT 24 14092062270 ps
T21 /workspace/coverage/default/24.sram_ctrl_bijection.1527399772 Mar 17 03:07:32 PM PDT 24 Mar 17 03:39:45 PM PDT 24 111472239720 ps
T16 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2215519527 Mar 17 03:09:07 PM PDT 24 Mar 17 03:11:33 PM PDT 24 8868599379 ps
T26 /workspace/coverage/default/22.sram_ctrl_bijection.2542119615 Mar 17 03:07:18 PM PDT 24 Mar 17 03:27:19 PM PDT 24 231088231152 ps
T17 /workspace/coverage/default/40.sram_ctrl_partial_access.664183658 Mar 17 03:10:27 PM PDT 24 Mar 17 03:10:50 PM PDT 24 2917385216 ps
T45 /workspace/coverage/default/8.sram_ctrl_multiple_keys.1424760682 Mar 17 03:06:17 PM PDT 24 Mar 17 03:25:34 PM PDT 24 28649897092 ps
T55 /workspace/coverage/default/17.sram_ctrl_partial_access.1668926587 Mar 17 03:06:46 PM PDT 24 Mar 17 03:09:54 PM PDT 24 1322264654 ps
T7 /workspace/coverage/default/33.sram_ctrl_lc_escalation.2580268128 Mar 17 03:09:02 PM PDT 24 Mar 17 03:09:52 PM PDT 24 15321304442 ps
T138 /workspace/coverage/default/17.sram_ctrl_bijection.3983920499 Mar 17 03:06:45 PM PDT 24 Mar 17 03:34:59 PM PDT 24 109774162963 ps
T131 /workspace/coverage/default/7.sram_ctrl_bijection.3742858725 Mar 17 03:06:14 PM PDT 24 Mar 17 03:14:51 PM PDT 24 47457396512 ps
T8 /workspace/coverage/default/24.sram_ctrl_stress_all.2025253389 Mar 17 03:07:45 PM PDT 24 Mar 17 04:52:08 PM PDT 24 243331535981 ps
T139 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2293648691 Mar 17 03:06:17 PM PDT 24 Mar 17 03:06:46 PM PDT 24 2978324117 ps
T66 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.297179804 Mar 17 03:07:05 PM PDT 24 Mar 17 03:08:27 PM PDT 24 10630970297 ps
T87 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2377209118 Mar 17 03:06:03 PM PDT 24 Mar 17 03:14:02 PM PDT 24 80133168082 ps
T34 /workspace/coverage/default/47.sram_ctrl_ram_cfg.3909761559 Mar 17 03:12:01 PM PDT 24 Mar 17 03:12:05 PM PDT 24 1342621858 ps
T18 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2936191241 Mar 17 03:12:24 PM PDT 24 Mar 17 03:12:30 PM PDT 24 140521529 ps
T140 /workspace/coverage/default/10.sram_ctrl_smoke.3815315550 Mar 17 03:06:26 PM PDT 24 Mar 17 03:06:51 PM PDT 24 10733336776 ps
T133 /workspace/coverage/default/44.sram_ctrl_multiple_keys.1711035551 Mar 17 03:11:13 PM PDT 24 Mar 17 03:27:40 PM PDT 24 6682850611 ps
T22 /workspace/coverage/default/44.sram_ctrl_alert_test.2379704991 Mar 17 03:11:26 PM PDT 24 Mar 17 03:11:27 PM PDT 24 36282751 ps
T69 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.429978160 Mar 17 03:06:00 PM PDT 24 Mar 17 03:08:18 PM PDT 24 19605736351 ps
T141 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2933185899 Mar 17 03:06:09 PM PDT 24 Mar 17 03:06:40 PM PDT 24 722817082 ps
T142 /workspace/coverage/default/45.sram_ctrl_smoke.4195079510 Mar 17 03:11:26 PM PDT 24 Mar 17 03:11:49 PM PDT 24 1402619303 ps
T135 /workspace/coverage/default/33.sram_ctrl_bijection.2996564647 Mar 17 03:08:58 PM PDT 24 Mar 17 03:18:13 PM PDT 24 29294707534 ps
T29 /workspace/coverage/default/36.sram_ctrl_lc_escalation.2667243060 Mar 17 03:09:54 PM PDT 24 Mar 17 03:10:20 PM PDT 24 4309739306 ps
T134 /workspace/coverage/default/3.sram_ctrl_bijection.3218336565 Mar 17 03:06:05 PM PDT 24 Mar 17 03:30:06 PM PDT 24 42707292746 ps
T27 /workspace/coverage/default/8.sram_ctrl_regwen.1657054600 Mar 17 03:06:14 PM PDT 24 Mar 17 03:12:18 PM PDT 24 53698721735 ps
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T88 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2622106510 Mar 17 03:07:00 PM PDT 24 Mar 17 03:09:04 PM PDT 24 2483785671 ps
T89 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.550361523 Mar 17 03:06:26 PM PDT 24 Mar 17 03:12:51 PM PDT 24 10087158095 ps
T23 /workspace/coverage/default/3.sram_ctrl_sec_cm.592098965 Mar 17 03:06:08 PM PDT 24 Mar 17 03:06:10 PM PDT 24 326835005 ps
T19 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.680030270 Mar 17 03:07:34 PM PDT 24 Mar 17 03:16:12 PM PDT 24 10005227381 ps
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T42 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.708576225 Mar 17 03:12:07 PM PDT 24 Mar 17 03:14:10 PM PDT 24 3197436508 ps
T43 /workspace/coverage/default/42.sram_ctrl_max_throughput.2080224454 Mar 17 03:10:53 PM PDT 24 Mar 17 03:11:45 PM PDT 24 3063898131 ps
T30 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4066938837 Mar 17 03:09:54 PM PDT 24 Mar 17 03:11:42 PM PDT 24 1034832307 ps
T44 /workspace/coverage/default/20.sram_ctrl_executable.3082956867 Mar 17 03:07:05 PM PDT 24 Mar 17 03:07:38 PM PDT 24 1827225750 ps
T144 /workspace/coverage/default/15.sram_ctrl_max_throughput.165147954 Mar 17 03:06:35 PM PDT 24 Mar 17 03:07:39 PM PDT 24 791547218 ps
T90 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.5957978 Mar 17 03:06:24 PM PDT 24 Mar 17 03:10:19 PM PDT 24 4097336996 ps
T136 /workspace/coverage/default/5.sram_ctrl_bijection.211501794 Mar 17 03:06:10 PM PDT 24 Mar 17 03:25:03 PM PDT 24 51463555699 ps
T35 /workspace/coverage/default/36.sram_ctrl_ram_cfg.2490063353 Mar 17 03:09:55 PM PDT 24 Mar 17 03:09:58 PM PDT 24 349302399 ps
T137 /workspace/coverage/default/1.sram_ctrl_max_throughput.1906735800 Mar 17 03:05:56 PM PDT 24 Mar 17 03:08:10 PM PDT 24 5830559774 ps
T32 /workspace/coverage/default/44.sram_ctrl_executable.3479260977 Mar 17 03:11:15 PM PDT 24 Mar 17 03:34:59 PM PDT 24 18007249980 ps
T54 /workspace/coverage/default/16.sram_ctrl_lc_escalation.1259136672 Mar 17 03:06:41 PM PDT 24 Mar 17 03:07:22 PM PDT 24 6469470046 ps
T47 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1637851101 Mar 17 03:05:57 PM PDT 24 Mar 17 03:06:16 PM PDT 24 5124642529 ps
T36 /workspace/coverage/default/9.sram_ctrl_ram_cfg.575337992 Mar 17 03:06:21 PM PDT 24 Mar 17 03:06:24 PM PDT 24 2235170406 ps
T145 /workspace/coverage/default/33.sram_ctrl_smoke.3392861237 Mar 17 03:08:59 PM PDT 24 Mar 17 03:10:49 PM PDT 24 781008620 ps
T146 /workspace/coverage/default/17.sram_ctrl_multiple_keys.4151504483 Mar 17 03:06:45 PM PDT 24 Mar 17 03:07:43 PM PDT 24 14418510154 ps
T33 /workspace/coverage/default/31.sram_ctrl_regwen.1006024163 Mar 17 03:08:44 PM PDT 24 Mar 17 03:29:13 PM PDT 24 14352138207 ps
T147 /workspace/coverage/default/4.sram_ctrl_mem_walk.3222027229 Mar 17 03:06:02 PM PDT 24 Mar 17 03:08:44 PM PDT 24 38323126309 ps
T70 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1699269579 Mar 17 03:12:22 PM PDT 24 Mar 17 03:13:33 PM PDT 24 10453328733 ps
T148 /workspace/coverage/default/10.sram_ctrl_mem_walk.622583496 Mar 17 03:06:19 PM PDT 24 Mar 17 03:08:16 PM PDT 24 2066546999 ps
T149 /workspace/coverage/default/8.sram_ctrl_max_throughput.4002529361 Mar 17 03:06:16 PM PDT 24 Mar 17 03:06:51 PM PDT 24 1489417987 ps
T71 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3148815873 Mar 17 03:06:08 PM PDT 24 Mar 17 03:07:14 PM PDT 24 1011172638 ps
T117 /workspace/coverage/default/4.sram_ctrl_executable.1864660959 Mar 17 03:06:07 PM PDT 24 Mar 17 03:11:18 PM PDT 24 13235716709 ps
T150 /workspace/coverage/default/48.sram_ctrl_ram_cfg.3280668905 Mar 17 03:12:16 PM PDT 24 Mar 17 03:12:20 PM PDT 24 1423954375 ps
T24 /workspace/coverage/default/1.sram_ctrl_sec_cm.2599736386 Mar 17 03:05:58 PM PDT 24 Mar 17 03:06:01 PM PDT 24 1170735385 ps
T151 /workspace/coverage/default/24.sram_ctrl_ram_cfg.4240973108 Mar 17 03:07:34 PM PDT 24 Mar 17 03:07:38 PM PDT 24 1350422518 ps
T72 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2398299977 Mar 17 03:09:47 PM PDT 24 Mar 17 03:11:48 PM PDT 24 3164470698 ps
T28 /workspace/coverage/default/38.sram_ctrl_stress_all.1253655669 Mar 17 03:10:09 PM PDT 24 Mar 17 05:06:22 PM PDT 24 1162316400404 ps
T82 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.781273849 Mar 17 03:05:58 PM PDT 24 Mar 17 03:07:03 PM PDT 24 1327200645 ps
T128 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3682315028 Mar 17 03:10:37 PM PDT 24 Mar 17 03:11:57 PM PDT 24 2669380008 ps
T20 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3380844516 Mar 17 03:07:28 PM PDT 24 Mar 17 03:41:16 PM PDT 24 21670737906 ps
T152 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.394145604 Mar 17 03:06:29 PM PDT 24 Mar 17 03:10:06 PM PDT 24 82326110339 ps
T153 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2966170317 Mar 17 03:06:30 PM PDT 24 Mar 17 03:08:34 PM PDT 24 838277924 ps
T116 /workspace/coverage/default/43.sram_ctrl_stress_all.1792665995 Mar 17 03:11:12 PM PDT 24 Mar 17 04:00:47 PM PDT 24 30226872861 ps
T154 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3720198667 Mar 17 03:05:58 PM PDT 24 Mar 17 03:11:17 PM PDT 24 10616682978 ps
T155 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2843808128 Mar 17 03:06:15 PM PDT 24 Mar 17 03:10:07 PM PDT 24 17440411295 ps
T156 /workspace/coverage/default/10.sram_ctrl_alert_test.3066035087 Mar 17 03:06:21 PM PDT 24 Mar 17 03:06:22 PM PDT 24 49585406 ps
T157 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.813738448 Mar 17 03:08:17 PM PDT 24 Mar 17 03:11:49 PM PDT 24 6481665281 ps
T158 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3430901072 Mar 17 03:06:49 PM PDT 24 Mar 17 03:24:39 PM PDT 24 46842233710 ps
T132 /workspace/coverage/default/17.sram_ctrl_alert_test.1452763704 Mar 17 03:06:46 PM PDT 24 Mar 17 03:06:47 PM PDT 24 11414315 ps
T48 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2365757948 Mar 17 03:08:48 PM PDT 24 Mar 17 03:08:58 PM PDT 24 1682543053 ps
T159 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3910128215 Mar 17 03:12:07 PM PDT 24 Mar 17 03:17:24 PM PDT 24 3178620770 ps
T160 /workspace/coverage/default/1.sram_ctrl_lc_escalation.2845888652 Mar 17 03:06:00 PM PDT 24 Mar 17 03:07:07 PM PDT 24 11666330097 ps
T161 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.4061896570 Mar 17 03:10:47 PM PDT 24 Mar 17 03:14:26 PM PDT 24 11403610160 ps
T46 /workspace/coverage/default/18.sram_ctrl_regwen.3119857245 Mar 17 03:06:49 PM PDT 24 Mar 17 03:14:09 PM PDT 24 8201375571 ps
T162 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1275874071 Mar 17 03:07:22 PM PDT 24 Mar 17 03:07:42 PM PDT 24 722566805 ps
T163 /workspace/coverage/default/15.sram_ctrl_ram_cfg.631384764 Mar 17 03:06:37 PM PDT 24 Mar 17 03:06:41 PM PDT 24 1251203664 ps
T123 /workspace/coverage/default/39.sram_ctrl_executable.781379566 Mar 17 03:10:20 PM PDT 24 Mar 17 03:22:07 PM PDT 24 12734154075 ps
T164 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1618803452 Mar 17 03:07:55 PM PDT 24 Mar 17 03:09:08 PM PDT 24 3678928898 ps
T165 /workspace/coverage/default/21.sram_ctrl_partial_access.3158030635 Mar 17 03:07:12 PM PDT 24 Mar 17 03:09:24 PM PDT 24 965745221 ps
T166 /workspace/coverage/default/45.sram_ctrl_bijection.2577624246 Mar 17 03:11:27 PM PDT 24 Mar 17 03:23:31 PM PDT 24 10829333794 ps
T167 /workspace/coverage/default/13.sram_ctrl_max_throughput.3092725613 Mar 17 03:06:26 PM PDT 24 Mar 17 03:07:15 PM PDT 24 759455407 ps
T168 /workspace/coverage/default/48.sram_ctrl_regwen.3322397727 Mar 17 03:12:15 PM PDT 24 Mar 17 03:15:45 PM PDT 24 1906658898 ps
T124 /workspace/coverage/default/22.sram_ctrl_stress_all.2480686730 Mar 17 03:07:22 PM PDT 24 Mar 17 04:13:23 PM PDT 24 425182806677 ps
T169 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2220372799 Mar 17 03:07:44 PM PDT 24 Mar 17 03:09:34 PM PDT 24 818792945 ps
T170 /workspace/coverage/default/41.sram_ctrl_multiple_keys.1594234770 Mar 17 03:10:39 PM PDT 24 Mar 17 03:22:28 PM PDT 24 23805491385 ps
T171 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3739835246 Mar 17 03:06:39 PM PDT 24 Mar 17 03:09:00 PM PDT 24 4360636360 ps
T172 /workspace/coverage/default/32.sram_ctrl_max_throughput.726216601 Mar 17 03:08:55 PM PDT 24 Mar 17 03:09:10 PM PDT 24 4300488324 ps
T173 /workspace/coverage/default/41.sram_ctrl_lc_escalation.4104863261 Mar 17 03:10:44 PM PDT 24 Mar 17 03:11:14 PM PDT 24 4832703659 ps
T174 /workspace/coverage/default/46.sram_ctrl_bijection.2948474206 Mar 17 03:11:51 PM PDT 24 Mar 17 03:21:46 PM PDT 24 158647460709 ps
T175 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3906901657 Mar 17 03:06:11 PM PDT 24 Mar 17 03:07:17 PM PDT 24 3108404945 ps
T176 /workspace/coverage/default/19.sram_ctrl_alert_test.760973167 Mar 17 03:07:02 PM PDT 24 Mar 17 03:07:02 PM PDT 24 19977107 ps
T177 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1419087192 Mar 17 03:06:42 PM PDT 24 Mar 17 03:07:20 PM PDT 24 1389297254 ps
T178 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1774228938 Mar 17 03:06:39 PM PDT 24 Mar 17 03:06:54 PM PDT 24 1471023133 ps
T179 /workspace/coverage/default/49.sram_ctrl_ram_cfg.3640322324 Mar 17 03:12:21 PM PDT 24 Mar 17 03:12:24 PM PDT 24 713261355 ps
T180 /workspace/coverage/default/49.sram_ctrl_max_throughput.743462332 Mar 17 03:12:21 PM PDT 24 Mar 17 03:12:26 PM PDT 24 2667010297 ps
T125 /workspace/coverage/default/9.sram_ctrl_executable.2334646781 Mar 17 03:06:21 PM PDT 24 Mar 17 03:26:05 PM PDT 24 77427975729 ps
T181 /workspace/coverage/default/19.sram_ctrl_bijection.1359761452 Mar 17 03:06:55 PM PDT 24 Mar 17 03:41:16 PM PDT 24 364327889487 ps
T182 /workspace/coverage/default/8.sram_ctrl_ram_cfg.3577473342 Mar 17 03:06:15 PM PDT 24 Mar 17 03:06:18 PM PDT 24 357951714 ps
T183 /workspace/coverage/default/34.sram_ctrl_alert_test.1714564246 Mar 17 03:09:49 PM PDT 24 Mar 17 03:09:49 PM PDT 24 24620807 ps
T184 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2262692459 Mar 17 03:06:43 PM PDT 24 Mar 17 03:17:04 PM PDT 24 18072799284 ps
T126 /workspace/coverage/default/12.sram_ctrl_stress_all.2383996368 Mar 17 03:06:24 PM PDT 24 Mar 17 03:34:52 PM PDT 24 88275495086 ps
T120 /workspace/coverage/default/20.sram_ctrl_regwen.2393330358 Mar 17 03:07:07 PM PDT 24 Mar 17 03:14:23 PM PDT 24 56144877894 ps
T185 /workspace/coverage/default/3.sram_ctrl_max_throughput.4273793788 Mar 17 03:06:06 PM PDT 24 Mar 17 03:07:55 PM PDT 24 1543960327 ps
T186 /workspace/coverage/default/3.sram_ctrl_alert_test.3853538661 Mar 17 03:06:05 PM PDT 24 Mar 17 03:06:06 PM PDT 24 20461030 ps
T187 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.133291008 Mar 17 03:10:10 PM PDT 24 Mar 17 03:12:40 PM PDT 24 10617928728 ps
T188 /workspace/coverage/default/48.sram_ctrl_multiple_keys.1375013332 Mar 17 03:12:07 PM PDT 24 Mar 17 03:13:48 PM PDT 24 1117171747 ps
T189 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4152027541 Mar 17 03:06:42 PM PDT 24 Mar 17 03:09:03 PM PDT 24 6586088668 ps
T190 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2946452011 Mar 17 03:10:51 PM PDT 24 Mar 17 03:11:33 PM PDT 24 24330283389 ps
T191 /workspace/coverage/default/30.sram_ctrl_alert_test.1659066760 Mar 17 03:08:41 PM PDT 24 Mar 17 03:08:42 PM PDT 24 19282774 ps
T192 /workspace/coverage/default/7.sram_ctrl_max_throughput.2194169526 Mar 17 03:06:14 PM PDT 24 Mar 17 03:07:40 PM PDT 24 1861430648 ps
T193 /workspace/coverage/default/39.sram_ctrl_lc_escalation.2522604361 Mar 17 03:10:21 PM PDT 24 Mar 17 03:11:05 PM PDT 24 7284139011 ps
T194 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2705378541 Mar 17 03:10:15 PM PDT 24 Mar 17 03:15:48 PM PDT 24 22436203379 ps
T195 /workspace/coverage/default/11.sram_ctrl_max_throughput.2278503263 Mar 17 03:06:30 PM PDT 24 Mar 17 03:07:52 PM PDT 24 788583851 ps
T196 /workspace/coverage/default/37.sram_ctrl_stress_all.3451405462 Mar 17 03:09:59 PM PDT 24 Mar 17 03:27:39 PM PDT 24 49598990865 ps
T197 /workspace/coverage/default/38.sram_ctrl_smoke.2484085939 Mar 17 03:10:03 PM PDT 24 Mar 17 03:10:07 PM PDT 24 371550749 ps
T127 /workspace/coverage/default/33.sram_ctrl_regwen.798798873 Mar 17 03:09:07 PM PDT 24 Mar 17 03:14:43 PM PDT 24 16070090193 ps
T198 /workspace/coverage/default/20.sram_ctrl_max_throughput.8213484 Mar 17 03:07:02 PM PDT 24 Mar 17 03:09:01 PM PDT 24 761654762 ps
T25 /workspace/coverage/default/0.sram_ctrl_sec_cm.2341109096 Mar 17 03:05:59 PM PDT 24 Mar 17 03:06:02 PM PDT 24 333752250 ps
T199 /workspace/coverage/default/21.sram_ctrl_mem_walk.35453977 Mar 17 03:07:18 PM PDT 24 Mar 17 03:09:17 PM PDT 24 4113004870 ps
T200 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.4279768771 Mar 17 03:11:13 PM PDT 24 Mar 17 03:12:16 PM PDT 24 958318917 ps
T201 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.372712675 Mar 17 03:12:14 PM PDT 24 Mar 17 03:21:51 PM PDT 24 8566420752 ps
T202 /workspace/coverage/default/34.sram_ctrl_stress_all.3247841943 Mar 17 03:09:49 PM PDT 24 Mar 17 04:12:40 PM PDT 24 599628452033 ps
T203 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2458249925 Mar 17 03:10:55 PM PDT 24 Mar 17 03:13:04 PM PDT 24 3217179783 ps
T204 /workspace/coverage/default/46.sram_ctrl_partial_access.3234234635 Mar 17 03:11:43 PM PDT 24 Mar 17 03:11:57 PM PDT 24 537065672 ps
T49 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.960272514 Mar 17 03:10:24 PM PDT 24 Mar 17 03:10:32 PM PDT 24 503838551 ps
T205 /workspace/coverage/default/37.sram_ctrl_multiple_keys.4082885756 Mar 17 03:09:56 PM PDT 24 Mar 17 03:16:02 PM PDT 24 37907918619 ps
T206 /workspace/coverage/default/7.sram_ctrl_ram_cfg.2038732229 Mar 17 03:06:23 PM PDT 24 Mar 17 03:06:26 PM PDT 24 679181009 ps
T207 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.204391289 Mar 17 03:07:22 PM PDT 24 Mar 17 03:11:09 PM PDT 24 3893469371 ps
T208 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.28944732 Mar 17 03:10:04 PM PDT 24 Mar 17 03:13:37 PM PDT 24 6629511446 ps
T209 /workspace/coverage/default/20.sram_ctrl_ram_cfg.526406168 Mar 17 03:07:07 PM PDT 24 Mar 17 03:07:13 PM PDT 24 6731874899 ps
T210 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1689895085 Mar 17 03:12:06 PM PDT 24 Mar 17 03:14:58 PM PDT 24 3939058378 ps
T211 /workspace/coverage/default/27.sram_ctrl_lc_escalation.3798981953 Mar 17 03:07:58 PM PDT 24 Mar 17 03:09:31 PM PDT 24 18882151579 ps
T212 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1049598273 Mar 17 03:10:43 PM PDT 24 Mar 17 03:10:46 PM PDT 24 1348871223 ps
T213 /workspace/coverage/default/9.sram_ctrl_alert_test.3612784986 Mar 17 03:06:26 PM PDT 24 Mar 17 03:06:27 PM PDT 24 30384804 ps
T214 /workspace/coverage/default/9.sram_ctrl_mem_walk.3663964640 Mar 17 03:06:20 PM PDT 24 Mar 17 03:08:27 PM PDT 24 2061613569 ps
T121 /workspace/coverage/default/3.sram_ctrl_stress_all.3586735167 Mar 17 03:06:08 PM PDT 24 Mar 17 04:17:23 PM PDT 24 86012779977 ps
T215 /workspace/coverage/default/19.sram_ctrl_multiple_keys.4125243804 Mar 17 03:06:56 PM PDT 24 Mar 17 03:28:03 PM PDT 24 69991428473 ps
T216 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2410684489 Mar 17 03:06:32 PM PDT 24 Mar 17 03:09:05 PM PDT 24 45574626076 ps
T217 /workspace/coverage/default/32.sram_ctrl_lc_escalation.1622841737 Mar 17 03:08:55 PM PDT 24 Mar 17 03:10:11 PM PDT 24 17236285932 ps
T118 /workspace/coverage/default/17.sram_ctrl_regwen.1583482301 Mar 17 03:06:38 PM PDT 24 Mar 17 03:14:00 PM PDT 24 9255429375 ps
T218 /workspace/coverage/default/2.sram_ctrl_executable.2212811898 Mar 17 03:05:55 PM PDT 24 Mar 17 03:09:06 PM PDT 24 7219090522 ps
T219 /workspace/coverage/default/7.sram_ctrl_alert_test.3551470065 Mar 17 03:06:14 PM PDT 24 Mar 17 03:06:15 PM PDT 24 20564624 ps
T220 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3190664240 Mar 17 03:09:51 PM PDT 24 Mar 17 03:11:07 PM PDT 24 2363580054 ps
T50 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2449282775 Mar 17 03:07:51 PM PDT 24 Mar 17 03:09:08 PM PDT 24 5638351482 ps
T221 /workspace/coverage/default/39.sram_ctrl_stress_all.3295255529 Mar 17 03:10:24 PM PDT 24 Mar 17 03:56:33 PM PDT 24 63817670405 ps
T222 /workspace/coverage/default/38.sram_ctrl_max_throughput.3522245147 Mar 17 03:10:10 PM PDT 24 Mar 17 03:10:35 PM PDT 24 13960116658 ps
T223 /workspace/coverage/default/6.sram_ctrl_multiple_keys.1382678246 Mar 17 03:06:09 PM PDT 24 Mar 17 03:15:18 PM PDT 24 4553940386 ps
T122 /workspace/coverage/default/29.sram_ctrl_stress_all.60859721 Mar 17 03:08:26 PM PDT 24 Mar 17 04:36:50 PM PDT 24 183499786503 ps
T224 /workspace/coverage/default/2.sram_ctrl_regwen.486729633 Mar 17 03:05:56 PM PDT 24 Mar 17 03:08:26 PM PDT 24 47615199999 ps
T225 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2554446593 Mar 17 03:11:19 PM PDT 24 Mar 17 03:13:50 PM PDT 24 2141014020 ps
T226 /workspace/coverage/default/1.sram_ctrl_stress_all.1052263451 Mar 17 03:05:59 PM PDT 24 Mar 17 04:41:15 PM PDT 24 407437513184 ps
T227 /workspace/coverage/default/41.sram_ctrl_max_throughput.3137349838 Mar 17 03:10:37 PM PDT 24 Mar 17 03:10:44 PM PDT 24 714328354 ps
T51 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2922053546 Mar 17 03:06:06 PM PDT 24 Mar 17 03:06:32 PM PDT 24 1077045550 ps
T228 /workspace/coverage/default/35.sram_ctrl_bijection.3747981451 Mar 17 03:09:48 PM PDT 24 Mar 17 03:27:09 PM PDT 24 62278765944 ps
T229 /workspace/coverage/default/17.sram_ctrl_max_throughput.1488518469 Mar 17 03:06:42 PM PDT 24 Mar 17 03:07:31 PM PDT 24 754544860 ps
T230 /workspace/coverage/default/1.sram_ctrl_ram_cfg.2923668012 Mar 17 03:06:04 PM PDT 24 Mar 17 03:06:07 PM PDT 24 347580793 ps
T231 /workspace/coverage/default/47.sram_ctrl_multiple_keys.4000838419 Mar 17 03:11:57 PM PDT 24 Mar 17 03:33:57 PM PDT 24 24035465541 ps
T232 /workspace/coverage/default/46.sram_ctrl_ram_cfg.332922073 Mar 17 03:12:07 PM PDT 24 Mar 17 03:12:10 PM PDT 24 724178118 ps
T233 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.629971610 Mar 17 03:12:18 PM PDT 24 Mar 17 03:16:54 PM PDT 24 43114227795 ps
T234 /workspace/coverage/default/24.sram_ctrl_max_throughput.2448661136 Mar 17 03:07:32 PM PDT 24 Mar 17 03:07:38 PM PDT 24 985382533 ps
T235 /workspace/coverage/default/1.sram_ctrl_bijection.3208711933 Mar 17 03:05:56 PM PDT 24 Mar 17 03:41:26 PM PDT 24 496639430104 ps
T236 /workspace/coverage/default/2.sram_ctrl_partial_access.3570930738 Mar 17 03:05:59 PM PDT 24 Mar 17 03:07:22 PM PDT 24 3332339671 ps
T237 /workspace/coverage/default/11.sram_ctrl_smoke.3958445009 Mar 17 03:06:25 PM PDT 24 Mar 17 03:06:46 PM PDT 24 2648485648 ps
T238 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2764311047 Mar 17 03:10:44 PM PDT 24 Mar 17 03:40:40 PM PDT 24 24587572327 ps
T52 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3520587894 Mar 17 03:09:08 PM PDT 24 Mar 17 03:09:16 PM PDT 24 2062546405 ps
T239 /workspace/coverage/default/5.sram_ctrl_lc_escalation.2062686391 Mar 17 03:06:09 PM PDT 24 Mar 17 03:06:35 PM PDT 24 25401562474 ps
T240 /workspace/coverage/default/40.sram_ctrl_max_throughput.449333749 Mar 17 03:10:28 PM PDT 24 Mar 17 03:10:35 PM PDT 24 677578563 ps
T241 /workspace/coverage/default/33.sram_ctrl_mem_walk.2270372174 Mar 17 03:09:08 PM PDT 24 Mar 17 03:11:15 PM PDT 24 2019610295 ps
T242 /workspace/coverage/default/49.sram_ctrl_executable.1176970690 Mar 17 03:12:21 PM PDT 24 Mar 17 03:19:09 PM PDT 24 12900954144 ps
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T282 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2294953728 Mar 17 03:11:39 PM PDT 24 Mar 17 03:11:51 PM PDT 24 604035699 ps
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T291 /workspace/coverage/default/13.sram_ctrl_partial_access.692218865 Mar 17 03:06:27 PM PDT 24 Mar 17 03:06:51 PM PDT 24 2478800772 ps
T292 /workspace/coverage/default/0.sram_ctrl_lc_escalation.963386635 Mar 17 03:05:54 PM PDT 24 Mar 17 03:06:18 PM PDT 24 4023737878 ps
T293 /workspace/coverage/default/21.sram_ctrl_alert_test.3034044458 Mar 17 03:07:19 PM PDT 24 Mar 17 03:07:20 PM PDT 24 57831405 ps
T294 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.167830284 Mar 17 03:07:24 PM PDT 24 Mar 17 03:11:47 PM PDT 24 5489434105 ps
T295 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2991849905 Mar 17 03:10:05 PM PDT 24 Mar 17 03:10:22 PM PDT 24 1530983164 ps
T296 /workspace/coverage/default/42.sram_ctrl_executable.1966936171 Mar 17 03:10:52 PM PDT 24 Mar 17 03:25:14 PM PDT 24 21978724131 ps
T297 /workspace/coverage/default/28.sram_ctrl_regwen.2639968778 Mar 17 03:08:13 PM PDT 24 Mar 17 03:25:03 PM PDT 24 3800033452 ps
T298 /workspace/coverage/default/46.sram_ctrl_regwen.3080561671 Mar 17 03:11:47 PM PDT 24 Mar 17 03:21:35 PM PDT 24 144353579175 ps
T299 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1087651358 Mar 17 03:07:55 PM PDT 24 Mar 17 03:07:58 PM PDT 24 346251389 ps
T300 /workspace/coverage/default/32.sram_ctrl_regwen.1049706715 Mar 17 03:08:54 PM PDT 24 Mar 17 03:18:50 PM PDT 24 9359750256 ps
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T302 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.549274538 Mar 17 03:06:52 PM PDT 24 Mar 17 03:08:59 PM PDT 24 1554035682 ps
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