Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	139590247	1			T1	704		T2	5790		T3	98303
triple_byte_access	2728370	1			T1	637		T2	127		T4	25
halfword_access	4184564	1			T1	968		T2	157		T4	39
byte_access	5856287	1			T1	1211		T2	253		T4	55
zero_access	1782969	1			T1	306		T2	61		T4	13

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76885447

1

T1

1916

T2

3137

T3

32768

auto[1]

77256990

1

T1

1910

T2

3251

T3

65535

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69472505	1			T1	342		T2	2835		T3	32768
auto[0]	triple_byte_access	1299994	1			T1	320		T2	59		T4	10
auto[0]	halfword_access	2042226	1			T1	468		T2	80		T4	22
auto[0]	byte_access	3002304	1			T1	621		T2	135		T4	29
auto[0]	zero_access	1068418	1			T1	165		T2	28		T4	5
auto[1]	word_access	70117742	1			T1	362		T2	2955		T3	65535
auto[1]	triple_byte_access	1428376	1			T1	317		T2	68		T4	15
auto[1]	halfword_access	2142338	1			T1	500		T2	77		T4	17
auto[1]	byte_access	2853983	1			T1	590		T2	118		T4	26
auto[1]	zero_access	714551	1			T1	141		T2	33		T4	8