Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	362817922	1			T1	400874		T2	424654		T3	313886
instr_valid_dis	315717979	1			T1	400874		T2	424654		T3	313886
instr_en	29675535	1			T24	149390		T22	32382		T40	274294

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15016340	1			T5	45136		T13	35690		T24	159356
sram_ifetch_valid_disable	317759979	1			T1	400874		T2	424654		T3	313886
sram_ifetch_enable	30041603	1			T5	114176		T13	93204		T24	346520

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	362817922	1			T1	400874		T2	424654		T3	313886
hw_debug_en_valid_off	314533812	1			T1	400874		T2	424654		T3	313886
hw_debug_en_on	36084978	1			T5	121530		T13	25408		T24	471968

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	317759979	1			T1	400874		T2	424654		T3	313886
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	299275471	1			T1	400874		T2	424654		T3	313886
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	14616360	1			T24	87330		T22	32382		T40	168218
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	8452480	1			T13	35690		T22	22890		T40	23126
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1756154	1			T13	35690		T126	77104		T23	41246
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2879624	1			T40	23126		T49	30542		T126	30962
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4233714	1			T5	34964		T24	88126		T22	33106
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1696136	1			T126	45680		T23	67372		T127	740
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1639110	1			T40	35018		T126	56174		T127	62502
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	23322678	1			T5	73110		T13	11352		T24	220698
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	14334038	1			T13	11352		T24	180764		T126	68
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7381834	1			T24	39178		T22	32382		T49	60718

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9543831	1			T24	34286		T40	47932		T49	716556
lc_exec_en	8528586	1			T5	13456		T13	14056		T24	163144
valid_exec_dis	300285369	1			T1	400874		T2	424654		T3	313886
invalid_exec_dis	45057943	1			T5	159312		T13	128894		T24	505876