Name |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3737194826 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.673040277 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3857751591 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2855129185 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4062568871 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4056472400 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2243575431 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1982499874 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1136734303 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.692483066 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2915371709 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1454877957 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.260269508 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3711213781 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1932190517 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3067967767 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3017918712 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.249290087 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1941304034 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4277907736 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.451346629 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.351613726 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.638943329 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2233391555 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.322942709 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1357598811 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.679174247 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.896628396 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.751497313 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3757527550 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2294092866 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4204859566 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.97108067 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4083936894 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.373551442 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.127418651 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.900636755 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.500422418 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.95354204 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2665214316 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1963141542 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.628153519 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4023801810 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.492459652 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1917481844 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2089162811 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.794826889 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3880314306 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1908685230 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.842209758 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1224192001 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3984846450 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.294242134 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1698822387 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2128297271 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3029074511 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.792627898 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.556108393 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2033911267 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3748674052 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3286348871 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2029205620 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2182702402 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1339583515 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.794910227 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1181951247 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3772888134 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1775903437 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.972967293 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2011377340 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1190999444 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3095436967 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.5401345 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2576875755 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1183802858 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2388007996 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1353082373 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1751791119 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.536895439 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3970594816 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.38060507 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3211409999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3888507252 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3565506394 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3669387370 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.349039405 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1583621247 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1348747948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.565865455 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2509999015 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.204460123 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2018923175 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.367855763 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1020964368 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4177127145 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2738118807 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1401388059 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.630045555 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3056538898 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1795032571 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3333136798 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3066488249 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4279769795 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2874478701 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3286597599 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3792939122 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3642987051 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1195463612 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1721219462 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1837424727 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3721696379 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.154087602 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4025769073 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.733525846 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3617399691 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1890448875 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2701921640 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3947254919 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4225046229 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1238313830 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4070781031 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2962514004 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2047942271 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.890568324 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1508167654 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1957463086 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4151035494 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2229865807 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.308868197 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2671673936 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1458844020 |
/workspace/coverage/default/0.sram_ctrl_bijection.1585090850 |
/workspace/coverage/default/0.sram_ctrl_executable.3793389166 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3394008945 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3683706237 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2173677329 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.3013832533 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3872798577 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1172576449 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.996903594 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3454509082 |
/workspace/coverage/default/0.sram_ctrl_regwen.1182135342 |
/workspace/coverage/default/0.sram_ctrl_smoke.2551048233 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1458426018 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4233279733 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.55182133 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4109944482 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.310369841 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2722534017 |
/workspace/coverage/default/1.sram_ctrl_bijection.1289343201 |
/workspace/coverage/default/1.sram_ctrl_executable.3238632648 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3065993289 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1610560010 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3718675404 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2290269533 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2793661457 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1948132288 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.52841614 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.4010084146 |
/workspace/coverage/default/1.sram_ctrl_regwen.921048440 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.228655885 |
/workspace/coverage/default/1.sram_ctrl_smoke.1070485183 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1568865674 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3579949198 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.458926437 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3111834153 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1170135057 |
/workspace/coverage/default/10.sram_ctrl_bijection.2461557187 |
/workspace/coverage/default/10.sram_ctrl_executable.640716797 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2832921815 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2649210319 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2500404733 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3285185319 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1860692429 |
/workspace/coverage/default/10.sram_ctrl_partial_access.4015230302 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1171793067 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2408577653 |
/workspace/coverage/default/10.sram_ctrl_smoke.2805775016 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2537863303 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2281141008 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2692089749 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2239589804 |
/workspace/coverage/default/11.sram_ctrl_alert_test.502932429 |
/workspace/coverage/default/11.sram_ctrl_bijection.3420989432 |
/workspace/coverage/default/11.sram_ctrl_executable.4214218568 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2177362732 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.53277614 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1348692575 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3645264079 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3052309229 |
/workspace/coverage/default/11.sram_ctrl_partial_access.4009957828 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.673458300 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.557062472 |
/workspace/coverage/default/11.sram_ctrl_regwen.1868560982 |
/workspace/coverage/default/11.sram_ctrl_smoke.1148327283 |
/workspace/coverage/default/11.sram_ctrl_stress_all.869770059 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3238682858 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1734482871 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2743760532 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2971435133 |
/workspace/coverage/default/12.sram_ctrl_alert_test.971197373 |
/workspace/coverage/default/12.sram_ctrl_bijection.84318185 |
/workspace/coverage/default/12.sram_ctrl_executable.1850481328 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3678803147 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1298640282 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.140394836 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2074951030 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2780203725 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3144763846 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3957913123 |
/workspace/coverage/default/12.sram_ctrl_regwen.658656481 |
/workspace/coverage/default/12.sram_ctrl_smoke.2104264366 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1996094421 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.999078421 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.463224838 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2772190860 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.4145579497 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2277050812 |
/workspace/coverage/default/13.sram_ctrl_bijection.336660762 |
/workspace/coverage/default/13.sram_ctrl_executable.1943413453 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2195092988 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2579997415 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2054876855 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.4194046012 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1359587434 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2381078908 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2129693093 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3311272200 |
/workspace/coverage/default/13.sram_ctrl_regwen.3602576944 |
/workspace/coverage/default/13.sram_ctrl_smoke.1592657887 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2416098011 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2937838719 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1687061284 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1186718452 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.4246378830 |
/workspace/coverage/default/14.sram_ctrl_alert_test.2863690139 |
/workspace/coverage/default/14.sram_ctrl_bijection.2686729482 |
/workspace/coverage/default/14.sram_ctrl_executable.642305916 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.163287920 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1992499042 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.168757883 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1847394656 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2857568008 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3588382117 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.384395074 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1775448254 |
/workspace/coverage/default/14.sram_ctrl_regwen.2946181393 |
/workspace/coverage/default/14.sram_ctrl_smoke.2845215504 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3629963356 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2004875664 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1146027426 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.504035003 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2738435262 |
/workspace/coverage/default/15.sram_ctrl_bijection.127947809 |
/workspace/coverage/default/15.sram_ctrl_executable.3093236759 |
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/workspace/coverage/default/44.sram_ctrl_multiple_keys.1840189894 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1953723199 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1738926327 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.737710792 |
/workspace/coverage/default/44.sram_ctrl_regwen.2670467623 |
/workspace/coverage/default/44.sram_ctrl_smoke.792556234 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3097803961 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2564983703 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3322023156 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2054998500 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2266336858 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1885814011 |
/workspace/coverage/default/45.sram_ctrl_bijection.2146338819 |
/workspace/coverage/default/45.sram_ctrl_executable.1464779140 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3557943449 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2178881401 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1077862209 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.1844125005 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1843794927 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3141144246 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3452034068 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2467150532 |
/workspace/coverage/default/45.sram_ctrl_regwen.1937401027 |
/workspace/coverage/default/45.sram_ctrl_smoke.1006710365 |
/workspace/coverage/default/45.sram_ctrl_stress_all.4259647321 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2320655368 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2878279208 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3209904463 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2405639342 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1397553219 |
/workspace/coverage/default/46.sram_ctrl_bijection.917991496 |
/workspace/coverage/default/46.sram_ctrl_executable.4250704416 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3448013290 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.3852302872 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2966764079 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.234197510 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.559576684 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1067031807 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4040911796 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1799650807 |
/workspace/coverage/default/46.sram_ctrl_regwen.2465078218 |
/workspace/coverage/default/46.sram_ctrl_smoke.3858646283 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3127091898 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.96161793 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1644744095 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4230803901 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1014356869 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1128976366 |
/workspace/coverage/default/47.sram_ctrl_bijection.3114653095 |
/workspace/coverage/default/47.sram_ctrl_executable.1868784129 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3071066101 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1689351620 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.778418664 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.936189623 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.100875015 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1756483048 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2783436280 |
/workspace/coverage/default/47.sram_ctrl_regwen.3874211104 |
/workspace/coverage/default/47.sram_ctrl_smoke.2259943270 |
/workspace/coverage/default/47.sram_ctrl_stress_all.618008051 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1288579438 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1303812287 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3612539258 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.422635602 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3747348751 |
/workspace/coverage/default/48.sram_ctrl_bijection.3036734183 |
/workspace/coverage/default/48.sram_ctrl_executable.204601639 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2477170874 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3249840826 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.119940891 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1594214746 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1720919229 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3212665819 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.927084164 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3809622500 |
/workspace/coverage/default/48.sram_ctrl_regwen.507326424 |
/workspace/coverage/default/48.sram_ctrl_smoke.226772172 |
/workspace/coverage/default/48.sram_ctrl_stress_all.4270248132 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2476478982 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1098711426 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2976565807 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.304442106 |
/workspace/coverage/default/49.sram_ctrl_alert_test.4024443692 |
/workspace/coverage/default/49.sram_ctrl_bijection.3171988346 |
/workspace/coverage/default/49.sram_ctrl_executable.4203197637 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2376232305 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2343724424 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3645214877 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.964189651 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.219385644 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1859558825 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3337114533 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2238634851 |
/workspace/coverage/default/49.sram_ctrl_regwen.2018501785 |
/workspace/coverage/default/49.sram_ctrl_smoke.3432546588 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2255943408 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.134884458 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2563496732 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1208083063 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1992828850 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2622381004 |
/workspace/coverage/default/5.sram_ctrl_bijection.2320052129 |
/workspace/coverage/default/5.sram_ctrl_executable.2508523670 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.591857737 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2557193022 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1086591624 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.2671790921 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2351986345 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2098659845 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1178665467 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3707667801 |
/workspace/coverage/default/5.sram_ctrl_regwen.1332706820 |
/workspace/coverage/default/5.sram_ctrl_smoke.33526642 |
/workspace/coverage/default/5.sram_ctrl_stress_all.50148397 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.247750171 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2443278582 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1696929264 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.284928758 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2965345376 |
/workspace/coverage/default/6.sram_ctrl_bijection.3103982331 |
/workspace/coverage/default/6.sram_ctrl_executable.2576903854 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4255477603 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2095444420 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.591186219 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2542418153 |
/workspace/coverage/default/6.sram_ctrl_partial_access.3382841872 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1388160025 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4202082653 |
/workspace/coverage/default/6.sram_ctrl_regwen.135410609 |
/workspace/coverage/default/6.sram_ctrl_smoke.951731061 |
/workspace/coverage/default/6.sram_ctrl_stress_all.589384077 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1982669740 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3925782618 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4158780144 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1533813313 |
/workspace/coverage/default/7.sram_ctrl_alert_test.4228297360 |
/workspace/coverage/default/7.sram_ctrl_bijection.1810660719 |
/workspace/coverage/default/7.sram_ctrl_executable.2220477555 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3153091581 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.620932833 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.842965438 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1201917313 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2024592933 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2042604535 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3054268973 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1354200103 |
/workspace/coverage/default/7.sram_ctrl_regwen.2492691008 |
/workspace/coverage/default/7.sram_ctrl_smoke.1508153242 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2927949176 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2756791691 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3534558461 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1876186473 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3570013170 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2014529488 |
/workspace/coverage/default/8.sram_ctrl_bijection.2824653747 |
/workspace/coverage/default/8.sram_ctrl_executable.1958724448 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2920757083 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3162211720 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2699879150 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1434421314 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2697844223 |
/workspace/coverage/default/8.sram_ctrl_partial_access.123114653 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1537593560 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3601979383 |
/workspace/coverage/default/8.sram_ctrl_regwen.2792060518 |
/workspace/coverage/default/8.sram_ctrl_smoke.2408771985 |
/workspace/coverage/default/8.sram_ctrl_stress_all.940732185 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1798632666 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3112489642 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2765583073 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.72714196 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1226443587 |
/workspace/coverage/default/9.sram_ctrl_bijection.3698979288 |
/workspace/coverage/default/9.sram_ctrl_executable.3022770675 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3911636772 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3397298059 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3800131667 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.131757757 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1329325596 |
/workspace/coverage/default/9.sram_ctrl_partial_access.794845286 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4071318132 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3884797092 |
/workspace/coverage/default/9.sram_ctrl_regwen.510157739 |
/workspace/coverage/default/9.sram_ctrl_smoke.4218726316 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3458523574 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3782447 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.410250426 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.530150293 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1212471923 |
|
|
Mar 19 02:32:04 PM PDT 24 |
Mar 19 02:38:15 PM PDT 24 |
19331452387 ps |
T2 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3372589928 |
|
|
Mar 19 02:30:40 PM PDT 24 |
Mar 19 02:35:21 PM PDT 24 |
4519259011 ps |
T3 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1394687860 |
|
|
Mar 19 02:21:58 PM PDT 24 |
Mar 19 02:25:25 PM PDT 24 |
4482560038 ps |
T9 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.481928007 |
|
|
Mar 19 02:28:29 PM PDT 24 |
Mar 19 02:28:54 PM PDT 24 |
1600156127 ps |
T6 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.50751728 |
|
|
Mar 19 02:26:09 PM PDT 24 |
Mar 19 02:27:22 PM PDT 24 |
11031935845 ps |
T7 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.4218478444 |
|
|
Mar 19 02:25:29 PM PDT 24 |
Mar 19 02:26:26 PM PDT 24 |
18091061140 ps |
T4 |
/workspace/coverage/default/45.sram_ctrl_smoke.1006710365 |
|
|
Mar 19 02:31:18 PM PDT 24 |
Mar 19 02:31:25 PM PDT 24 |
695628737 ps |
T5 |
/workspace/coverage/default/10.sram_ctrl_regwen.2010973045 |
|
|
Mar 19 02:22:53 PM PDT 24 |
Mar 19 02:33:03 PM PDT 24 |
45561177275 ps |
T10 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.422299462 |
|
|
Mar 19 02:23:19 PM PDT 24 |
Mar 19 02:23:22 PM PDT 24 |
1345609677 ps |
T11 |
/workspace/coverage/default/8.sram_ctrl_partial_access.123114653 |
|
|
Mar 19 02:22:37 PM PDT 24 |
Mar 19 02:24:08 PM PDT 24 |
4828687997 ps |
T12 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2554486376 |
|
|
Mar 19 02:30:46 PM PDT 24 |
Mar 19 02:54:38 PM PDT 24 |
17189485004 ps |
T8 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.4016956055 |
|
|
Mar 19 02:25:03 PM PDT 24 |
Mar 19 02:25:50 PM PDT 24 |
43020315202 ps |
T48 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3803943928 |
|
|
Mar 19 02:25:36 PM PDT 24 |
Mar 19 02:28:04 PM PDT 24 |
2300580243 ps |
T13 |
/workspace/coverage/default/25.sram_ctrl_regwen.1822264464 |
|
|
Mar 19 02:26:10 PM PDT 24 |
Mar 19 02:40:34 PM PDT 24 |
7291852844 ps |
T14 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.504035003 |
|
|
Mar 19 02:23:50 PM PDT 24 |
Mar 19 02:35:51 PM PDT 24 |
37983587337 ps |
T16 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3215853344 |
|
|
Mar 19 02:26:34 PM PDT 24 |
Mar 19 02:26:34 PM PDT 24 |
16992935 ps |
T61 |
/workspace/coverage/default/25.sram_ctrl_partial_access.2074815892 |
|
|
Mar 19 02:26:00 PM PDT 24 |
Mar 19 02:26:20 PM PDT 24 |
7745438415 ps |
T15 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2209265822 |
|
|
Mar 19 02:29:58 PM PDT 24 |
Mar 19 02:51:57 PM PDT 24 |
48710979294 ps |
T62 |
/workspace/coverage/default/36.sram_ctrl_bijection.451063088 |
|
|
Mar 19 02:29:14 PM PDT 24 |
Mar 19 02:56:24 PM PDT 24 |
46027360823 ps |
T63 |
/workspace/coverage/default/11.sram_ctrl_bijection.3420989432 |
|
|
Mar 19 02:22:59 PM PDT 24 |
Mar 19 02:58:50 PM PDT 24 |
30823291393 ps |
T69 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.310369841 |
|
|
Mar 19 02:21:49 PM PDT 24 |
Mar 19 02:46:03 PM PDT 24 |
13106952300 ps |
T136 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3285185319 |
|
|
Mar 19 02:23:00 PM PDT 24 |
Mar 19 02:25:36 PM PDT 24 |
14058091504 ps |
T132 |
/workspace/coverage/default/21.sram_ctrl_bijection.2102355429 |
|
|
Mar 19 02:25:06 PM PDT 24 |
Mar 19 02:50:20 PM PDT 24 |
183313499020 ps |
T70 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.931044065 |
|
|
Mar 19 02:31:12 PM PDT 24 |
Mar 19 02:45:10 PM PDT 24 |
16063635991 ps |
T27 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.346593401 |
|
|
Mar 19 02:28:59 PM PDT 24 |
Mar 19 02:29:03 PM PDT 24 |
345671184 ps |
T137 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1027294715 |
|
|
Mar 19 02:24:48 PM PDT 24 |
Mar 19 02:25:29 PM PDT 24 |
886883947 ps |
T138 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.2506043004 |
|
|
Mar 19 02:22:00 PM PDT 24 |
Mar 19 02:26:29 PM PDT 24 |
16410964773 ps |
T28 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1206024014 |
|
|
Mar 19 02:24:05 PM PDT 24 |
Mar 19 02:24:08 PM PDT 24 |
1410078478 ps |
T139 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1212744995 |
|
|
Mar 19 02:24:56 PM PDT 24 |
Mar 19 02:29:06 PM PDT 24 |
15756260212 ps |
T140 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.936189623 |
|
|
Mar 19 02:32:13 PM PDT 24 |
Mar 19 02:35:05 PM PDT 24 |
41274029224 ps |
T141 |
/workspace/coverage/default/16.sram_ctrl_bijection.4090118962 |
|
|
Mar 19 02:23:57 PM PDT 24 |
Mar 19 02:36:11 PM PDT 24 |
129945254970 ps |
T71 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.4168728740 |
|
|
Mar 19 02:30:54 PM PDT 24 |
Mar 19 02:34:55 PM PDT 24 |
4716557235 ps |
T135 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1756483048 |
|
|
Mar 19 02:32:04 PM PDT 24 |
Mar 19 02:32:46 PM PDT 24 |
1529661602 ps |
T142 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.131757757 |
|
|
Mar 19 02:22:39 PM PDT 24 |
Mar 19 02:24:52 PM PDT 24 |
5640541771 ps |
T143 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3601979383 |
|
|
Mar 19 02:22:31 PM PDT 24 |
Mar 19 02:22:35 PM PDT 24 |
356577367 ps |
T72 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2971435133 |
|
|
Mar 19 02:23:09 PM PDT 24 |
Mar 19 02:45:04 PM PDT 24 |
10395253553 ps |
T24 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2927949176 |
|
|
Mar 19 02:22:30 PM PDT 24 |
Mar 19 03:39:37 PM PDT 24 |
46380960201 ps |
T22 |
/workspace/coverage/default/10.sram_ctrl_stress_all.2364422145 |
|
|
Mar 19 02:23:01 PM PDT 24 |
Mar 19 02:53:16 PM PDT 24 |
41012684495 ps |
T144 |
/workspace/coverage/default/11.sram_ctrl_partial_access.4009957828 |
|
|
Mar 19 02:23:00 PM PDT 24 |
Mar 19 02:25:05 PM PDT 24 |
1224977505 ps |
T95 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.4029195397 |
|
|
Mar 19 02:25:50 PM PDT 24 |
Mar 19 02:30:08 PM PDT 24 |
17810060329 ps |
T96 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.535242340 |
|
|
Mar 19 02:27:56 PM PDT 24 |
Mar 19 02:33:19 PM PDT 24 |
4907350040 ps |
T40 |
/workspace/coverage/default/20.sram_ctrl_regwen.3179621877 |
|
|
Mar 19 02:25:05 PM PDT 24 |
Mar 19 02:41:58 PM PDT 24 |
12223598619 ps |
T17 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2603781887 |
|
|
Mar 19 02:28:06 PM PDT 24 |
Mar 19 02:28:07 PM PDT 24 |
27689445 ps |
T73 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1012849485 |
|
|
Mar 19 02:21:58 PM PDT 24 |
Mar 19 02:30:02 PM PDT 24 |
8934023539 ps |
T74 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3753692773 |
|
|
Mar 19 02:28:06 PM PDT 24 |
Mar 19 02:48:04 PM PDT 24 |
16785890554 ps |
T97 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2237509355 |
|
|
Mar 19 02:29:29 PM PDT 24 |
Mar 19 02:35:25 PM PDT 24 |
5433708198 ps |
T49 |
/workspace/coverage/default/8.sram_ctrl_stress_all.940732185 |
|
|
Mar 19 02:22:39 PM PDT 24 |
Mar 19 04:33:03 PM PDT 24 |
561702484833 ps |
T145 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2098659845 |
|
|
Mar 19 02:22:17 PM PDT 24 |
Mar 19 02:22:28 PM PDT 24 |
2862579341 ps |
T50 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2477170874 |
|
|
Mar 19 02:32:21 PM PDT 24 |
Mar 19 02:34:22 PM PDT 24 |
75483035331 ps |
T126 |
/workspace/coverage/default/29.sram_ctrl_executable.41806884 |
|
|
Mar 19 02:27:18 PM PDT 24 |
Mar 19 02:49:44 PM PDT 24 |
15317116689 ps |
T18 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1367305738 |
|
|
Mar 19 02:28:48 PM PDT 24 |
Mar 19 02:28:49 PM PDT 24 |
42830612 ps |
T25 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2537863303 |
|
|
Mar 19 02:22:59 PM PDT 24 |
Mar 19 02:23:15 PM PDT 24 |
1397406249 ps |
T111 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3030051513 |
|
|
Mar 19 02:26:24 PM PDT 24 |
Mar 19 02:26:46 PM PDT 24 |
3522500709 ps |
T146 |
/workspace/coverage/default/14.sram_ctrl_smoke.2845215504 |
|
|
Mar 19 02:23:26 PM PDT 24 |
Mar 19 02:23:30 PM PDT 24 |
1364199342 ps |
T125 |
/workspace/coverage/default/6.sram_ctrl_executable.2576903854 |
|
|
Mar 19 02:22:19 PM PDT 24 |
Mar 19 02:28:41 PM PDT 24 |
29195078141 ps |
T23 |
/workspace/coverage/default/38.sram_ctrl_regwen.3018581910 |
|
|
Mar 19 02:29:51 PM PDT 24 |
Mar 19 02:53:00 PM PDT 24 |
44460369429 ps |
T127 |
/workspace/coverage/default/38.sram_ctrl_executable.3934947268 |
|
|
Mar 19 02:29:40 PM PDT 24 |
Mar 19 02:40:40 PM PDT 24 |
50874729086 ps |
T112 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1021103453 |
|
|
Mar 19 02:28:26 PM PDT 24 |
Mar 19 02:29:11 PM PDT 24 |
28367914555 ps |
T75 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.29118552 |
|
|
Mar 19 02:28:26 PM PDT 24 |
Mar 19 02:30:33 PM PDT 24 |
1553424111 ps |
T134 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3448013290 |
|
|
Mar 19 02:31:46 PM PDT 24 |
Mar 19 02:32:13 PM PDT 24 |
6072323661 ps |
T147 |
/workspace/coverage/default/23.sram_ctrl_alert_test.127336962 |
|
|
Mar 19 02:25:46 PM PDT 24 |
Mar 19 02:25:48 PM PDT 24 |
14139654 ps |
T148 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.11289891 |
|
|
Mar 19 02:21:58 PM PDT 24 |
Mar 19 02:22:14 PM PDT 24 |
737357678 ps |
T149 |
/workspace/coverage/default/18.sram_ctrl_bijection.3650618060 |
|
|
Mar 19 02:24:47 PM PDT 24 |
Mar 19 02:43:41 PM PDT 24 |
16415494562 ps |
T150 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2178881401 |
|
|
Mar 19 02:31:27 PM PDT 24 |
Mar 19 02:31:36 PM PDT 24 |
1627308296 ps |
T151 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.460014190 |
|
|
Mar 19 02:29:17 PM PDT 24 |
Mar 19 02:30:43 PM PDT 24 |
763276722 ps |
T152 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1813568963 |
|
|
Mar 19 02:25:36 PM PDT 24 |
Mar 19 02:26:15 PM PDT 24 |
5120417119 ps |
T153 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.4092465277 |
|
|
Mar 19 02:29:14 PM PDT 24 |
Mar 19 02:38:41 PM PDT 24 |
11711827248 ps |
T154 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2283011867 |
|
|
Mar 19 02:27:08 PM PDT 24 |
Mar 19 02:27:10 PM PDT 24 |
71958067 ps |
T155 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2246306835 |
|
|
Mar 19 02:25:36 PM PDT 24 |
Mar 19 02:25:37 PM PDT 24 |
50591404 ps |
T156 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2174076767 |
|
|
Mar 19 02:25:48 PM PDT 24 |
Mar 19 02:45:42 PM PDT 24 |
20484652649 ps |
T157 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2697844223 |
|
|
Mar 19 02:22:29 PM PDT 24 |
Mar 19 02:32:22 PM PDT 24 |
9298837990 ps |
T158 |
/workspace/coverage/default/3.sram_ctrl_smoke.3726234386 |
|
|
Mar 19 02:22:01 PM PDT 24 |
Mar 19 02:22:16 PM PDT 24 |
4688982546 ps |
T159 |
/workspace/coverage/default/33.sram_ctrl_regwen.3715406221 |
|
|
Mar 19 02:28:26 PM PDT 24 |
Mar 19 02:32:11 PM PDT 24 |
5036937837 ps |
T160 |
/workspace/coverage/default/39.sram_ctrl_alert_test.2627885232 |
|
|
Mar 19 02:30:07 PM PDT 24 |
Mar 19 02:30:07 PM PDT 24 |
64547631 ps |
T161 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.627145558 |
|
|
Mar 19 02:30:15 PM PDT 24 |
Mar 19 02:33:06 PM PDT 24 |
21086844857 ps |
T162 |
/workspace/coverage/default/48.sram_ctrl_bijection.3036734183 |
|
|
Mar 19 02:32:20 PM PDT 24 |
Mar 19 03:03:09 PM PDT 24 |
91192449748 ps |
T98 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2295056150 |
|
|
Mar 19 02:26:23 PM PDT 24 |
Mar 19 02:31:29 PM PDT 24 |
5397520093 ps |
T133 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.201742149 |
|
|
Mar 19 02:24:58 PM PDT 24 |
Mar 19 02:26:42 PM PDT 24 |
17484100644 ps |
T26 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.230838419 |
|
|
Mar 19 02:30:00 PM PDT 24 |
Mar 19 02:32:40 PM PDT 24 |
2751884582 ps |
T41 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3629963356 |
|
|
Mar 19 02:23:41 PM PDT 24 |
Mar 19 02:23:48 PM PDT 24 |
1076033392 ps |
T163 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.616557083 |
|
|
Mar 19 02:29:33 PM PDT 24 |
Mar 19 02:30:22 PM PDT 24 |
21680134525 ps |
T128 |
/workspace/coverage/default/44.sram_ctrl_executable.848119715 |
|
|
Mar 19 02:31:12 PM PDT 24 |
Mar 19 02:33:59 PM PDT 24 |
3125994422 ps |
T88 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1069057110 |
|
|
Mar 19 02:29:25 PM PDT 24 |
Mar 19 02:32:15 PM PDT 24 |
37583126649 ps |
T164 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3327866725 |
|
|
Mar 19 02:25:48 PM PDT 24 |
Mar 19 02:28:20 PM PDT 24 |
5151162494 ps |
T165 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3880841167 |
|
|
Mar 19 02:26:15 PM PDT 24 |
Mar 19 02:26:17 PM PDT 24 |
84736443 ps |
T166 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2092033104 |
|
|
Mar 19 02:27:08 PM PDT 24 |
Mar 19 02:29:43 PM PDT 24 |
3187918923 ps |
T131 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3052309229 |
|
|
Mar 19 02:23:02 PM PDT 24 |
Mar 19 02:37:55 PM PDT 24 |
33244650262 ps |
T167 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.3769729400 |
|
|
Mar 19 02:27:45 PM PDT 24 |
Mar 19 02:31:57 PM PDT 24 |
4068791604 ps |
T42 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1043207230 |
|
|
Mar 19 02:25:54 PM PDT 24 |
Mar 19 02:26:09 PM PDT 24 |
430167247 ps |
T168 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3903910135 |
|
|
Mar 19 02:28:18 PM PDT 24 |
Mar 19 02:28:24 PM PDT 24 |
1638901564 ps |
T169 |
/workspace/coverage/default/9.sram_ctrl_partial_access.794845286 |
|
|
Mar 19 02:22:39 PM PDT 24 |
Mar 19 02:23:00 PM PDT 24 |
1077702995 ps |
T99 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3100845938 |
|
|
Mar 19 02:24:56 PM PDT 24 |
Mar 19 02:32:35 PM PDT 24 |
20785464358 ps |
T170 |
/workspace/coverage/default/9.sram_ctrl_bijection.3698979288 |
|
|
Mar 19 02:22:41 PM PDT 24 |
Mar 19 03:11:05 PM PDT 24 |
155764515811 ps |
T171 |
/workspace/coverage/default/8.sram_ctrl_smoke.2408771985 |
|
|
Mar 19 02:22:38 PM PDT 24 |
Mar 19 02:24:20 PM PDT 24 |
432375326 ps |
T172 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.4067532159 |
|
|
Mar 19 02:29:50 PM PDT 24 |
Mar 19 02:52:15 PM PDT 24 |
27246814832 ps |
T173 |
/workspace/coverage/default/48.sram_ctrl_regwen.507326424 |
|
|
Mar 19 02:32:19 PM PDT 24 |
Mar 19 02:42:57 PM PDT 24 |
4378945945 ps |
T174 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3726724082 |
|
|
Mar 19 02:28:18 PM PDT 24 |
Mar 19 02:28:51 PM PDT 24 |
726173033 ps |
T175 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.4243255929 |
|
|
Mar 19 02:25:04 PM PDT 24 |
Mar 19 02:25:11 PM PDT 24 |
710451459 ps |
T176 |
/workspace/coverage/default/32.sram_ctrl_stress_all.4280783689 |
|
|
Mar 19 02:28:08 PM PDT 24 |
Mar 19 03:57:44 PM PDT 24 |
557154224425 ps |
T177 |
/workspace/coverage/default/38.sram_ctrl_stress_all.4188561745 |
|
|
Mar 19 02:29:51 PM PDT 24 |
Mar 19 03:26:04 PM PDT 24 |
60683222626 ps |
T124 |
/workspace/coverage/default/17.sram_ctrl_regwen.4181771906 |
|
|
Mar 19 02:24:48 PM PDT 24 |
Mar 19 02:58:58 PM PDT 24 |
76490007396 ps |
T178 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3162211720 |
|
|
Mar 19 02:22:30 PM PDT 24 |
Mar 19 02:24:11 PM PDT 24 |
1437328157 ps |
T179 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2671673936 |
|
|
Mar 19 02:21:34 PM PDT 24 |
Mar 19 02:24:12 PM PDT 24 |
1424701492 ps |
T180 |
/workspace/coverage/default/14.sram_ctrl_stress_all.2524376371 |
|
|
Mar 19 02:23:35 PM PDT 24 |
Mar 19 03:54:44 PM PDT 24 |
243400877112 ps |
T43 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.4061081511 |
|
|
Mar 19 02:23:50 PM PDT 24 |
Mar 19 02:24:00 PM PDT 24 |
453737413 ps |
T130 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1329325596 |
|
|
Mar 19 02:22:41 PM PDT 24 |
Mar 19 02:58:56 PM PDT 24 |
83745210004 ps |
T181 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1843794927 |
|
|
Mar 19 02:31:18 PM PDT 24 |
Mar 19 02:41:55 PM PDT 24 |
11809246636 ps |
T182 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.7749114 |
|
|
Mar 19 02:27:09 PM PDT 24 |
Mar 19 02:27:16 PM PDT 24 |
3699448579 ps |
T183 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3579949198 |
|
|
Mar 19 02:21:47 PM PDT 24 |
Mar 19 02:26:47 PM PDT 24 |
9782337832 ps |
T89 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3043084356 |
|
|
Mar 19 02:25:55 PM PDT 24 |
Mar 19 02:27:13 PM PDT 24 |
2614141534 ps |
T184 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2563496732 |
|
|
Mar 19 02:32:25 PM PDT 24 |
Mar 19 02:35:21 PM PDT 24 |
4688945749 ps |
T185 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2050547405 |
|
|
Mar 19 02:28:39 PM PDT 24 |
Mar 19 02:28:40 PM PDT 24 |
20617150 ps |
T186 |
/workspace/coverage/default/36.sram_ctrl_smoke.869084933 |
|
|
Mar 19 02:29:08 PM PDT 24 |
Mar 19 02:29:14 PM PDT 24 |
494195728 ps |
T187 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3375503108 |
|
|
Mar 19 02:31:03 PM PDT 24 |
Mar 19 02:31:04 PM PDT 24 |
13464231 ps |
T188 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1984907852 |
|
|
Mar 19 02:25:09 PM PDT 24 |
Mar 19 02:26:09 PM PDT 24 |
10980988869 ps |
T189 |
/workspace/coverage/default/32.sram_ctrl_smoke.2763255182 |
|
|
Mar 19 02:27:56 PM PDT 24 |
Mar 19 02:28:12 PM PDT 24 |
10653764933 ps |
T190 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2343724424 |
|
|
Mar 19 02:32:33 PM PDT 24 |
Mar 19 02:32:44 PM PDT 24 |
4527310604 ps |
T191 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3493491817 |
|
|
Mar 19 02:27:59 PM PDT 24 |
Mar 19 03:05:26 PM PDT 24 |
166875398507 ps |
T192 |
/workspace/coverage/default/15.sram_ctrl_bijection.127947809 |
|
|
Mar 19 02:23:41 PM PDT 24 |
Mar 19 02:59:02 PM PDT 24 |
121962572043 ps |
T193 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1373501884 |
|
|
Mar 19 02:23:53 PM PDT 24 |
Mar 19 02:25:11 PM PDT 24 |
9857835388 ps |
T44 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1995433020 |
|
|
Mar 19 02:21:59 PM PDT 24 |
Mar 19 02:22:08 PM PDT 24 |
2409932256 ps |
T19 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.228655885 |
|
|
Mar 19 02:21:59 PM PDT 24 |
Mar 19 02:22:02 PM PDT 24 |
353510076 ps |
T31 |
/workspace/coverage/default/23.sram_ctrl_regwen.2762303411 |
|
|
Mar 19 02:25:40 PM PDT 24 |
Mar 19 02:29:08 PM PDT 24 |
4926282340 ps |
T32 |
/workspace/coverage/default/47.sram_ctrl_regwen.3874211104 |
|
|
Mar 19 02:32:15 PM PDT 24 |
Mar 19 02:56:35 PM PDT 24 |
9304174193 ps |
T33 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3097803961 |
|
|
Mar 19 02:31:18 PM PDT 24 |
Mar 19 04:08:45 PM PDT 24 |
248145575711 ps |
T34 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2218006675 |
|
|
Mar 19 02:27:19 PM PDT 24 |
Mar 19 02:27:22 PM PDT 24 |
696199762 ps |
T35 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1170135057 |
|
|
Mar 19 02:23:00 PM PDT 24 |
Mar 19 02:23:01 PM PDT 24 |
14960622 ps |
T36 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1857076518 |
|
|
Mar 19 02:29:35 PM PDT 24 |
Mar 19 02:29:36 PM PDT 24 |
40493580 ps |
T37 |
/workspace/coverage/default/29.sram_ctrl_smoke.593097303 |
|
|
Mar 19 02:27:08 PM PDT 24 |
Mar 19 02:29:43 PM PDT 24 |
1842458303 ps |
T38 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1348692575 |
|
|
Mar 19 02:23:10 PM PDT 24 |
Mar 19 02:24:30 PM PDT 24 |
6688280282 ps |
T39 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3401458828 |
|
|
Mar 19 02:30:48 PM PDT 24 |
Mar 19 03:59:42 PM PDT 24 |
43818354887 ps |
T194 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.4040116262 |
|
|
Mar 19 02:28:27 PM PDT 24 |
Mar 19 02:30:55 PM PDT 24 |
28747864505 ps |
T195 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3961410220 |
|
|
Mar 19 02:24:48 PM PDT 24 |
Mar 19 02:45:54 PM PDT 24 |
28763271698 ps |
T196 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3057162310 |
|
|
Mar 19 02:26:08 PM PDT 24 |
Mar 19 02:26:33 PM PDT 24 |
4447306931 ps |
T197 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.970824968 |
|
|
Mar 19 02:28:48 PM PDT 24 |
Mar 19 02:29:25 PM PDT 24 |
1796863434 ps |
T198 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3818243272 |
|
|
Mar 19 02:26:56 PM PDT 24 |
Mar 19 02:28:15 PM PDT 24 |
10725930384 ps |
T199 |
/workspace/coverage/default/38.sram_ctrl_bijection.2387167666 |
|
|
Mar 19 02:29:49 PM PDT 24 |
Mar 19 03:13:14 PM PDT 24 |
480928800598 ps |
T200 |
/workspace/coverage/default/20.sram_ctrl_smoke.1251666675 |
|
|
Mar 19 02:25:01 PM PDT 24 |
Mar 19 02:26:08 PM PDT 24 |
783166138 ps |
T201 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.673458300 |
|
|
Mar 19 02:23:00 PM PDT 24 |
Mar 19 02:27:53 PM PDT 24 |
5411471608 ps |
T202 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1687061284 |
|
|
Mar 19 02:23:18 PM PDT 24 |
Mar 19 02:25:57 PM PDT 24 |
5846130970 ps |
T203 |
/workspace/coverage/default/47.sram_ctrl_smoke.2259943270 |
|
|
Mar 19 02:32:03 PM PDT 24 |
Mar 19 02:32:22 PM PDT 24 |
2260369175 ps |
T204 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3249840826 |
|
|
Mar 19 02:32:19 PM PDT 24 |
Mar 19 02:32:48 PM PDT 24 |
715966344 ps |
T205 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.4171625696 |
|
|
Mar 19 02:28:50 PM PDT 24 |
Mar 19 02:28:53 PM PDT 24 |
1349658301 ps |
T206 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.495922735 |
|
|
Mar 19 02:29:50 PM PDT 24 |
Mar 19 02:34:29 PM PDT 24 |
17186115896 ps |
T207 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3293124358 |
|
|
Mar 19 02:26:35 PM PDT 24 |
Mar 19 02:29:19 PM PDT 24 |
11354166980 ps |
T208 |
/workspace/coverage/default/33.sram_ctrl_bijection.2297633347 |
|
|
Mar 19 02:28:17 PM PDT 24 |
Mar 19 02:47:10 PM PDT 24 |
59946782139 ps |
T209 |
/workspace/coverage/default/14.sram_ctrl_alert_test.2863690139 |
|
|
Mar 19 02:23:39 PM PDT 24 |
Mar 19 02:23:40 PM PDT 24 |
73836852 ps |
T210 |
/workspace/coverage/default/43.sram_ctrl_partial_access.3780775021 |
|
|
Mar 19 02:30:54 PM PDT 24 |
Mar 19 02:31:10 PM PDT 24 |
848424398 ps |
T211 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2024592933 |
|
|
Mar 19 02:22:25 PM PDT 24 |
Mar 19 02:39:46 PM PDT 24 |
19646547881 ps |
T212 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1146027426 |
|
|
Mar 19 02:23:26 PM PDT 24 |
Mar 19 02:24:15 PM PDT 24 |
1450776543 ps |
T213 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.832007678 |
|
|
Mar 19 02:29:41 PM PDT 24 |
Mar 19 02:46:39 PM PDT 24 |
30336182396 ps |
T214 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1186718452 |
|
|
Mar 19 02:23:17 PM PDT 24 |
Mar 19 02:23:28 PM PDT 24 |
7618180627 ps |
T215 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2622381004 |
|
|
Mar 19 02:22:08 PM PDT 24 |
Mar 19 02:22:10 PM PDT 24 |
14364237 ps |
T216 |
/workspace/coverage/default/5.sram_ctrl_executable.2508523670 |
|
|
Mar 19 02:22:16 PM PDT 24 |
Mar 19 02:23:24 PM PDT 24 |
1680611510 ps |
T217 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.4290067013 |
|
|
Mar 19 02:24:58 PM PDT 24 |
Mar 19 02:25:18 PM PDT 24 |
705507611 ps |
T218 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2911828335 |
|
|
Mar 19 02:29:15 PM PDT 24 |
Mar 19 02:30:22 PM PDT 24 |
37771637691 ps |
T219 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.126855871 |
|
|
Mar 19 02:26:43 PM PDT 24 |
Mar 19 02:28:18 PM PDT 24 |
228834843005 ps |
T220 |
/workspace/coverage/default/25.sram_ctrl_executable.2788519558 |
|
|
Mar 19 02:26:08 PM PDT 24 |
Mar 19 02:32:10 PM PDT 24 |
2674982627 ps |
T221 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.4235556634 |
|
|
Mar 19 02:27:38 PM PDT 24 |
Mar 19 02:28:58 PM PDT 24 |
11062461136 ps |
T222 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3888289513 |
|
|
Mar 19 02:29:41 PM PDT 24 |
Mar 19 02:30:58 PM PDT 24 |
10548116090 ps |
T223 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1434421314 |
|
|
Mar 19 02:22:30 PM PDT 24 |
Mar 19 02:25:13 PM PDT 24 |
9229509541 ps |
T224 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.4126439212 |
|
|
Mar 19 02:24:52 PM PDT 24 |
Mar 19 02:25:01 PM PDT 24 |
713913863 ps |
T225 |
/workspace/coverage/default/11.sram_ctrl_smoke.1148327283 |
|
|
Mar 19 02:23:00 PM PDT 24 |
Mar 19 02:23:16 PM PDT 24 |
544656485 ps |
T226 |
/workspace/coverage/default/44.sram_ctrl_bijection.3401677740 |
|
|
Mar 19 02:31:04 PM PDT 24 |
Mar 19 02:50:45 PM PDT 24 |
247200210868 ps |
T227 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3574126942 |
|
|
Mar 19 02:25:07 PM PDT 24 |
Mar 19 02:27:16 PM PDT 24 |
1976853676 ps |
T228 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1613950898 |
|
|
Mar 19 02:24:06 PM PDT 24 |
Mar 19 02:27:23 PM PDT 24 |
14122147150 ps |
T229 |
/workspace/coverage/default/39.sram_ctrl_executable.1458919410 |
|
|
Mar 19 02:29:59 PM PDT 24 |
Mar 19 02:33:53 PM PDT 24 |
7102421989 ps |
T230 |
/workspace/coverage/default/45.sram_ctrl_executable.1464779140 |
|
|
Mar 19 02:31:33 PM PDT 24 |
Mar 19 02:48:09 PM PDT 24 |
44884779157 ps |
T231 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1412845402 |
|
|
Mar 19 02:27:47 PM PDT 24 |
Mar 19 02:28:48 PM PDT 24 |
1495258735 ps |
T232 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3392784764 |
|
|
Mar 19 02:30:07 PM PDT 24 |
Mar 19 02:34:54 PM PDT 24 |
19145029059 ps |
T233 |
/workspace/coverage/default/41.sram_ctrl_stress_all.390531291 |
|
|
Mar 19 02:30:38 PM PDT 24 |
Mar 19 03:15:37 PM PDT 24 |
37825420498 ps |
T234 |
/workspace/coverage/default/21.sram_ctrl_regwen.1202159697 |
|
|
Mar 19 02:25:04 PM PDT 24 |
Mar 19 02:26:17 PM PDT 24 |
4917700269 ps |
T235 |
/workspace/coverage/default/43.sram_ctrl_stress_all.148639921 |
|
|
Mar 19 02:31:05 PM PDT 24 |
Mar 19 02:48:27 PM PDT 24 |
257199691323 ps |
T236 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.4203591095 |
|
|
Mar 19 02:28:36 PM PDT 24 |
Mar 19 02:30:13 PM PDT 24 |
764740376 ps |
T237 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3615307655 |
|
|
Mar 19 02:25:53 PM PDT 24 |
Mar 19 04:20:42 PM PDT 24 |
148411678338 ps |
T238 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3534431428 |
|
|
Mar 19 02:27:08 PM PDT 24 |
Mar 19 02:27:16 PM PDT 24 |
1764578073 ps |
T239 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.99535351 |
|
|
Mar 19 02:29:51 PM PDT 24 |
Mar 19 02:30:29 PM PDT 24 |
744835004 ps |
T240 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3280003923 |
|
|
Mar 19 02:25:35 PM PDT 24 |
Mar 19 02:42:57 PM PDT 24 |
14740086144 ps |
T241 |
/workspace/coverage/default/10.sram_ctrl_partial_access.4015230302 |
|
|
Mar 19 02:22:49 PM PDT 24 |
Mar 19 02:23:04 PM PDT 24 |
5970049027 ps |
T242 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3065993289 |
|
|
Mar 19 02:21:45 PM PDT 24 |
Mar 19 02:22:46 PM PDT 24 |
35335418642 ps |
T243 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1941243389 |
|
|
Mar 19 02:29:08 PM PDT 24 |
Mar 19 02:29:11 PM PDT 24 |
24237448 ps |
T244 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.996903594 |
|
|
Mar 19 02:21:31 PM PDT 24 |
Mar 19 02:26:33 PM PDT 24 |
99581338415 ps |
T245 |
/workspace/coverage/default/40.sram_ctrl_smoke.62204100 |
|
|
Mar 19 02:30:07 PM PDT 24 |
Mar 19 02:32:33 PM PDT 24 |
881128001 ps |
T246 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.512725478 |
|
|
Mar 19 02:22:08 PM PDT 24 |
Mar 19 02:36:33 PM PDT 24 |
77681046463 ps |
T247 |
/workspace/coverage/default/40.sram_ctrl_bijection.3292461401 |
|
|
Mar 19 02:30:06 PM PDT 24 |
Mar 19 02:57:18 PM PDT 24 |
897866744437 ps |
T248 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4255477603 |
|
|
Mar 19 02:22:25 PM PDT 24 |
Mar 19 02:22:45 PM PDT 24 |
3412817699 ps |
T249 |
/workspace/coverage/default/27.sram_ctrl_smoke.3026789382 |
|
|
Mar 19 02:26:43 PM PDT 24 |
Mar 19 02:27:04 PM PDT 24 |
874439925 ps |
T250 |
/workspace/coverage/default/33.sram_ctrl_executable.1387468286 |
|
|
Mar 19 02:28:27 PM PDT 24 |
Mar 19 02:39:09 PM PDT 24 |
38784815742 ps |
T251 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1226443587 |
|
|
Mar 19 02:22:43 PM PDT 24 |
Mar 19 02:22:46 PM PDT 24 |
22685701 ps |
T252 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1128976366 |
|
|
Mar 19 02:32:11 PM PDT 24 |
Mar 19 02:32:13 PM PDT 24 |
24451252 ps |
T253 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.4243855886 |
|
|
Mar 19 02:24:06 PM PDT 24 |
Mar 19 02:25:08 PM PDT 24 |
971416518 ps |
T254 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2783436280 |
|
|
Mar 19 02:32:11 PM PDT 24 |
Mar 19 02:32:15 PM PDT 24 |
3706798268 ps |
T255 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1315909368 |
|
|
Mar 19 02:27:36 PM PDT 24 |
Mar 19 02:28:58 PM PDT 24 |
5093205616 ps |
T256 |
/workspace/coverage/default/30.sram_ctrl_regwen.2913501178 |
|
|
Mar 19 02:27:27 PM PDT 24 |
Mar 19 02:33:45 PM PDT 24 |
18060775807 ps |
T45 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2711877712 |
|
|
Mar 19 02:29:34 PM PDT 24 |
Mar 19 02:29:49 PM PDT 24 |
451091910 ps |
T257 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3984302354 |
|
|
Mar 19 02:25:04 PM PDT 24 |
Mar 19 02:41:57 PM PDT 24 |
26579809281 ps |
T258 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2588123617 |
|
|
Mar 19 02:30:54 PM PDT 24 |
Mar 19 02:36:03 PM PDT 24 |
19796354573 ps |
T259 |
/workspace/coverage/default/40.sram_ctrl_executable.2362445556 |
|
|
Mar 19 02:30:19 PM PDT 24 |
Mar 19 02:34:06 PM PDT 24 |
9327854363 ps |
T260 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.4145579497 |
|
|
Mar 19 02:23:28 PM PDT 24 |
Mar 19 02:39:44 PM PDT 24 |
15791655630 ps |
T261 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1083102357 |
|
|
Mar 19 02:28:58 PM PDT 24 |
Mar 19 02:29:09 PM PDT 24 |
789616825 ps |
T262 |
/workspace/coverage/default/26.sram_ctrl_bijection.804921180 |
|
|
Mar 19 02:26:24 PM PDT 24 |
Mar 19 03:03:51 PM PDT 24 |
67672666160 ps |
T263 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1170008193 |
|
|
Mar 19 02:23:42 PM PDT 24 |
Mar 19 02:31:33 PM PDT 24 |
7710982155 ps |
T264 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2956984705 |
|
|
Mar 19 02:27:37 PM PDT 24 |
Mar 19 02:28:05 PM PDT 24 |
750799524 ps |
T265 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3477674151 |
|
|
Mar 19 02:27:57 PM PDT 24 |
Mar 19 02:28:43 PM PDT 24 |
677703451 ps |
T266 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3809622500 |
|
|
Mar 19 02:32:20 PM PDT 24 |
Mar 19 02:32:23 PM PDT 24 |
692482159 ps |
T267 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3154892248 |
|
|
Mar 19 02:24:59 PM PDT 24 |
Mar 19 02:25:02 PM PDT 24 |
356885011 ps |
T268 |
/workspace/coverage/default/21.sram_ctrl_smoke.1854917469 |
|
|
Mar 19 02:25:03 PM PDT 24 |
Mar 19 02:25:18 PM PDT 24 |
1057725951 ps |
T46 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1640539230 |
|
|
Mar 19 02:26:34 PM PDT 24 |
Mar 19 02:26:50 PM PDT 24 |
484200220 ps |
T47 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2109910763 |
|
|
Mar 19 02:27:36 PM PDT 24 |
Mar 19 02:28:15 PM PDT 24 |
2494895614 ps |
T269 |
/workspace/coverage/default/37.sram_ctrl_executable.625859014 |
|
|
Mar 19 02:29:33 PM PDT 24 |
Mar 19 02:47:48 PM PDT 24 |
33155404601 ps |
T270 |
/workspace/coverage/default/47.sram_ctrl_bijection.3114653095 |
|
|
Mar 19 02:32:03 PM PDT 24 |
Mar 19 03:12:30 PM PDT 24 |
149414569473 ps |
T271 |
/workspace/coverage/default/11.sram_ctrl_executable.4214218568 |
|
|
Mar 19 02:23:09 PM PDT 24 |
Mar 19 02:43:38 PM PDT 24 |
22679663705 ps |
T272 |
/workspace/coverage/default/27.sram_ctrl_executable.2611785141 |
|
|
Mar 19 02:26:43 PM PDT 24 |
Mar 19 02:36:20 PM PDT 24 |
8884192299 ps |
T273 |
/workspace/coverage/default/46.sram_ctrl_bijection.917991496 |
|
|
Mar 19 02:31:40 PM PDT 24 |
Mar 19 02:54:58 PM PDT 24 |
84616989961 ps |
T129 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1324181820 |
|
|
Mar 19 02:27:07 PM PDT 24 |
Mar 19 02:34:20 PM PDT 24 |
19465803617 ps |
T274 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1738926327 |
|
|
Mar 19 02:31:10 PM PDT 24 |
Mar 19 02:39:17 PM PDT 24 |
25869998292 ps |
T275 |
/workspace/coverage/default/14.sram_ctrl_regwen.2946181393 |
|
|
Mar 19 02:23:37 PM PDT 24 |
Mar 19 02:30:40 PM PDT 24 |
9038679660 ps |
T276 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1992499042 |
|
|
Mar 19 02:23:27 PM PDT 24 |
Mar 19 02:24:20 PM PDT 24 |
1470139197 ps |
T277 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2965345376 |
|
|
Mar 19 02:22:18 PM PDT 24 |
Mar 19 02:22:19 PM PDT 24 |
35767521 ps |
T278 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2425769663 |
|
|
Mar 19 02:22:01 PM PDT 24 |
Mar 19 02:22:29 PM PDT 24 |
1345220120 ps |
T279 |
/workspace/coverage/default/15.sram_ctrl_executable.3093236759 |
|
|
Mar 19 02:23:41 PM PDT 24 |
Mar 19 02:43:57 PM PDT 24 |
39948581470 ps |
T280 |
/workspace/coverage/default/29.sram_ctrl_alert_test.867382644 |
|
|
Mar 19 02:27:25 PM PDT 24 |
Mar 19 02:27:26 PM PDT 24 |
15066793 ps |
T281 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3238682858 |
|
|
Mar 19 02:23:10 PM PDT 24 |
Mar 19 02:26:21 PM PDT 24 |
18661968946 ps |
T282 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1885814011 |
|
|
Mar 19 02:31:41 PM PDT 24 |
Mar 19 02:31:42 PM PDT 24 |
47960949 ps |
T283 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2266336858 |
|
|
Mar 19 02:31:26 PM PDT 24 |
Mar 19 02:46:37 PM PDT 24 |
21362941752 ps |
T104 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3942337865 |
|
|
Mar 19 02:28:08 PM PDT 24 |
Mar 19 02:28:56 PM PDT 24 |
17777009715 ps |
T284 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2748612011 |
|
|
Mar 19 02:26:34 PM PDT 24 |
Mar 19 02:27:43 PM PDT 24 |
997463259 ps |
T285 |
/workspace/coverage/default/4.sram_ctrl_regwen.709322295 |
|
|
Mar 19 02:22:12 PM PDT 24 |
Mar 19 02:27:18 PM PDT 24 |
8345446292 ps |
T286 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.155872070 |
|
|
Mar 19 02:23:52 PM PDT 24 |
Mar 19 02:30:23 PM PDT 24 |
275239268444 ps |
T287 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1799650807 |
|
|
Mar 19 02:31:46 PM PDT 24 |
Mar 19 02:31:50 PM PDT 24 |
1403255907 ps |
T288 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1561503864 |
|
|
Mar 19 02:22:01 PM PDT 24 |
Mar 19 02:58:34 PM PDT 24 |
81076467785 ps |
T289 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2722534017 |
|
|
Mar 19 02:22:00 PM PDT 24 |
Mar 19 02:22:01 PM PDT 24 |
14231384 ps |
T105 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1844526074 |
|
|
Mar 19 02:25:33 PM PDT 24 |
Mar 19 02:25:50 PM PDT 24 |
4629200375 ps |
T290 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3397298059 |
|
|
Mar 19 02:22:40 PM PDT 24 |
Mar 19 02:24:17 PM PDT 24 |
769470230 ps |
T291 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4202082653 |
|
|
Mar 19 02:22:23 PM PDT 24 |
Mar 19 02:22:27 PM PDT 24 |
345612137 ps |
T292 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2129693093 |
|
|
Mar 19 02:23:19 PM PDT 24 |
Mar 19 02:29:39 PM PDT 24 |
57431525496 ps |
T293 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1860692429 |
|
|
Mar 19 02:22:53 PM PDT 24 |
Mar 19 02:33:51 PM PDT 24 |
78339841567 ps |
T294 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1002746770 |
|
|
Mar 19 02:24:59 PM PDT 24 |
Mar 19 02:25:05 PM PDT 24 |
2690137072 ps |
T295 |
/workspace/coverage/default/47.sram_ctrl_executable.1868784129 |
|
|
Mar 19 02:32:12 PM PDT 24 |
Mar 19 02:53:18 PM PDT 24 |
14768892624 ps |
T296 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2772190860 |
|
|
Mar 19 02:23:10 PM PDT 24 |
Mar 19 02:23:17 PM PDT 24 |
691811739 ps |
T297 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2738435262 |
|
|
Mar 19 02:23:56 PM PDT 24 |
Mar 19 02:23:57 PM PDT 24 |
17986170 ps |
T298 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3337114533 |
|
|
Mar 19 02:32:35 PM PDT 24 |
Mar 19 02:40:47 PM PDT 24 |
88372302782 ps |
T299 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1711096605 |
|
|
Mar 19 02:25:46 PM PDT 24 |
Mar 19 02:29:29 PM PDT 24 |
12750564482 ps |
T300 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2187436737 |
|
|
Mar 19 02:31:10 PM PDT 24 |
Mar 19 02:33:35 PM PDT 24 |
3462500608 ps |
T301 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1139465498 |
|
|
Mar 19 02:27:24 PM PDT 24 |
Mar 19 02:34:47 PM PDT 24 |
14860300867 ps |
T302 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4230803901 |
|
|
Mar 19 02:31:46 PM PDT 24 |
Mar 19 02:32:20 PM PDT 24 |
1452631743 ps |
T303 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2115131118 |
|
|
Mar 19 02:27:28 PM PDT 24 |
Mar 19 02:31:36 PM PDT 24 |
8284522602 ps |
T304 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2054998500 |
|
|
Mar 19 02:31:11 PM PDT 24 |
Mar 19 02:31:34 PM PDT 24 |
2179579604 ps |
T305 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.219385644 |
|
|
Mar 19 02:32:27 PM PDT 24 |
Mar 19 03:06:31 PM PDT 24 |
46688129631 ps |
T306 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3186631252 |
|
|
Mar 19 02:21:58 PM PDT 24 |
Mar 19 02:22:02 PM PDT 24 |
1344856274 ps |