Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	152217313	1			T1	36384		T2	193036		T3	142722
triple_byte_access	2782520	1			T1	33151		T2	3868		T3	2881
halfword_access	4266303	1			T1	49405		T2	5844		T3	4277
byte_access	5962516	1			T1	65353		T2	7606		T3	5638
zero_access	1795493	1			T1	16144		T2	1973		T3	1425

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83248681

1

T1

99726

T2

106272

T3

78619

auto[1]

83775464

1

T1

100711

T2

106055

T3

78324

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75715734	1			T1	18252		T2	96578		T3	71596
auto[0]	triple_byte_access	1329493	1			T1	16383		T2	1928		T3	1401
auto[0]	halfword_access	2084527	1			T1	24598		T2	2946		T3	2101
auto[0]	byte_access	3050883	1			T1	32526		T2	3825		T3	2808
auto[0]	zero_access	1068044	1			T1	7967		T2	995		T3	713
auto[1]	word_access	76501579	1			T1	18132		T2	96458		T3	71126
auto[1]	triple_byte_access	1453027	1			T1	16768		T2	1940		T3	1480
auto[1]	halfword_access	2181776	1			T1	24807		T2	2898		T3	2176
auto[1]	byte_access	2911633	1			T1	32827		T2	3781		T3	2830
auto[1]	zero_access	727449	1			T1	8177		T2	978		T3	712