Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	335870854	1			T1	9418		T3	256996		T4	17674
instr_valid_dis	297097977	1			T1	9418		T3	256996		T4	17674
instr_en	30648406	1			T10	236618		T16	125428		T7	348272

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18724984	1			T10	59162		T16	61452		T7	261604
sram_ifetch_valid_disable	291857886	1			T1	9418		T3	256996		T4	17674
sram_ifetch_enable	25287984	1			T10	199516		T12	6766		T16	200300

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	335870854	1			T1	9418		T3	256996		T4	17674
hw_debug_en_valid_off	291918612	1			T1	9418		T3	256996		T4	17674
hw_debug_en_on	28065588	1			T10	210792		T16	297064		T7	332152

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	291857886	1			T1	9418		T3	256996		T4	17674
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	275514097	1			T1	9418		T3	256996		T4	17674
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13007060	1			T10	10074		T16	15834		T7	33730
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	8633798	1			T16	14130		T7	85428		T24	57918
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	5390766	1			T16	14130		T7	78832		T39	43228
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2534402	1			T7	6596		T24	57918		T124	54
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6486812	1			T10	32134		T16	43022		T7	105956
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3511276	1			T16	27704		T7	28968		T39	73460
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2129640	1			T7	76988		T24	12594		T25	12412
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13476072	1			T10	17288		T16	119306		T7	32648
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4800412	1			T10	7214		T16	18694		T7	32648
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7059184	1			T10	10074		T24	903238		T50	30488

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12012558	1			T10	199516		T16	109594		T7	173354
lc_exec_en	8102704	1			T10	161370		T16	134736		T7	193548
valid_exec_dis	283306842	1			T1	9418		T3	256996		T4	17674
invalid_exec_dis	44012968	1			T10	258678		T12	6766		T16	206445