Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	100.00	97.91	100.00	100.00	99.72	99.70	98.52

Total tests in report: 1036

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
83.70	83.70	97.76	97.76	83.82	83.82	93.47	93.47	71.43	71.43	91.27	91.27	95.10	95.10	53.06	53.06	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3301041043
93.13	9.43	99.44	1.68	89.96	6.14	97.94	4.47	100.00	28.57	95.49	4.23	95.39	0.30	73.65	20.59	/workspace/coverage/default/37.sram_ctrl_stress_all.2526917881
95.71	2.59	99.44	0.00	92.61	2.65	97.94	0.00	100.00	0.00	97.18	1.69	95.99	0.59	86.83	13.17	/workspace/coverage/default/32.sram_ctrl_partial_access.1414600679
96.76	1.05	99.91	0.47	95.68	3.07	98.51	0.57	100.00	0.00	99.44	2.25	96.58	0.59	87.20	0.37	/workspace/coverage/default/1.sram_ctrl_sec_cm.2668951508
97.53	0.78	99.91	0.00	96.09	0.42	98.51	0.00	100.00	0.00	99.44	0.00	96.58	0.00	92.21	5.01	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4033708342
98.01	0.47	99.91	0.00	96.09	0.00	98.51	0.00	100.00	0.00	99.44	0.00	96.73	0.15	95.36	3.15	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.478316242
98.27	0.27	99.91	0.00	96.37	0.28	98.58	0.07	100.00	0.00	99.44	0.00	98.07	1.34	95.55	0.19	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4061139137
98.51	0.24	99.91	0.00	96.65	0.28	98.58	0.00	100.00	0.00	99.44	0.00	99.26	1.19	95.73	0.19	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2198827502
98.72	0.21	99.91	0.00	97.07	0.42	99.08	0.50	100.00	0.00	99.44	0.00	99.26	0.00	96.29	0.56	/workspace/coverage/default/4.sram_ctrl_alert_test.3265873618
98.91	0.19	99.91	0.00	97.49	0.42	99.29	0.21	100.00	0.00	99.72	0.28	99.70	0.45	96.29	0.00	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3839362419
99.03	0.11	100.00	0.09	97.49	0.00	100.00	0.71	100.00	0.00	99.72	0.00	99.70	0.00	96.29	0.00	/workspace/coverage/default/11.sram_ctrl_ram_cfg.3530301062
99.13	0.11	100.00	0.00	97.49	0.00	100.00	0.00	100.00	0.00	99.72	0.00	99.70	0.00	97.03	0.74	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2765876046
99.23	0.10	100.00	0.00	97.63	0.14	100.00	0.00	100.00	0.00	99.72	0.00	99.70	0.00	97.59	0.56	/workspace/coverage/default/5.sram_ctrl_stress_all.3418286321
99.29	0.05	100.00	0.00	97.63	0.00	100.00	0.00	100.00	0.00	99.72	0.00	99.70	0.00	97.96	0.37	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.113783642
99.34	0.05	100.00	0.00	97.63	0.00	100.00	0.00	100.00	0.00	99.72	0.00	99.70	0.00	98.33	0.37	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3377617613
99.37	0.03	100.00	0.00	97.63	0.00	100.00	0.00	100.00	0.00	99.72	0.00	99.70	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1530935587

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2743022751
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2771227306
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.955942124
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.580874225
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.961287144
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.153947608
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.174913561
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.71806646
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4172944244
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.920559217
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3914259841
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3841860744
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.603962822
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3543385172
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3695636945
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.156898150
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3842367528
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.526700157
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4006392860
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1967897059
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1068657512
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2922291395
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.124961614
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1583935516
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3939611280
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3916833761
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1613316393
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2398285678
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3159691988
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3861271129
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2333371714
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4262931305
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2379640784
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.652324596
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3984157782
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2330649385
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4194802016
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.423726898
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1985093317
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1031648300
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2818160905
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1834662383
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.731598083
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3934776065
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3622887981
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4026109007
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3114314724
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3284785821
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3059500822
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3219036492
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2734356914
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.916393143
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4273127437
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4088117519
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3306296153
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2269031127
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2294381943
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.513370894
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3078927480
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.91870461
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4117316505
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1430858563
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.867470290
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1757317877
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.788851767
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1265009608
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3733504827
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4076499754
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1433903076
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4138662494
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2891723189
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1294672487
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2410241221
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1932543481
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2925089999
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3252379262
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3367788022
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1141096682
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3613441277
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2948817470
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3296261668
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1446152537
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1952003517
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1603919945
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1538934744
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1773693699
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3017651650
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1818740732
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.503342989
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1948070975
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1286702319
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.866850348
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.750198604
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1669387917
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3523012194
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2206475107
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1508120877
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3806438660
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3278809947
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3610480137
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3006490651
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2675194714
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1759657694
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4073008506
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3987779389
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.480691697
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.83380415
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2272203091
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.544551881
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3127062389
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1553222043
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.714900704
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2981830855
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3045975557
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3186305819
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2441066278
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.585115630
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.546138384
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3111326635
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.168379560
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2749299424
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3507587039
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3871405646
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.612681321
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4219349028
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1244302944
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3403172122
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.909389332
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.683369953
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2945285589
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3800319441
/workspace/coverage/default/0.sram_ctrl_alert_test.3818214243
/workspace/coverage/default/0.sram_ctrl_bijection.2701833813
/workspace/coverage/default/0.sram_ctrl_executable.4267651293
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2693026246
/workspace/coverage/default/0.sram_ctrl_max_throughput.1876354580
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2441298976
/workspace/coverage/default/0.sram_ctrl_mem_walk.1647710453
/workspace/coverage/default/0.sram_ctrl_multiple_keys.773383176
/workspace/coverage/default/0.sram_ctrl_partial_access.713015901
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1380974304
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1103981516
/workspace/coverage/default/0.sram_ctrl_regwen.3114488413
/workspace/coverage/default/0.sram_ctrl_sec_cm.1926974385
/workspace/coverage/default/0.sram_ctrl_smoke.2952634463
/workspace/coverage/default/0.sram_ctrl_stress_all.2269419467
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4075797970
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1674334846
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4010173062
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.129647424
/workspace/coverage/default/1.sram_ctrl_alert_test.1048559941
/workspace/coverage/default/1.sram_ctrl_bijection.1573148208
/workspace/coverage/default/1.sram_ctrl_executable.2114250240
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3967107763
/workspace/coverage/default/1.sram_ctrl_max_throughput.654797303
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1142999836
/workspace/coverage/default/1.sram_ctrl_mem_walk.3659204014
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3979505697
/workspace/coverage/default/1.sram_ctrl_partial_access.293159252
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1354869528
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3878603955
/workspace/coverage/default/1.sram_ctrl_regwen.750120635
/workspace/coverage/default/1.sram_ctrl_smoke.4216528039
/workspace/coverage/default/1.sram_ctrl_stress_all.1823027904
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.219099653
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1578801583
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.914092624
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3018117094
/workspace/coverage/default/10.sram_ctrl_alert_test.1423199751
/workspace/coverage/default/10.sram_ctrl_bijection.870843813
/workspace/coverage/default/10.sram_ctrl_executable.3919205125
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1485416129
/workspace/coverage/default/10.sram_ctrl_max_throughput.3209626834
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.134119007
/workspace/coverage/default/10.sram_ctrl_mem_walk.2242001166
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4126648399
/workspace/coverage/default/10.sram_ctrl_partial_access.1503434835
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3516631767
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3888094714
/workspace/coverage/default/10.sram_ctrl_regwen.1629085224
/workspace/coverage/default/10.sram_ctrl_smoke.345412203
/workspace/coverage/default/10.sram_ctrl_stress_all.3408384451
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1874732061
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.349816877
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1900714611
/workspace/coverage/default/11.sram_ctrl_alert_test.4234143622
/workspace/coverage/default/11.sram_ctrl_bijection.484818383
/workspace/coverage/default/11.sram_ctrl_executable.1882803789
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1430374860
/workspace/coverage/default/11.sram_ctrl_max_throughput.2062148333
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3162876273
/workspace/coverage/default/11.sram_ctrl_mem_walk.4070350010
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3557647709
/workspace/coverage/default/11.sram_ctrl_partial_access.2213493896
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2823884652
/workspace/coverage/default/11.sram_ctrl_regwen.4255812328
/workspace/coverage/default/11.sram_ctrl_smoke.1452819202
/workspace/coverage/default/11.sram_ctrl_stress_all.2460799639
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.729809161
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2658044505
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.62685088
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.4142945465
/workspace/coverage/default/12.sram_ctrl_alert_test.873785899
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/workspace/coverage/default/42.sram_ctrl_partial_access.530212887
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3466267873
/workspace/coverage/default/42.sram_ctrl_ram_cfg.120183881
/workspace/coverage/default/42.sram_ctrl_regwen.231536507
/workspace/coverage/default/42.sram_ctrl_smoke.2378087220
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1606236224
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3853019000
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2748949172
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3923600312
/workspace/coverage/default/43.sram_ctrl_alert_test.2651878470
/workspace/coverage/default/43.sram_ctrl_bijection.4004567640
/workspace/coverage/default/43.sram_ctrl_executable.1765516709
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2534145265
/workspace/coverage/default/43.sram_ctrl_max_throughput.1216485457
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2365565712
/workspace/coverage/default/43.sram_ctrl_mem_walk.1194688223
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2742498018
/workspace/coverage/default/43.sram_ctrl_partial_access.4027704579
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3640577072
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1876832087
/workspace/coverage/default/43.sram_ctrl_regwen.3032566824
/workspace/coverage/default/43.sram_ctrl_smoke.3376756163
/workspace/coverage/default/43.sram_ctrl_stress_all.1526461971
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3843812205
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2824282445
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3807646190
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1497293422
/workspace/coverage/default/44.sram_ctrl_alert_test.1447581284
/workspace/coverage/default/44.sram_ctrl_bijection.1297706278
/workspace/coverage/default/44.sram_ctrl_executable.2648256417
/workspace/coverage/default/44.sram_ctrl_lc_escalation.4028271649
/workspace/coverage/default/44.sram_ctrl_max_throughput.927402091
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.398075387
/workspace/coverage/default/44.sram_ctrl_mem_walk.769223826
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4165841861
/workspace/coverage/default/44.sram_ctrl_partial_access.571463121
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3224601891
/workspace/coverage/default/44.sram_ctrl_ram_cfg.499846715
/workspace/coverage/default/44.sram_ctrl_regwen.3212550867
/workspace/coverage/default/44.sram_ctrl_smoke.3223413480
/workspace/coverage/default/44.sram_ctrl_stress_all.1808753206
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4102749705
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.51521898
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1730327879
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.824444183
/workspace/coverage/default/45.sram_ctrl_alert_test.1660402213
/workspace/coverage/default/45.sram_ctrl_bijection.3912116944
/workspace/coverage/default/45.sram_ctrl_executable.3802436305
/workspace/coverage/default/45.sram_ctrl_lc_escalation.4120087024
/workspace/coverage/default/45.sram_ctrl_max_throughput.1838262447
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.430232781
/workspace/coverage/default/45.sram_ctrl_mem_walk.2099600052
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2185526839
/workspace/coverage/default/45.sram_ctrl_partial_access.695130910
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2992407352
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2700020451
/workspace/coverage/default/45.sram_ctrl_regwen.2919871583
/workspace/coverage/default/45.sram_ctrl_smoke.693073653
/workspace/coverage/default/45.sram_ctrl_stress_all.2850063289
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2668126940
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2207119166
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2034196988
/workspace/coverage/default/46.sram_ctrl_alert_test.2624558270
/workspace/coverage/default/46.sram_ctrl_bijection.3648531969
/workspace/coverage/default/46.sram_ctrl_executable.1551429947
/workspace/coverage/default/46.sram_ctrl_lc_escalation.511199933
/workspace/coverage/default/46.sram_ctrl_max_throughput.885192145
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1076641303
/workspace/coverage/default/46.sram_ctrl_mem_walk.2018220168
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3858295732
/workspace/coverage/default/46.sram_ctrl_partial_access.1013254861
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1249643027
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1674803974
/workspace/coverage/default/46.sram_ctrl_regwen.2757964461
/workspace/coverage/default/46.sram_ctrl_smoke.1154934579
/workspace/coverage/default/46.sram_ctrl_stress_all.3724427383
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.353004701
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.702002431
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.877514078
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1319956764
/workspace/coverage/default/47.sram_ctrl_alert_test.1345246030
/workspace/coverage/default/47.sram_ctrl_bijection.3993481698
/workspace/coverage/default/47.sram_ctrl_executable.1161587797
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3787807985
/workspace/coverage/default/47.sram_ctrl_max_throughput.3123362839
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1076301954
/workspace/coverage/default/47.sram_ctrl_mem_walk.206978854
/workspace/coverage/default/47.sram_ctrl_multiple_keys.782392770
/workspace/coverage/default/47.sram_ctrl_partial_access.376768349
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2861131815
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3972870156
/workspace/coverage/default/47.sram_ctrl_regwen.3949085157
/workspace/coverage/default/47.sram_ctrl_smoke.466591674
/workspace/coverage/default/47.sram_ctrl_stress_all.1831510286
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1571601073
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.557264449
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1464807156
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3920276678
/workspace/coverage/default/48.sram_ctrl_alert_test.335878968
/workspace/coverage/default/48.sram_ctrl_bijection.2579711913
/workspace/coverage/default/48.sram_ctrl_executable.3615333300
/workspace/coverage/default/48.sram_ctrl_lc_escalation.702845315
/workspace/coverage/default/48.sram_ctrl_max_throughput.4216822405
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.455615598
/workspace/coverage/default/48.sram_ctrl_mem_walk.1098770365
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2683694146
/workspace/coverage/default/48.sram_ctrl_partial_access.1170699965
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.20930220
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1635562140
/workspace/coverage/default/48.sram_ctrl_regwen.2517352760
/workspace/coverage/default/48.sram_ctrl_smoke.3234149156
/workspace/coverage/default/48.sram_ctrl_stress_all.4023730171
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3149690585
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.288967949
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.388640080
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.475856647
/workspace/coverage/default/49.sram_ctrl_alert_test.935349496
/workspace/coverage/default/49.sram_ctrl_bijection.2657249189
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1463958584
/workspace/coverage/default/49.sram_ctrl_max_throughput.80160221
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3842666586
/workspace/coverage/default/49.sram_ctrl_mem_walk.41377034
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2034827750
/workspace/coverage/default/49.sram_ctrl_partial_access.191210493
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1335248289
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1386116182
/workspace/coverage/default/49.sram_ctrl_regwen.3901231531
/workspace/coverage/default/49.sram_ctrl_smoke.2785431956
/workspace/coverage/default/49.sram_ctrl_stress_all.168384797
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1272183945
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.827656600
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1490994872
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2471138337
/workspace/coverage/default/5.sram_ctrl_alert_test.151343690
/workspace/coverage/default/5.sram_ctrl_bijection.454413966
/workspace/coverage/default/5.sram_ctrl_executable.1388990436
/workspace/coverage/default/5.sram_ctrl_lc_escalation.354225924
/workspace/coverage/default/5.sram_ctrl_max_throughput.747649512
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2932393583
/workspace/coverage/default/5.sram_ctrl_mem_walk.2755098132
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1552717648
/workspace/coverage/default/5.sram_ctrl_partial_access.1717484265
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2799503310
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3301720337
/workspace/coverage/default/5.sram_ctrl_regwen.3980799622
/workspace/coverage/default/5.sram_ctrl_smoke.115677769
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1089699726
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.338408840
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.976353416
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2098429879
/workspace/coverage/default/6.sram_ctrl_alert_test.374906215
/workspace/coverage/default/6.sram_ctrl_bijection.2320110538
/workspace/coverage/default/6.sram_ctrl_executable.4125175426
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3023178378
/workspace/coverage/default/6.sram_ctrl_max_throughput.1171371785
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3384684704
/workspace/coverage/default/6.sram_ctrl_mem_walk.1337744229
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1567137647
/workspace/coverage/default/6.sram_ctrl_partial_access.509709031
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.845377575
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1539799856
/workspace/coverage/default/6.sram_ctrl_regwen.36609242
/workspace/coverage/default/6.sram_ctrl_smoke.1825035506
/workspace/coverage/default/6.sram_ctrl_stress_all.1334722114
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1386295718
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3273513473
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2831274087
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.593480585
/workspace/coverage/default/7.sram_ctrl_alert_test.1463319750
/workspace/coverage/default/7.sram_ctrl_bijection.2436019853
/workspace/coverage/default/7.sram_ctrl_executable.613479494
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2189279748
/workspace/coverage/default/7.sram_ctrl_max_throughput.227951998
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.540617216
/workspace/coverage/default/7.sram_ctrl_mem_walk.2502265992
/workspace/coverage/default/7.sram_ctrl_multiple_keys.245914610
/workspace/coverage/default/7.sram_ctrl_partial_access.3589392506
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.736984727
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3708800868
/workspace/coverage/default/7.sram_ctrl_regwen.2234461437
/workspace/coverage/default/7.sram_ctrl_smoke.4267975850
/workspace/coverage/default/7.sram_ctrl_stress_all.1924715604
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2917386812
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1172458912
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.63791875
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2634752856
/workspace/coverage/default/8.sram_ctrl_alert_test.2246107870
/workspace/coverage/default/8.sram_ctrl_bijection.4021207123
/workspace/coverage/default/8.sram_ctrl_executable.1766083007
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1380489479
/workspace/coverage/default/8.sram_ctrl_max_throughput.2492049416
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3935804475
/workspace/coverage/default/8.sram_ctrl_mem_walk.2761829068
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1023689281
/workspace/coverage/default/8.sram_ctrl_partial_access.2363876241
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1827993283
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3236774719
/workspace/coverage/default/8.sram_ctrl_regwen.185616878
/workspace/coverage/default/8.sram_ctrl_smoke.3173190410
/workspace/coverage/default/8.sram_ctrl_stress_all.3708051055
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.175117871
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3768476449
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2698117753
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.940549169
/workspace/coverage/default/9.sram_ctrl_alert_test.95825297
/workspace/coverage/default/9.sram_ctrl_bijection.146653698
/workspace/coverage/default/9.sram_ctrl_executable.4232989911
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2409590269
/workspace/coverage/default/9.sram_ctrl_max_throughput.4137976769
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2669037775
/workspace/coverage/default/9.sram_ctrl_mem_walk.820334964
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3939412193
/workspace/coverage/default/9.sram_ctrl_partial_access.2597934516
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.136005391
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2304039983
/workspace/coverage/default/9.sram_ctrl_regwen.1437208778
/workspace/coverage/default/9.sram_ctrl_smoke.313249914
/workspace/coverage/default/9.sram_ctrl_stress_all.2910369640
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.89372299
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4256280115
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1295032792

Total test records in report: 1036

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/17.sram_ctrl_partial_access.3028314736	Mar 21 01:26:01 PM PDT 24	Mar 21 01:26:31 PM PDT 24	672161401 ps
T2	/workspace/coverage/default/17.sram_ctrl_ram_cfg.677041030	Mar 21 01:26:05 PM PDT 24	Mar 21 01:26:08 PM PDT 24	1408034066 ps
T3	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2198827502	Mar 21 01:28:38 PM PDT 24	Mar 21 01:38:17 PM PDT 24	10964378276 ps
T4	/workspace/coverage/default/32.sram_ctrl_partial_access.1414600679	Mar 21 01:26:49 PM PDT 24	Mar 21 01:28:57 PM PDT 24	1319145725 ps
T5	/workspace/coverage/default/32.sram_ctrl_lc_escalation.308381895	Mar 21 01:26:58 PM PDT 24	Mar 21 01:28:17 PM PDT 24	13475786171 ps
T8	/workspace/coverage/default/19.sram_ctrl_ram_cfg.435345999	Mar 21 01:26:17 PM PDT 24	Mar 21 01:26:21 PM PDT 24	3742198134 ps
T9	/workspace/coverage/default/11.sram_ctrl_partial_access.2213493896	Mar 21 01:25:35 PM PDT 24	Mar 21 01:25:52 PM PDT 24	818383962 ps
T10	/workspace/coverage/default/30.sram_ctrl_executable.90740446	Mar 21 01:26:43 PM PDT 24	Mar 21 01:41:50 PM PDT 24	4738557253 ps
T11	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1295032792	Mar 21 01:25:37 PM PDT 24	Mar 21 01:26:18 PM PDT 24	752751250 ps
T12	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3301041043	Mar 21 01:27:26 PM PDT 24	Mar 21 01:28:18 PM PDT 24	1433556763 ps
T13	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1036715688	Mar 21 01:28:00 PM PDT 24	Mar 21 01:28:51 PM PDT 24	12686563427 ps
T14	/workspace/coverage/default/38.sram_ctrl_bijection.2330279188	Mar 21 01:27:32 PM PDT 24	Mar 21 01:43:59 PM PDT 24	49203239352 ps
T23	/workspace/coverage/default/45.sram_ctrl_bijection.3912116944	Mar 21 01:28:26 PM PDT 24	Mar 21 02:12:00 PM PDT 24	115095574638 ps
T15	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.3585356945	Mar 21 01:26:06 PM PDT 24	Mar 21 01:41:09 PM PDT 24	15324387770 ps
T16	/workspace/coverage/default/8.sram_ctrl_stress_all.3708051055	Mar 21 01:25:28 PM PDT 24	Mar 21 03:07:57 PM PDT 24	62233523826 ps
T17	/workspace/coverage/default/7.sram_ctrl_alert_test.1463319750	Mar 21 01:25:58 PM PDT 24	Mar 21 01:25:59 PM PDT 24	15540551 ps
T6	/workspace/coverage/default/35.sram_ctrl_lc_escalation.2120923608	Mar 21 01:27:26 PM PDT 24	Mar 21 01:28:07 PM PDT 24	13554748959 ps
T7	/workspace/coverage/default/37.sram_ctrl_stress_all.2526917881	Mar 21 01:27:23 PM PDT 24	Mar 21 02:32:19 PM PDT 24	94595048980 ps
T49	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2842409505	Mar 21 01:27:00 PM PDT 24	Mar 21 01:30:42 PM PDT 24	4573286373 ps
T24	/workspace/coverage/default/15.sram_ctrl_stress_all.887801292	Mar 21 01:26:03 PM PDT 24	Mar 21 02:24:23 PM PDT 24	520122175798 ps
T80	/workspace/coverage/default/41.sram_ctrl_bijection.2354665911	Mar 21 01:27:49 PM PDT 24	Mar 21 01:56:42 PM PDT 24	51661037347 ps
T81	/workspace/coverage/default/32.sram_ctrl_smoke.619811479	Mar 21 01:26:57 PM PDT 24	Mar 21 01:27:24 PM PDT 24	812040198 ps
T50	/workspace/coverage/default/48.sram_ctrl_regwen.2517352760	Mar 21 01:28:57 PM PDT 24	Mar 21 01:53:37 PM PDT 24	23440734729 ps
T82	/workspace/coverage/default/39.sram_ctrl_multiple_keys.3158516266	Mar 21 01:27:38 PM PDT 24	Mar 21 01:37:32 PM PDT 24	62692490590 ps
T39	/workspace/coverage/default/6.sram_ctrl_executable.4125175426	Mar 21 01:26:06 PM PDT 24	Mar 21 01:50:41 PM PDT 24	38498135996 ps
T83	/workspace/coverage/default/3.sram_ctrl_partial_access.3414842342	Mar 21 01:25:21 PM PDT 24	Mar 21 01:25:36 PM PDT 24	550474265 ps
T64	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3479791202	Mar 21 01:26:16 PM PDT 24	Mar 21 01:40:28 PM PDT 24	33994592654 ps
T65	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.398075387	Mar 21 01:28:21 PM PDT 24	Mar 21 01:30:25 PM PDT 24	8692049019 ps
T68	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2788419653	Mar 21 01:27:32 PM PDT 24	Mar 21 01:29:57 PM PDT 24	20364004127 ps
T69	/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2626531891	Mar 21 01:26:47 PM PDT 24	Mar 21 01:29:02 PM PDT 24	9769642917 ps
T51	/workspace/coverage/default/26.sram_ctrl_lc_escalation.2227134969	Mar 21 01:26:12 PM PDT 24	Mar 21 01:26:47 PM PDT 24	10881118111 ps
T28	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.469793860	Mar 21 01:25:23 PM PDT 24	Mar 21 01:25:41 PM PDT 24	792444937 ps
T70	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3992893848	Mar 21 01:26:59 PM PDT 24	Mar 21 01:41:41 PM PDT 24	16996656407 ps
T29	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2026779688	Mar 21 01:27:02 PM PDT 24	Mar 21 01:30:10 PM PDT 24	9403348709 ps
T52	/workspace/coverage/default/1.sram_ctrl_regwen.750120635	Mar 21 01:25:22 PM PDT 24	Mar 21 01:27:58 PM PDT 24	3684170363 ps
T90	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.513123	Mar 21 01:26:22 PM PDT 24	Mar 21 01:31:30 PM PDT 24	16784954330 ps
T71	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2365565712	Mar 21 01:28:11 PM PDT 24	Mar 21 01:30:30 PM PDT 24	4498061490 ps
T91	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2660809127	Mar 21 01:26:31 PM PDT 24	Mar 21 01:30:17 PM PDT 24	20220384716 ps
T25	/workspace/coverage/default/5.sram_ctrl_stress_all.3418286321	Mar 21 01:25:24 PM PDT 24	Mar 21 03:18:45 PM PDT 24	104383895950 ps
T18	/workspace/coverage/default/28.sram_ctrl_alert_test.1520571984	Mar 21 01:26:31 PM PDT 24	Mar 21 01:26:32 PM PDT 24	31497331 ps
T105	/workspace/coverage/default/46.sram_ctrl_smoke.1154934579	Mar 21 01:28:31 PM PDT 24	Mar 21 01:28:48 PM PDT 24	543282057 ps
T53	/workspace/coverage/default/20.sram_ctrl_lc_escalation.2642190313	Mar 21 01:26:14 PM PDT 24	Mar 21 01:27:01 PM PDT 24	8447829444 ps
T42	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.175117871	Mar 21 01:25:35 PM PDT 24	Mar 21 01:25:51 PM PDT 24	2006968031 ps
T125	/workspace/coverage/default/36.sram_ctrl_bijection.1739674585	Mar 21 01:27:27 PM PDT 24	Mar 21 01:50:44 PM PDT 24	207662666479 ps
T30	/workspace/coverage/default/48.sram_ctrl_ram_cfg.1635562140	Mar 21 01:28:58 PM PDT 24	Mar 21 01:29:01 PM PDT 24	360585035 ps
T127	/workspace/coverage/default/22.sram_ctrl_partial_access.1852701410	Mar 21 01:26:19 PM PDT 24	Mar 21 01:26:37 PM PDT 24	1373129107 ps
T128	/workspace/coverage/default/30.sram_ctrl_multiple_keys.73691094	Mar 21 01:26:38 PM PDT 24	Mar 21 01:52:42 PM PDT 24	39071615881 ps
T40	/workspace/coverage/default/43.sram_ctrl_executable.1765516709	Mar 21 01:28:12 PM PDT 24	Mar 21 01:42:39 PM PDT 24	89248144224 ps
T129	/workspace/coverage/default/31.sram_ctrl_ram_cfg.2734109983	Mar 21 01:26:48 PM PDT 24	Mar 21 01:26:52 PM PDT 24	1401534503 ps
T130	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3083614746	Mar 21 01:27:33 PM PDT 24	Mar 21 01:27:58 PM PDT 24	2985975186 ps
T41	/workspace/coverage/default/21.sram_ctrl_stress_all.1785487721	Mar 21 01:26:07 PM PDT 24	Mar 21 02:17:10 PM PDT 24	130295455486 ps
T20	/workspace/coverage/default/0.sram_ctrl_sec_cm.1926974385	Mar 21 01:25:18 PM PDT 24	Mar 21 01:25:24 PM PDT 24	1220547831 ps
T33	/workspace/coverage/default/40.sram_ctrl_smoke.3908522886	Mar 21 01:27:47 PM PDT 24	Mar 21 01:29:00 PM PDT 24	1553041437 ps
T34	/workspace/coverage/default/33.sram_ctrl_executable.203492071	Mar 21 01:27:02 PM PDT 24	Mar 21 01:40:20 PM PDT 24	12122520121 ps
T26	/workspace/coverage/default/21.sram_ctrl_lc_escalation.3621629919	Mar 21 01:26:08 PM PDT 24	Mar 21 01:27:06 PM PDT 24	35679039662 ps
T27	/workspace/coverage/default/17.sram_ctrl_lc_escalation.1209036272	Mar 21 01:25:54 PM PDT 24	Mar 21 01:27:13 PM PDT 24	14249882719 ps
T35	/workspace/coverage/default/31.sram_ctrl_max_throughput.1789309708	Mar 21 01:26:48 PM PDT 24	Mar 21 01:28:30 PM PDT 24	817838424 ps
T36	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.3051749747	Mar 21 01:26:29 PM PDT 24	Mar 21 01:33:41 PM PDT 24	29137500464 ps
T19	/workspace/coverage/default/4.sram_ctrl_alert_test.3265873618	Mar 21 01:25:26 PM PDT 24	Mar 21 01:25:27 PM PDT 24	14540405 ps
T37	/workspace/coverage/default/0.sram_ctrl_partial_access.713015901	Mar 21 01:25:11 PM PDT 24	Mar 21 01:25:37 PM PDT 24	3817651604 ps
T38	/workspace/coverage/default/14.sram_ctrl_partial_access.3735309102	Mar 21 01:25:55 PM PDT 24	Mar 21 01:26:06 PM PDT 24	3746365036 ps
T131	/workspace/coverage/default/6.sram_ctrl_mem_walk.1337744229	Mar 21 01:25:55 PM PDT 24	Mar 21 01:30:41 PM PDT 24	27498255911 ps
T132	/workspace/coverage/default/43.sram_ctrl_lc_escalation.2534145265	Mar 21 01:28:10 PM PDT 24	Mar 21 01:29:46 PM PDT 24	77048621354 ps
T133	/workspace/coverage/default/15.sram_ctrl_smoke.1235230999	Mar 21 01:25:44 PM PDT 24	Mar 21 01:25:54 PM PDT 24	433270255 ps
T134	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3517975236	Mar 21 01:26:14 PM PDT 24	Mar 21 01:30:31 PM PDT 24	12536953789 ps
T135	/workspace/coverage/default/6.sram_ctrl_lc_escalation.3023178378	Mar 21 01:25:36 PM PDT 24	Mar 21 01:26:05 PM PDT 24	5465123970 ps
T136	/workspace/coverage/default/42.sram_ctrl_multiple_keys.3380803678	Mar 21 01:27:53 PM PDT 24	Mar 21 01:35:51 PM PDT 24	45932025281 ps
T137	/workspace/coverage/default/29.sram_ctrl_multiple_keys.1158224134	Mar 21 01:26:23 PM PDT 24	Mar 21 01:38:05 PM PDT 24	56378433600 ps
T126	/workspace/coverage/default/47.sram_ctrl_stress_all.1831510286	Mar 21 01:28:51 PM PDT 24	Mar 21 04:24:21 PM PDT 24	1169505688637 ps
T138	/workspace/coverage/default/8.sram_ctrl_smoke.3173190410	Mar 21 01:25:50 PM PDT 24	Mar 21 01:26:13 PM PDT 24	13407658304 ps
T139	/workspace/coverage/default/24.sram_ctrl_smoke.172600632	Mar 21 01:26:09 PM PDT 24	Mar 21 01:28:39 PM PDT 24	1298325531 ps
T140	/workspace/coverage/default/26.sram_ctrl_multiple_keys.3156836037	Mar 21 01:26:19 PM PDT 24	Mar 21 01:44:42 PM PDT 24	14067700599 ps
T124	/workspace/coverage/default/45.sram_ctrl_executable.3802436305	Mar 21 01:28:31 PM PDT 24	Mar 21 01:46:17 PM PDT 24	21096724772 ps
T141	/workspace/coverage/default/35.sram_ctrl_regwen.4160893254	Mar 21 01:27:26 PM PDT 24	Mar 21 01:33:47 PM PDT 24	4891259716 ps
T142	/workspace/coverage/default/23.sram_ctrl_partial_access.2243500815	Mar 21 01:26:18 PM PDT 24	Mar 21 01:28:11 PM PDT 24	831528015 ps
T43	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1875083005	Mar 21 01:27:47 PM PDT 24	Mar 21 01:28:00 PM PDT 24	513726566 ps
T143	/workspace/coverage/default/2.sram_ctrl_alert_test.4292735410	Mar 21 01:25:21 PM PDT 24	Mar 21 01:25:22 PM PDT 24	20558464 ps
T144	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.647678087	Mar 21 01:25:21 PM PDT 24	Mar 21 01:26:00 PM PDT 24	758642689 ps
T145	/workspace/coverage/default/31.sram_ctrl_bijection.1743566563	Mar 21 01:26:49 PM PDT 24	Mar 21 02:03:54 PM PDT 24	33134907028 ps
T146	/workspace/coverage/default/10.sram_ctrl_executable.3919205125	Mar 21 01:25:57 PM PDT 24	Mar 21 01:31:23 PM PDT 24	19192689436 ps
T147	/workspace/coverage/default/36.sram_ctrl_executable.4174009155	Mar 21 01:27:27 PM PDT 24	Mar 21 01:51:43 PM PDT 24	40078013769 ps
T148	/workspace/coverage/default/11.sram_ctrl_lc_escalation.1430374860	Mar 21 01:25:33 PM PDT 24	Mar 21 01:26:38 PM PDT 24	10230697570 ps
T149	/workspace/coverage/default/35.sram_ctrl_partial_access.1005320844	Mar 21 01:27:26 PM PDT 24	Mar 21 01:27:45 PM PDT 24	882494705 ps
T78	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1751178369	Mar 21 01:26:06 PM PDT 24	Mar 21 01:27:08 PM PDT 24	3950233912 ps
T150	/workspace/coverage/default/20.sram_ctrl_executable.3681303358	Mar 21 01:25:57 PM PDT 24	Mar 21 01:34:45 PM PDT 24	3953410889 ps
T151	/workspace/coverage/default/0.sram_ctrl_mem_walk.1647710453	Mar 21 01:25:23 PM PDT 24	Mar 21 01:27:46 PM PDT 24	14357906099 ps
T92	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.478316242	Mar 21 01:26:58 PM PDT 24	Mar 21 01:31:00 PM PDT 24	24466146617 ps
T152	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.485540216	Mar 21 01:26:59 PM PDT 24	Mar 21 01:27:31 PM PDT 24	729358440 ps
T153	/workspace/coverage/default/38.sram_ctrl_multiple_keys.1068356522	Mar 21 01:27:32 PM PDT 24	Mar 21 01:41:19 PM PDT 24	45979976776 ps
T154	/workspace/coverage/default/41.sram_ctrl_alert_test.4110838593	Mar 21 01:27:59 PM PDT 24	Mar 21 01:28:00 PM PDT 24	50500371 ps
T79	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1936675967	Mar 21 01:25:23 PM PDT 24	Mar 21 01:27:53 PM PDT 24	10487927143 ps
T155	/workspace/coverage/default/32.sram_ctrl_alert_test.225397189	Mar 21 01:26:57 PM PDT 24	Mar 21 01:26:58 PM PDT 24	54138366 ps
T156	/workspace/coverage/default/40.sram_ctrl_partial_access.2465255688	Mar 21 01:27:45 PM PDT 24	Mar 21 01:28:01 PM PDT 24	3602585690 ps
T157	/workspace/coverage/default/16.sram_ctrl_ram_cfg.2892014140	Mar 21 01:26:06 PM PDT 24	Mar 21 01:26:09 PM PDT 24	352353493 ps
T158	/workspace/coverage/default/25.sram_ctrl_smoke.1054826956	Mar 21 01:26:10 PM PDT 24	Mar 21 01:26:25 PM PDT 24	6040992669 ps
T93	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.76348975	Mar 21 01:27:36 PM PDT 24	Mar 21 01:34:54 PM PDT 24	8639810182 ps
T44	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.353004701	Mar 21 01:28:50 PM PDT 24	Mar 21 01:29:54 PM PDT 24	3476724278 ps
T159	/workspace/coverage/default/12.sram_ctrl_regwen.870350623	Mar 21 01:25:42 PM PDT 24	Mar 21 01:36:01 PM PDT 24	52556403178 ps
T160	/workspace/coverage/default/49.sram_ctrl_bijection.2657249189	Mar 21 01:28:55 PM PDT 24	Mar 21 02:13:07 PM PDT 24	528620802947 ps
T45	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2239299803	Mar 21 01:26:10 PM PDT 24	Mar 21 01:26:37 PM PDT 24	931936680 ps
T161	/workspace/coverage/default/14.sram_ctrl_max_throughput.2905831714	Mar 21 01:26:07 PM PDT 24	Mar 21 01:27:15 PM PDT 24	5228796879 ps
T117	/workspace/coverage/default/41.sram_ctrl_regwen.3053825429	Mar 21 01:27:54 PM PDT 24	Mar 21 01:36:01 PM PDT 24	4909070751 ps
T162	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.51521898	Mar 21 01:28:29 PM PDT 24	Mar 21 01:32:12 PM PDT 24	4210779473 ps
T163	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2748949172	Mar 21 01:27:59 PM PDT 24	Mar 21 01:28:33 PM PDT 24	721396573 ps
T164	/workspace/coverage/default/7.sram_ctrl_regwen.2234461437	Mar 21 01:25:24 PM PDT 24	Mar 21 01:28:42 PM PDT 24	13968048830 ps
T165	/workspace/coverage/default/29.sram_ctrl_bijection.3300918241	Mar 21 01:26:22 PM PDT 24	Mar 21 02:05:53 PM PDT 24	413973681235 ps
T166	/workspace/coverage/default/31.sram_ctrl_regwen.2726387972	Mar 21 01:26:47 PM PDT 24	Mar 21 01:31:54 PM PDT 24	9586398028 ps
T46	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3377617613	Mar 21 01:25:48 PM PDT 24	Mar 21 01:28:55 PM PDT 24	4002217903 ps
T167	/workspace/coverage/default/14.sram_ctrl_mem_walk.2890394116	Mar 21 01:26:01 PM PDT 24	Mar 21 01:31:03 PM PDT 24	41241843171 ps
T47	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3839362419	Mar 21 01:27:36 PM PDT 24	Mar 21 01:28:36 PM PDT 24	2581632558 ps
T168	/workspace/coverage/default/13.sram_ctrl_ram_cfg.2054755650	Mar 21 01:26:00 PM PDT 24	Mar 21 01:26:03 PM PDT 24	344594651 ps
T169	/workspace/coverage/default/36.sram_ctrl_smoke.395749892	Mar 21 01:27:29 PM PDT 24	Mar 21 01:27:35 PM PDT 24	772966723 ps
T170	/workspace/coverage/default/5.sram_ctrl_executable.1388990436	Mar 21 01:25:24 PM PDT 24	Mar 21 01:33:21 PM PDT 24	9292167018 ps
T118	/workspace/coverage/default/32.sram_ctrl_stress_all.755146328	Mar 21 01:26:57 PM PDT 24	Mar 21 02:46:00 PM PDT 24	214264194144 ps
T171	/workspace/coverage/default/36.sram_ctrl_max_throughput.2986450545	Mar 21 01:27:28 PM PDT 24	Mar 21 01:28:47 PM PDT 24	4649836628 ps
T172	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.824444183	Mar 21 01:28:28 PM PDT 24	Mar 21 01:44:52 PM PDT 24	60217289178 ps
T173	/workspace/coverage/default/32.sram_ctrl_mem_walk.1006089145	Mar 21 01:26:51 PM PDT 24	Mar 21 01:31:31 PM PDT 24	14352793674 ps
T174	/workspace/coverage/default/5.sram_ctrl_max_throughput.747649512	Mar 21 01:25:27 PM PDT 24	Mar 21 01:27:26 PM PDT 24	3147231201 ps
T48	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3998654623	Mar 21 01:26:31 PM PDT 24	Mar 21 01:26:59 PM PDT 24	1197509355 ps
T175	/workspace/coverage/default/12.sram_ctrl_multiple_keys.3248285653	Mar 21 01:26:03 PM PDT 24	Mar 21 01:37:41 PM PDT 24	15209715842 ps
T176	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.20930220	Mar 21 01:28:48 PM PDT 24	Mar 21 01:33:35 PM PDT 24	12635070085 ps
T177	/workspace/coverage/default/33.sram_ctrl_bijection.3894643021	Mar 21 01:26:57 PM PDT 24	Mar 21 02:03:36 PM PDT 24	364632432818 ps
T178	/workspace/coverage/default/49.sram_ctrl_ram_cfg.1386116182	Mar 21 01:29:02 PM PDT 24	Mar 21 01:29:06 PM PDT 24	360432962 ps
T179	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2812072902	Mar 21 01:26:29 PM PDT 24	Mar 21 01:27:49 PM PDT 24	5129043238 ps
T180	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2992407352	Mar 21 01:28:38 PM PDT 24	Mar 21 01:32:41 PM PDT 24	12922985662 ps
T181	/workspace/coverage/default/6.sram_ctrl_max_throughput.1171371785	Mar 21 01:25:31 PM PDT 24	Mar 21 01:25:46 PM PDT 24	714547661 ps
T182	/workspace/coverage/default/14.sram_ctrl_multiple_keys.1667290896	Mar 21 01:25:54 PM PDT 24	Mar 21 01:34:49 PM PDT 24	6859890784 ps
T183	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.4209383663	Mar 21 01:26:08 PM PDT 24	Mar 21 01:27:09 PM PDT 24	994205868 ps
T184	/workspace/coverage/default/22.sram_ctrl_lc_escalation.2208645274	Mar 21 01:26:09 PM PDT 24	Mar 21 01:26:39 PM PDT 24	4837604927 ps
T185	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.63791875	Mar 21 01:25:35 PM PDT 24	Mar 21 01:27:18 PM PDT 24	774360161 ps
T186	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3384924742	Mar 21 01:28:04 PM PDT 24	Mar 21 01:48:29 PM PDT 24	130422026135 ps
T187	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3202787562	Mar 21 01:27:56 PM PDT 24	Mar 21 01:29:09 PM PDT 24	2544150964 ps
T188	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2034196988	Mar 21 01:28:35 PM PDT 24	Mar 21 01:31:07 PM PDT 24	1505109065 ps
T189	/workspace/coverage/default/7.sram_ctrl_partial_access.3589392506	Mar 21 01:25:33 PM PDT 24	Mar 21 01:25:58 PM PDT 24	3065263101 ps
T190	/workspace/coverage/default/40.sram_ctrl_executable.3205632626	Mar 21 01:27:48 PM PDT 24	Mar 21 01:39:13 PM PDT 24	13622921237 ps
T191	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2621162638	Mar 21 01:26:10 PM PDT 24	Mar 21 01:27:05 PM PDT 24	2869053140 ps
T192	/workspace/coverage/default/28.sram_ctrl_lc_escalation.1020645435	Mar 21 01:26:20 PM PDT 24	Mar 21 01:26:55 PM PDT 24	6467955263 ps
T193	/workspace/coverage/default/16.sram_ctrl_mem_walk.3032761169	Mar 21 01:25:56 PM PDT 24	Mar 21 01:30:15 PM PDT 24	9616651386 ps
T194	/workspace/coverage/default/8.sram_ctrl_bijection.4021207123	Mar 21 01:25:54 PM PDT 24	Mar 21 01:43:34 PM PDT 24	184925200566 ps
T195	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.540617216	Mar 21 01:25:34 PM PDT 24	Mar 21 01:26:34 PM PDT 24	1946947058 ps
T196	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.174357570	Mar 21 01:26:01 PM PDT 24	Mar 21 01:27:18 PM PDT 24	2485008861 ps
T197	/workspace/coverage/default/32.sram_ctrl_executable.1389535040	Mar 21 01:26:50 PM PDT 24	Mar 21 01:40:33 PM PDT 24	6748216894 ps
T198	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2658044505	Mar 21 01:25:57 PM PDT 24	Mar 21 01:28:08 PM PDT 24	2236181869 ps
T199	/workspace/coverage/default/36.sram_ctrl_regwen.4248535186	Mar 21 01:27:28 PM PDT 24	Mar 21 01:32:17 PM PDT 24	5070426896 ps
T200	/workspace/coverage/default/10.sram_ctrl_multiple_keys.4126648399	Mar 21 01:25:38 PM PDT 24	Mar 21 01:26:16 PM PDT 24	5016738219 ps
T201	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3322284969	Mar 21 01:27:34 PM PDT 24	Mar 21 01:33:40 PM PDT 24	28640346120 ps
T202	/workspace/coverage/default/8.sram_ctrl_mem_walk.2761829068	Mar 21 01:26:00 PM PDT 24	Mar 21 01:28:30 PM PDT 24	7031533247 ps
T203	/workspace/coverage/default/23.sram_ctrl_mem_walk.2736822403	Mar 21 01:26:26 PM PDT 24	Mar 21 01:31:54 PM PDT 24	41351481354 ps
T204	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.2158462825	Mar 21 01:26:25 PM PDT 24	Mar 21 01:27:44 PM PDT 24	2899233689 ps
T205	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.604882810	Mar 21 01:26:16 PM PDT 24	Mar 21 01:27:22 PM PDT 24	1929816030 ps
T206	/workspace/coverage/default/13.sram_ctrl_lc_escalation.1779329871	Mar 21 01:25:59 PM PDT 24	Mar 21 01:26:19 PM PDT 24	6147857764 ps
T207	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3853019000	Mar 21 01:27:56 PM PDT 24	Mar 21 01:31:00 PM PDT 24	3303237916 ps
T208	/workspace/coverage/default/39.sram_ctrl_executable.884990704	Mar 21 01:27:50 PM PDT 24	Mar 21 01:45:20 PM PDT 24	54650132061 ps
T209	/workspace/coverage/default/3.sram_ctrl_mem_walk.2007991322	Mar 21 01:25:23 PM PDT 24	Mar 21 01:30:41 PM PDT 24	86051422170 ps
T210	/workspace/coverage/default/44.sram_ctrl_ram_cfg.499846715	Mar 21 01:28:28 PM PDT 24	Mar 21 01:28:31 PM PDT 24	710556612 ps
T211	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1153126656	Mar 21 01:27:00 PM PDT 24	Mar 21 01:29:04 PM PDT 24	3132557039 ps
T212	/workspace/coverage/default/44.sram_ctrl_smoke.3223413480	Mar 21 01:28:13 PM PDT 24	Mar 21 01:28:21 PM PDT 24	2146432194 ps
T213	/workspace/coverage/default/3.sram_ctrl_smoke.1285095647	Mar 21 01:25:19 PM PDT 24	Mar 21 01:25:40 PM PDT 24	10921925665 ps
T214	/workspace/coverage/default/22.sram_ctrl_executable.2688456624	Mar 21 01:26:15 PM PDT 24	Mar 21 01:33:17 PM PDT 24	12475274974 ps
T215	/workspace/coverage/default/26.sram_ctrl_bijection.1647878648	Mar 21 01:26:17 PM PDT 24	Mar 21 02:10:04 PM PDT 24	166939595905 ps
T216	/workspace/coverage/default/11.sram_ctrl_smoke.1452819202	Mar 21 01:25:36 PM PDT 24	Mar 21 01:28:00 PM PDT 24	1196366051 ps
T217	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3574436214	Mar 21 01:26:07 PM PDT 24	Mar 21 01:26:33 PM PDT 24	1476143629 ps
T218	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2159614874	Mar 21 01:25:54 PM PDT 24	Mar 21 01:33:09 PM PDT 24	14885609645 ps
T219	/workspace/coverage/default/27.sram_ctrl_stress_all.3705669943	Mar 21 01:26:19 PM PDT 24	Mar 21 02:17:57 PM PDT 24	74713312170 ps
T220	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.610840635	Mar 21 01:26:15 PM PDT 24	Mar 21 01:29:13 PM PDT 24	15497076902 ps
T221	/workspace/coverage/default/35.sram_ctrl_stress_all.2622245552	Mar 21 01:27:27 PM PDT 24	Mar 21 03:13:59 PM PDT 24	645737866762 ps
T222	/workspace/coverage/default/36.sram_ctrl_ram_cfg.3652350329	Mar 21 01:27:28 PM PDT 24	Mar 21 01:27:32 PM PDT 24	2106614865 ps
T223	/workspace/coverage/default/32.sram_ctrl_regwen.2054317190	Mar 21 01:26:58 PM PDT 24	Mar 21 01:44:23 PM PDT 24	14460342959 ps
T224	/workspace/coverage/default/38.sram_ctrl_partial_access.2379211173	Mar 21 01:27:32 PM PDT 24	Mar 21 01:28:50 PM PDT 24	2515557069 ps
T225	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2823884652	Mar 21 01:25:34 PM PDT 24	Mar 21 01:33:32 PM PDT 24	88482462792 ps
T226	/workspace/coverage/default/38.sram_ctrl_stress_all.692265415	Mar 21 01:27:31 PM PDT 24	Mar 21 02:38:21 PM PDT 24	44205756632 ps
T227	/workspace/coverage/default/28.sram_ctrl_stress_all.947172973	Mar 21 01:26:28 PM PDT 24	Mar 21 01:48:00 PM PDT 24	248920037935 ps
T228	/workspace/coverage/default/46.sram_ctrl_executable.1551429947	Mar 21 01:28:41 PM PDT 24	Mar 21 01:44:53 PM PDT 24	59008866897 ps
T229	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1319956764	Mar 21 01:28:51 PM PDT 24	Mar 21 01:49:51 PM PDT 24	15081463057 ps
T230	/workspace/coverage/default/44.sram_ctrl_executable.2648256417	Mar 21 01:28:26 PM PDT 24	Mar 21 01:37:32 PM PDT 24	18618964227 ps
T231	/workspace/coverage/default/15.sram_ctrl_multiple_keys.3677482738	Mar 21 01:26:00 PM PDT 24	Mar 21 01:39:47 PM PDT 24	31572874192 ps
T232	/workspace/coverage/default/10.sram_ctrl_regwen.1629085224	Mar 21 01:25:28 PM PDT 24	Mar 21 01:30:14 PM PDT 24	10309701844 ps
T233	/workspace/coverage/default/42.sram_ctrl_max_throughput.3293852946	Mar 21 01:27:55 PM PDT 24	Mar 21 01:29:03 PM PDT 24	875467707 ps
T234	/workspace/coverage/default/18.sram_ctrl_max_throughput.1835470681	Mar 21 01:25:57 PM PDT 24	Mar 21 01:26:03 PM PDT 24	680963472 ps
T235	/workspace/coverage/default/47.sram_ctrl_bijection.3993481698	Mar 21 01:28:51 PM PDT 24	Mar 21 01:48:37 PM PDT 24	230717735106 ps
T236	/workspace/coverage/default/26.sram_ctrl_mem_walk.4247421453	Mar 21 01:26:18 PM PDT 24	Mar 21 01:28:43 PM PDT 24	7128059811 ps
T237	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2368827974	Mar 21 01:26:09 PM PDT 24	Mar 21 01:26:33 PM PDT 24	1726462984 ps
T238	/workspace/coverage/default/13.sram_ctrl_max_throughput.579204908	Mar 21 01:25:59 PM PDT 24	Mar 21 01:27:55 PM PDT 24	3178518709 ps
T239	/workspace/coverage/default/40.sram_ctrl_multiple_keys.4215011073	Mar 21 01:27:46 PM PDT 24	Mar 21 01:34:30 PM PDT 24	14403745261 ps
T240	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1578801583	Mar 21 01:25:23 PM PDT 24	Mar 21 01:30:21 PM PDT 24	9157811646 ps
T241	/workspace/coverage/default/11.sram_ctrl_ram_cfg.3530301062	Mar 21 01:25:55 PM PDT 24	Mar 21 01:25:58 PM PDT 24	705521366 ps
T242	/workspace/coverage/default/31.sram_ctrl_smoke.3469813782	Mar 21 01:26:49 PM PDT 24	Mar 21 01:26:53 PM PDT 24	646626643 ps
T243	/workspace/coverage/default/11.sram_ctrl_regwen.4255812328	Mar 21 01:25:29 PM PDT 24	Mar 21 01:29:30 PM PDT 24	5063409756 ps
T244	/workspace/coverage/default/15.sram_ctrl_mem_walk.1809033716	Mar 21 01:25:55 PM PDT 24	Mar 21 01:28:06 PM PDT 24	8600012050 ps
T245	/workspace/coverage/default/49.sram_ctrl_mem_walk.41377034	Mar 21 01:29:03 PM PDT 24	Mar 21 01:31:07 PM PDT 24	4114098230 ps
T246	/workspace/coverage/default/11.sram_ctrl_max_throughput.2062148333	Mar 21 01:25:45 PM PDT 24	Mar 21 01:25:52 PM PDT 24	679781190 ps
T247	/workspace/coverage/default/12.sram_ctrl_bijection.2086473995	Mar 21 01:26:08 PM PDT 24	Mar 21 01:47:49 PM PDT 24	230798049203 ps
T248	/workspace/coverage/default/39.sram_ctrl_smoke.2484287585	Mar 21 01:27:36 PM PDT 24	Mar 21 01:27:44 PM PDT 24	966461790 ps
T249	/workspace/coverage/default/47.sram_ctrl_smoke.466591674	Mar 21 01:28:41 PM PDT 24	Mar 21 01:31:04 PM PDT 24	1381000210 ps
T250	/workspace/coverage/default/35.sram_ctrl_alert_test.1342274613	Mar 21 01:27:26 PM PDT 24	Mar 21 01:27:28 PM PDT 24	160722137 ps
T251	/workspace/coverage/default/41.sram_ctrl_smoke.1833285447	Mar 21 01:27:50 PM PDT 24	Mar 21 01:28:28 PM PDT 24	555985562 ps
T252	/workspace/coverage/default/34.sram_ctrl_max_throughput.1282756389	Mar 21 01:27:00 PM PDT 24	Mar 21 01:28:30 PM PDT 24	3098864153 ps
T253	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.974393927	Mar 21 01:26:47 PM PDT 24	Mar 21 01:31:43 PM PDT 24	191215159685 ps
T254	/workspace/coverage/default/11.sram_ctrl_bijection.484818383	Mar 21 01:25:36 PM PDT 24	Mar 21 01:40:50 PM PDT 24	85017746504 ps
T255	/workspace/coverage/default/30.sram_ctrl_mem_walk.3758366413	Mar 21 01:26:35 PM PDT 24	Mar 21 01:30:24 PM PDT 24	8046875582 ps
T256	/workspace/coverage/default/20.sram_ctrl_stress_all.2528284528	Mar 21 01:26:20 PM PDT 24	Mar 21 03:02:23 PM PDT 24	942885263104 ps
T98	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2668126940	Mar 21 01:28:39 PM PDT 24	Mar 21 01:28:50 PM PDT 24	1629533938 ps
T257	/workspace/coverage/default/24.sram_ctrl_alert_test.1376675113	Mar 21 01:26:12 PM PDT 24	Mar 21 01:26:13 PM PDT 24	31890168 ps
T258	/workspace/coverage/default/45.sram_ctrl_partial_access.695130910	Mar 21 01:28:30 PM PDT 24	Mar 21 01:28:39 PM PDT 24	1738431780 ps
T259	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1730327879	Mar 21 01:28:21 PM PDT 24	Mar 21 01:30:14 PM PDT 24	6488350849 ps
T120	/workspace/coverage/default/39.sram_ctrl_regwen.1799637225	Mar 21 01:27:35 PM PDT 24	Mar 21 01:44:13 PM PDT 24	24074174624 ps
T260	/workspace/coverage/default/21.sram_ctrl_alert_test.4266823397	Mar 21 01:26:11 PM PDT 24	Mar 21 01:26:12 PM PDT 24	168110604 ps
T261	/workspace/coverage/default/9.sram_ctrl_mem_walk.820334964	Mar 21 01:25:38 PM PDT 24	Mar 21 01:28:00 PM PDT 24	20695523650 ps
T262	/workspace/coverage/default/44.sram_ctrl_mem_walk.769223826	Mar 21 01:28:27 PM PDT 24	Mar 21 01:30:59 PM PDT 24	20643990962 ps
T263	/workspace/coverage/default/21.sram_ctrl_partial_access.4177099743	Mar 21 01:26:01 PM PDT 24	Mar 21 01:27:54 PM PDT 24	946588759 ps
T264	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1680859509	Mar 21 01:25:25 PM PDT 24	Mar 21 01:32:40 PM PDT 24	7376736106 ps
T265	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3318760384	Mar 21 01:26:20 PM PDT 24	Mar 21 01:46:21 PM PDT 24	18047823819 ps
T266	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2729949464	Mar 21 01:26:49 PM PDT 24	Mar 21 01:29:17 PM PDT 24	6243738242 ps
T267	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1076301954	Mar 21 01:28:48 PM PDT 24	Mar 21 01:31:20 PM PDT 24	4445983284 ps
T268	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3621504711	Mar 21 01:27:32 PM PDT 24	Mar 21 01:30:02 PM PDT 24	18241804502 ps
T269	/workspace/coverage/default/27.sram_ctrl_mem_walk.3942779444	Mar 21 01:26:21 PM PDT 24	Mar 21 01:30:26 PM PDT 24	4109484049 ps
T270	/workspace/coverage/default/12.sram_ctrl_partial_access.1920137119	Mar 21 01:26:05 PM PDT 24	Mar 21 01:26:21 PM PDT 24	1267522359 ps
T271	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1501880817	Mar 21 01:26:07 PM PDT 24	Mar 21 01:26:52 PM PDT 24	771278646 ps
T272	/workspace/coverage/default/0.sram_ctrl_executable.4267651293	Mar 21 01:25:14 PM PDT 24	Mar 21 01:37:18 PM PDT 24	10031762127 ps
T273	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1706351047	Mar 21 01:25:34 PM PDT 24	Mar 21 01:26:39 PM PDT 24	15686527278 ps
T274	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2363851685	Mar 21 01:26:48 PM PDT 24	Mar 21 01:27:26 PM PDT 24	5164339492 ps
T275	/workspace/coverage/default/5.sram_ctrl_multiple_keys.1552717648	Mar 21 01:25:29 PM PDT 24	Mar 21 01:26:20 PM PDT 24	1744196596 ps
T276	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3768476449	Mar 21 01:25:32 PM PDT 24	Mar 21 01:28:37 PM PDT 24	3147107556 ps
T277	/workspace/coverage/default/2.sram_ctrl_ram_cfg.942973615	Mar 21 01:25:20 PM PDT 24	Mar 21 01:25:24 PM PDT 24	2249138046 ps
T278	/workspace/coverage/default/39.sram_ctrl_lc_escalation.3112340129	Mar 21 01:27:38 PM PDT 24	Mar 21 01:28:24 PM PDT 24	37425695135 ps
T279	/workspace/coverage/default/49.sram_ctrl_regwen.3901231531	Mar 21 01:29:04 PM PDT 24	Mar 21 01:44:01 PM PDT 24	16580049436 ps
T280	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2917386812	Mar 21 01:25:32 PM PDT 24	Mar 21 01:25:38 PM PDT 24	313430097 ps
T281	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1075185309	Mar 21 01:27:49 PM PDT 24	Mar 21 01:30:14 PM PDT 24	11112447934 ps
T282	/workspace/coverage/default/45.sram_ctrl_alert_test.1660402213	Mar 21 01:28:33 PM PDT 24	Mar 21 01:28:33 PM PDT 24	12915376 ps
T283	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.4112151737	Mar 21 01:26:19 PM PDT 24	Mar 21 01:28:54 PM PDT 24	3162033365 ps
T284	/workspace/coverage/default/37.sram_ctrl_smoke.3309866817	Mar 21 01:27:29 PM PDT 24	Mar 21 01:27:41 PM PDT 24	499919446 ps
T285	/workspace/coverage/default/0.sram_ctrl_bijection.2701833813	Mar 21 01:25:21 PM PDT 24	Mar 21 01:36:16 PM PDT 24	27977693708 ps
T21	/workspace/coverage/default/1.sram_ctrl_sec_cm.2668951508	Mar 21 01:25:22 PM PDT 24	Mar 21 01:25:26 PM PDT 24	973425801 ps
T99	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1418316857	Mar 21 01:25:56 PM PDT 24	Mar 21 01:30:02 PM PDT 24	7861510867 ps
T286	/workspace/coverage/default/31.sram_ctrl_alert_test.2312650275	Mar 21 01:26:50 PM PDT 24	Mar 21 01:26:51 PM PDT 24	42399228 ps
T287	/workspace/coverage/default/14.sram_ctrl_stress_all.2233336849	Mar 21 01:25:56 PM PDT 24	Mar 21 02:23:32 PM PDT 24	195052204803 ps
T100	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.235691178	Mar 21 01:26:05 PM PDT 24	Mar 21 01:26:34 PM PDT 24	1201777317 ps
T288	/workspace/coverage/default/18.sram_ctrl_ram_cfg.1048304108	Mar 21 01:26:07 PM PDT 24	Mar 21 01:26:10 PM PDT 24	356458356 ps
T289	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1386295718	Mar 21 01:25:52 PM PDT 24	Mar 21 01:26:13 PM PDT 24	767380618 ps
T290	/workspace/coverage/default/22.sram_ctrl_ram_cfg.2130638223	Mar 21 01:26:10 PM PDT 24	Mar 21 01:26:14 PM PDT 24	375220529 ps
T291	/workspace/coverage/default/36.sram_ctrl_multiple_keys.3300809571	Mar 21 01:27:27 PM PDT 24	Mar 21 01:40:33 PM PDT 24	25520357728 ps
T292	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2831274087	Mar 21 01:25:35 PM PDT 24	Mar 21 01:27:57 PM PDT 24	2066241003 ps
T293	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.341411302	Mar 21 01:27:27 PM PDT 24	Mar 21 01:27:45 PM PDT 24	3223539825 ps
T294	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.4221868310	Mar 21 01:26:18 PM PDT 24	Mar 21 01:46:52 PM PDT 24	64182406866 ps
T295	/workspace/coverage/default/15.sram_ctrl_bijection.3185801180	Mar 21 01:26:01 PM PDT 24	Mar 21 02:04:11 PM PDT 24	105564327576 ps
T296	/workspace/coverage/default/27.sram_ctrl_bijection.55910621	Mar 21 01:26:20 PM PDT 24	Mar 21 01:47:29 PM PDT 24	113116518799 ps
T297	/workspace/coverage/default/20.sram_ctrl_partial_access.1848722472	Mar 21 01:26:00 PM PDT 24	Mar 21 01:26:09 PM PDT 24	2447829010 ps
T298	/workspace/coverage/default/27.sram_ctrl_smoke.1917578232	Mar 21 01:26:12 PM PDT 24	Mar 21 01:26:29 PM PDT 24	1757724958 ps
T119	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3162876273	Mar 21 01:25:35 PM PDT 24	Mar 21 01:28:04 PM PDT 24	5098685396 ps
T299	/workspace/coverage/default/19.sram_ctrl_bijection.1501832471	Mar 21 01:26:12 PM PDT 24	Mar 21 01:46:43 PM PDT 24	55407059989 ps