Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	138344830	1			T1	927		T3	116991		T4	1620
triple_byte_access	2834419	1			T1	774		T3	2250		T4	1431
halfword_access	4345568	1			T1	1135		T3	3488		T4	2195
byte_access	6055240	1			T1	1490		T3	4628		T4	2838
zero_access	1810781	1			T1	383		T3	1141		T4	753

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76532327

1

T1

2364

T3

64162

T4

4394

auto[1]

76858511

1

T1

2345

T3

64336

T4

4443

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	68867619	1			T1	444		T3	58362		T4	795
auto[0]	triple_byte_access	1358415	1			T1	373		T3	1130		T4	694
auto[0]	halfword_access	2131062	1			T1	575		T3	1762		T4	1075
auto[0]	byte_access	3102296	1			T1	780		T3	2332		T4	1420
auto[0]	zero_access	1072935	1			T1	192		T3	576		T4	410
auto[1]	word_access	69477211	1			T1	483		T3	58629		T4	825
auto[1]	triple_byte_access	1476004	1			T1	401		T3	1120		T4	737
auto[1]	halfword_access	2214506	1			T1	560		T3	1726		T4	1120
auto[1]	byte_access	2952944	1			T1	710		T3	2296		T4	1418
auto[1]	zero_access	737846	1			T1	191		T3	565		T4	343