Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	339175316	1			T1	11788		T2	125142		T3	15904
instr_valid_dis	307642515	1			T1	11788		T2	125142		T3	15904
instr_en	21902823	1			T4	182778		T12	392266		T7	70570

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9694536	1			T4	53294		T12	81108		T7	65900
sram_ifetch_valid_disable	306595570	1			T1	11788		T2	125142		T3	15904
sram_ifetch_enable	22885210	1			T4	45392		T12	162920		T7	132440

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	339175316	1			T1	11788		T2	125142		T3	15904
hw_debug_en_valid_off	303797794	1			T1	11788		T2	125142		T3	15904
hw_debug_en_on	25981174	1			T4	93830		T12	189026		T7	82910

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	306595570	1			T1	11788		T2	125142		T3	15904
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	293759613	1			T1	11788		T2	125142		T3	15904
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9155429	1			T4	84092		T12	148238		T7	820
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3913408	1			T4	11064		T12	29954		T9	33222
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1490248	1			T38	54458		T142	50226		T135	10502
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1582844	1			T4	11064		T12	29954		T9	33222
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3659562	1			T4	42230		T12	51154		T7	65900
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1343346	1			T16	13928		T45	12916		T55	1954
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1607232	1			T4	42230		T12	51154		T46	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10849868	1			T4	23058		T12	85360		T46	17938
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5542598	1			T15	39278		T38	20594		T28	21218
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3738770	1			T4	23058		T12	85360		T46	17938

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8808682	1			T4	45392		T12	162920		T7	69750
lc_exec_en	11471744	1			T4	28542		T12	52512		T7	17010
valid_exec_dis	302428370	1			T1	11788		T2	125142		T3	15904
invalid_exec_dis	32579746	1			T4	98686		T12	244028		T7	198340