Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.81	97.23	100.00	100.00	98.61	99.70	98.52

Total tests in report: 1038

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
76.33	76.33	97.19	97.19	78.16	78.16	55.22	55.22	71.43	71.43	91.29	91.29	94.80	94.80	46.20	46.20	/workspace/coverage/default/38.sram_ctrl_regwen.3749092315
86.83	10.51	98.60	1.40	82.55	4.40	86.04	30.82	100.00	28.57	95.22	3.93	94.95	0.15	50.46	4.27	/workspace/coverage/default/3.sram_ctrl_stress_all.4247922890
93.49	6.66	98.97	0.37	88.74	6.18	89.03	2.98	100.00	0.00	96.07	0.84	96.29	1.34	85.34	34.88	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3097723273
95.03	1.54	98.97	0.00	89.84	1.10	98.12	9.09	100.00	0.00	96.07	0.00	96.29	0.00	85.90	0.56	/workspace/coverage/default/44.sram_ctrl_alert_test.2591053867
96.14	1.12	99.44	0.47	93.13	3.30	98.69	0.57	100.00	0.00	98.60	2.53	96.88	0.59	86.27	0.37	/workspace/coverage/default/2.sram_ctrl_sec_cm.1725028059
96.86	0.72	99.44	0.00	93.54	0.41	98.69	0.00	100.00	0.00	98.60	0.00	96.88	0.00	90.91	4.64	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1684567593
97.41	0.55	99.44	0.00	93.54	0.00	99.04	0.36	100.00	0.00	98.60	0.00	97.03	0.15	94.25	3.34	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3133316072
97.76	0.34	99.72	0.28	93.96	0.41	99.22	0.18	100.00	0.00	98.88	0.28	97.92	0.89	94.62	0.37	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3009839164
98.05	0.29	99.72	0.00	94.23	0.27	99.29	0.07	100.00	0.00	98.88	0.00	99.26	1.34	94.99	0.37	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4000341290
98.26	0.21	99.72	0.00	94.37	0.14	99.29	0.00	100.00	0.00	98.88	0.00	99.26	0.00	96.29	1.30	/workspace/coverage/default/38.sram_ctrl_stress_all.2955124727
98.37	0.11	99.81	0.09	94.37	0.00	100.00	0.71	100.00	0.00	98.88	0.00	99.26	0.00	96.29	0.00	/workspace/coverage/default/10.sram_ctrl_ram_cfg.530362941
98.48	0.11	99.81	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.26	0.00	97.03	0.74	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1680837116
98.58	0.11	99.81	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.26	0.00	97.77	0.74	/workspace/coverage/default/49.sram_ctrl_executable.2245081839
98.65	0.06	99.81	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.70	0.45	97.77	0.00	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2792256897
98.70	0.05	99.81	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.70	0.00	98.14	0.37	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2306709239
98.73	0.03	99.81	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.70	0.00	98.33	0.19	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3451155308
98.75	0.03	99.81	0.00	94.37	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.70	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2933677065

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3785791328
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3039453746
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2034562573
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2165621852
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3441638471
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1873437699
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2622895804
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.249075653
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.731635755
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1209480762
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1472423385
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2823360535
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.185042118
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1185620051
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.13287308
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2752048033
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4115844999
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2451770716
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1643900895
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3840687433
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4211657387
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3027296326
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3990141493
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2224697384
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1637514358
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1256521652
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2357770764
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3661211554
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2628288869
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.395213815
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4267587694
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1592995138
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2567214180
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1446869022
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2445121479
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.23770231
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2818328765
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2812488369
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.491856191
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1554554288
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.359431503
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.817989905
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3157022494
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2376221791
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3749008994
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2774003471
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.813120670
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1979779284
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.470561440
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3923890299
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.558669166
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1111909700
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1086491275
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1100310274
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3070578634
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2120671811
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.930782018
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.276222114
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.46402510
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1543408853
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3012113983
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2207015896
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.820899110
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.716386364
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2196297678
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1836672537
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3222807759
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3703044506
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.761881575
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1898786418
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.342439257
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1931937816
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.558247602
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.547114898
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2376209038
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3065159367
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.142488813
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.289701602
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.689279179
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.92792321
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2027876889
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.594352240
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2147393820
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3049073392
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1096557692
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.870426012
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2736384589
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3642515254
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3663955855
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1936911438
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4015337267
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3102456676
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2174753154
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.214609611
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2611809820
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3421223738
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2311316018
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1572233899
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3681547228
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1166612534
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.358147538
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2080858474
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2881415567
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.36899086
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1788327892
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4135869815
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3081597344
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1881839123
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.816459117
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.286835216
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4181792088
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1889139889
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.828629123
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2695260767
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.313560089
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2236516023
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3444545168
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2675012650
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2322173802
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.752389959
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.899419376
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2931165147
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.35615256
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2535093697
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4026189929
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4100583232
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1158957405
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1404626921
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1659745349
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2534161316
/workspace/coverage/default/0.sram_ctrl_alert_test.56847006
/workspace/coverage/default/0.sram_ctrl_bijection.1981541236
/workspace/coverage/default/0.sram_ctrl_executable.1497750705
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1867340608
/workspace/coverage/default/0.sram_ctrl_max_throughput.3399986546
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.57035272
/workspace/coverage/default/0.sram_ctrl_mem_walk.2887939509
/workspace/coverage/default/0.sram_ctrl_multiple_keys.4136168886
/workspace/coverage/default/0.sram_ctrl_partial_access.2833293700
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2701211178
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2867412607
/workspace/coverage/default/0.sram_ctrl_regwen.1816082630
/workspace/coverage/default/0.sram_ctrl_sec_cm.3973404231
/workspace/coverage/default/0.sram_ctrl_smoke.3011931011
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1753918516
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1578380166
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2746331921
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3836777505
/workspace/coverage/default/1.sram_ctrl_alert_test.3523846002
/workspace/coverage/default/1.sram_ctrl_bijection.4203953777
/workspace/coverage/default/1.sram_ctrl_executable.2861119302
/workspace/coverage/default/1.sram_ctrl_lc_escalation.314282474
/workspace/coverage/default/1.sram_ctrl_max_throughput.1623979798
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3711578223
/workspace/coverage/default/1.sram_ctrl_mem_walk.1218003475
/workspace/coverage/default/1.sram_ctrl_multiple_keys.78956594
/workspace/coverage/default/1.sram_ctrl_partial_access.763104762
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1775540678
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2644849957
/workspace/coverage/default/1.sram_ctrl_regwen.2723579331
/workspace/coverage/default/1.sram_ctrl_sec_cm.832717786
/workspace/coverage/default/1.sram_ctrl_smoke.2200808324
/workspace/coverage/default/1.sram_ctrl_stress_all.4279064645
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3170039654
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2208971329
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.419767238
/workspace/coverage/default/10.sram_ctrl_alert_test.337743598
/workspace/coverage/default/10.sram_ctrl_bijection.4016963323
/workspace/coverage/default/10.sram_ctrl_executable.11963330
/workspace/coverage/default/10.sram_ctrl_lc_escalation.555352854
/workspace/coverage/default/10.sram_ctrl_max_throughput.2970753014
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3510045739
/workspace/coverage/default/10.sram_ctrl_mem_walk.538486024
/workspace/coverage/default/10.sram_ctrl_multiple_keys.186595088
/workspace/coverage/default/10.sram_ctrl_partial_access.3468279011
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.132041396
/workspace/coverage/default/10.sram_ctrl_regwen.3817695010
/workspace/coverage/default/10.sram_ctrl_smoke.429438851
/workspace/coverage/default/10.sram_ctrl_stress_all.156684070
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1859998856
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3792843367
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1741721727
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.159153254
/workspace/coverage/default/11.sram_ctrl_alert_test.3569352530
/workspace/coverage/default/11.sram_ctrl_bijection.107135395
/workspace/coverage/default/11.sram_ctrl_executable.1025644526
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3369891761
/workspace/coverage/default/11.sram_ctrl_max_throughput.932544310
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.247048549
/workspace/coverage/default/11.sram_ctrl_mem_walk.582699734
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3186056131
/workspace/coverage/default/11.sram_ctrl_partial_access.2872693947
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2333003947
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2083651160
/workspace/coverage/default/11.sram_ctrl_regwen.657200886
/workspace/coverage/default/11.sram_ctrl_smoke.3543063025
/workspace/coverage/default/11.sram_ctrl_stress_all.629697308
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1991534010
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2208495246
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3913837133
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2969161753
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/workspace/coverage/default/42.sram_ctrl_max_throughput.1836910013
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3333613057
/workspace/coverage/default/42.sram_ctrl_mem_walk.1652458673
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1575345662
/workspace/coverage/default/42.sram_ctrl_partial_access.3384114132
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3560232978
/workspace/coverage/default/42.sram_ctrl_regwen.2707461930
/workspace/coverage/default/42.sram_ctrl_smoke.1314965267
/workspace/coverage/default/42.sram_ctrl_stress_all.3912273181
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.427293929
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3411247921
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4214778982
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3665655710
/workspace/coverage/default/43.sram_ctrl_alert_test.420240289
/workspace/coverage/default/43.sram_ctrl_bijection.2876724342
/workspace/coverage/default/43.sram_ctrl_executable.3109386317
/workspace/coverage/default/43.sram_ctrl_lc_escalation.4241649937
/workspace/coverage/default/43.sram_ctrl_max_throughput.535767400
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3293724169
/workspace/coverage/default/43.sram_ctrl_mem_walk.1524754169
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1649032425
/workspace/coverage/default/43.sram_ctrl_partial_access.3696058141
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2338801997
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2950805289
/workspace/coverage/default/43.sram_ctrl_regwen.3583217205
/workspace/coverage/default/43.sram_ctrl_smoke.3457112738
/workspace/coverage/default/43.sram_ctrl_stress_all.3060424811
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3473651367
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2591683371
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2711715372
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3451707013
/workspace/coverage/default/44.sram_ctrl_bijection.1023085509
/workspace/coverage/default/44.sram_ctrl_executable.279799898
/workspace/coverage/default/44.sram_ctrl_lc_escalation.4097870617
/workspace/coverage/default/44.sram_ctrl_max_throughput.1303594423
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.4190108747
/workspace/coverage/default/44.sram_ctrl_mem_walk.2750231568
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1293761164
/workspace/coverage/default/44.sram_ctrl_partial_access.3568862618
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3087238532
/workspace/coverage/default/44.sram_ctrl_ram_cfg.577190200
/workspace/coverage/default/44.sram_ctrl_regwen.1363168399
/workspace/coverage/default/44.sram_ctrl_smoke.531001544
/workspace/coverage/default/44.sram_ctrl_stress_all.99815014
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.559958716
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.443293228
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.754379646
/workspace/coverage/default/45.sram_ctrl_alert_test.1575198200
/workspace/coverage/default/45.sram_ctrl_bijection.3347614934
/workspace/coverage/default/45.sram_ctrl_executable.2142777981
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1424204554
/workspace/coverage/default/45.sram_ctrl_max_throughput.977786653
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1704376812
/workspace/coverage/default/45.sram_ctrl_mem_walk.3689029025
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1829990692
/workspace/coverage/default/45.sram_ctrl_partial_access.1422036760
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3573620236
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1737996224
/workspace/coverage/default/45.sram_ctrl_regwen.3937154941
/workspace/coverage/default/45.sram_ctrl_smoke.1074400360
/workspace/coverage/default/45.sram_ctrl_stress_all.2125551199
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.444692930
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.772405971
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3271818523
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3196110807
/workspace/coverage/default/46.sram_ctrl_alert_test.2448671326
/workspace/coverage/default/46.sram_ctrl_bijection.3863970440
/workspace/coverage/default/46.sram_ctrl_executable.216792585
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1098916504
/workspace/coverage/default/46.sram_ctrl_max_throughput.303208354
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.504699308
/workspace/coverage/default/46.sram_ctrl_mem_walk.3673903073
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1013889786
/workspace/coverage/default/46.sram_ctrl_partial_access.2119618270
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.210402344
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3465414116
/workspace/coverage/default/46.sram_ctrl_regwen.3673789243
/workspace/coverage/default/46.sram_ctrl_smoke.1896100912
/workspace/coverage/default/46.sram_ctrl_stress_all.1885987242
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3301161513
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.4132558105
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1215205372
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3206070704
/workspace/coverage/default/47.sram_ctrl_alert_test.2142988382
/workspace/coverage/default/47.sram_ctrl_bijection.1931587727
/workspace/coverage/default/47.sram_ctrl_executable.1434994154
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2642121719
/workspace/coverage/default/47.sram_ctrl_max_throughput.60094508
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3112083331
/workspace/coverage/default/47.sram_ctrl_mem_walk.3740836499
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4279524766
/workspace/coverage/default/47.sram_ctrl_partial_access.1235488162
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3468118757
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3237147057
/workspace/coverage/default/47.sram_ctrl_regwen.998483254
/workspace/coverage/default/47.sram_ctrl_smoke.1816334020
/workspace/coverage/default/47.sram_ctrl_stress_all.2530760189
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3810362949
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3133859955
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3030460668
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.178239477
/workspace/coverage/default/48.sram_ctrl_alert_test.1990742104
/workspace/coverage/default/48.sram_ctrl_bijection.166821277
/workspace/coverage/default/48.sram_ctrl_executable.1566122497
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2870313017
/workspace/coverage/default/48.sram_ctrl_max_throughput.3725331165
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2133200822
/workspace/coverage/default/48.sram_ctrl_mem_walk.1130619074
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3213836879
/workspace/coverage/default/48.sram_ctrl_partial_access.4276153979
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2008502226
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1982642838
/workspace/coverage/default/48.sram_ctrl_regwen.2727666982
/workspace/coverage/default/48.sram_ctrl_smoke.4106498837
/workspace/coverage/default/48.sram_ctrl_stress_all.3664854599
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2354393793
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3022375267
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2551398102
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3463640677
/workspace/coverage/default/49.sram_ctrl_alert_test.2688039278
/workspace/coverage/default/49.sram_ctrl_bijection.3282575811
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1142612233
/workspace/coverage/default/49.sram_ctrl_max_throughput.2402473009
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4270778551
/workspace/coverage/default/49.sram_ctrl_mem_walk.636686606
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2488611044
/workspace/coverage/default/49.sram_ctrl_partial_access.2949281342
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2466505074
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2707486329
/workspace/coverage/default/49.sram_ctrl_regwen.647045679
/workspace/coverage/default/49.sram_ctrl_smoke.821314415
/workspace/coverage/default/49.sram_ctrl_stress_all.3736636528
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3716067054
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.4066426680
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3787835666
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1333332816
/workspace/coverage/default/5.sram_ctrl_alert_test.286946324
/workspace/coverage/default/5.sram_ctrl_bijection.1688845354
/workspace/coverage/default/5.sram_ctrl_executable.3148027264
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3693129301
/workspace/coverage/default/5.sram_ctrl_max_throughput.2721428114
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3441227957
/workspace/coverage/default/5.sram_ctrl_mem_walk.1064705817
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2826923766
/workspace/coverage/default/5.sram_ctrl_partial_access.770770675
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1516351496
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3232459214
/workspace/coverage/default/5.sram_ctrl_regwen.1093569477
/workspace/coverage/default/5.sram_ctrl_smoke.1312043750
/workspace/coverage/default/5.sram_ctrl_stress_all.2146408273
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2718795277
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3462643604
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3019686404
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1319945037
/workspace/coverage/default/6.sram_ctrl_alert_test.649848602
/workspace/coverage/default/6.sram_ctrl_bijection.4119466393
/workspace/coverage/default/6.sram_ctrl_executable.2564733567
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1557003378
/workspace/coverage/default/6.sram_ctrl_max_throughput.2568242323
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.776619960
/workspace/coverage/default/6.sram_ctrl_mem_walk.773003736
/workspace/coverage/default/6.sram_ctrl_multiple_keys.312855212
/workspace/coverage/default/6.sram_ctrl_partial_access.1161326402
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3385430933
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2280610874
/workspace/coverage/default/6.sram_ctrl_regwen.649603579
/workspace/coverage/default/6.sram_ctrl_smoke.255741106
/workspace/coverage/default/6.sram_ctrl_stress_all.2624580430
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.346124043
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2541350293
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1162538609
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4019462463
/workspace/coverage/default/7.sram_ctrl_alert_test.1581184392
/workspace/coverage/default/7.sram_ctrl_bijection.2850906138
/workspace/coverage/default/7.sram_ctrl_executable.2101596056
/workspace/coverage/default/7.sram_ctrl_lc_escalation.361596504
/workspace/coverage/default/7.sram_ctrl_max_throughput.2327550184
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.268212763
/workspace/coverage/default/7.sram_ctrl_mem_walk.2601865459
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2169005450
/workspace/coverage/default/7.sram_ctrl_partial_access.1369188977
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4260493383
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1268090309
/workspace/coverage/default/7.sram_ctrl_regwen.4103757300
/workspace/coverage/default/7.sram_ctrl_smoke.1614958585
/workspace/coverage/default/7.sram_ctrl_stress_all.934279548
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.169009111
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2352202307
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2216501384
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3585699807
/workspace/coverage/default/8.sram_ctrl_alert_test.1717909386
/workspace/coverage/default/8.sram_ctrl_bijection.3611831101
/workspace/coverage/default/8.sram_ctrl_executable.1169239797
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1455894719
/workspace/coverage/default/8.sram_ctrl_max_throughput.2952966445
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1163128876
/workspace/coverage/default/8.sram_ctrl_mem_walk.4212937204
/workspace/coverage/default/8.sram_ctrl_multiple_keys.373627187
/workspace/coverage/default/8.sram_ctrl_partial_access.1683619112
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2863218211
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2294781092
/workspace/coverage/default/8.sram_ctrl_regwen.1942893566
/workspace/coverage/default/8.sram_ctrl_smoke.3804671541
/workspace/coverage/default/8.sram_ctrl_stress_all.4160362805
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3031863198
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2376977192
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2907544539
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3915753684
/workspace/coverage/default/9.sram_ctrl_alert_test.2685391397
/workspace/coverage/default/9.sram_ctrl_bijection.4110758742
/workspace/coverage/default/9.sram_ctrl_executable.1280195400
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3598623987
/workspace/coverage/default/9.sram_ctrl_max_throughput.3106517821
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1464632880
/workspace/coverage/default/9.sram_ctrl_mem_walk.1115640075
/workspace/coverage/default/9.sram_ctrl_multiple_keys.376185125
/workspace/coverage/default/9.sram_ctrl_partial_access.1558250170
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2098993474
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2195189396
/workspace/coverage/default/9.sram_ctrl_regwen.3983269049
/workspace/coverage/default/9.sram_ctrl_smoke.4202596381
/workspace/coverage/default/9.sram_ctrl_stress_all.3529051291
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.451714271
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4016281432
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2153006872

Total test records in report: 1038

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3476059475	Mar 24 01:44:31 PM PDT 24	Mar 24 01:45:15 PM PDT 24	738990116 ps
T2	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.309936892	Mar 24 01:46:21 PM PDT 24	Mar 24 01:48:24 PM PDT 24	1658041464 ps
T3	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3724092009	Mar 24 01:40:17 PM PDT 24	Mar 24 01:41:50 PM PDT 24	787463998 ps
T10	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.592163912	Mar 24 01:39:28 PM PDT 24	Mar 24 01:44:23 PM PDT 24	6060954709 ps
T4	/workspace/coverage/default/38.sram_ctrl_regwen.3749092315	Mar 24 01:46:17 PM PDT 24	Mar 24 01:53:08 PM PDT 24	42932382171 ps
T11	/workspace/coverage/default/43.sram_ctrl_ram_cfg.2950805289	Mar 24 01:47:40 PM PDT 24	Mar 24 01:47:44 PM PDT 24	2247379312 ps
T12	/workspace/coverage/default/2.sram_ctrl_regwen.2797552099	Mar 24 01:35:23 PM PDT 24	Mar 24 01:52:27 PM PDT 24	6890383523 ps
T13	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.709551402	Mar 24 01:44:16 PM PDT 24	Mar 24 02:11:52 PM PDT 24	16273391086 ps
T5	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.238250664	Mar 24 01:35:59 PM PDT 24	Mar 24 01:37:19 PM PDT 24	4900117954 ps
T14	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2879835029	Mar 24 01:41:25 PM PDT 24	Mar 24 01:42:27 PM PDT 24	1904784116 ps
T6	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3009839164	Mar 24 01:39:27 PM PDT 24	Mar 24 02:01:28 PM PDT 24	43853356823 ps
T7	/workspace/coverage/default/3.sram_ctrl_stress_all.4247922890	Mar 24 01:35:38 PM PDT 24	Mar 24 02:54:01 PM PDT 24	405253251435 ps
T19	/workspace/coverage/default/44.sram_ctrl_alert_test.2591053867	Mar 24 01:48:04 PM PDT 24	Mar 24 01:48:05 PM PDT 24	15455032 ps
T64	/workspace/coverage/default/24.sram_ctrl_mem_walk.183633760	Mar 24 01:42:13 PM PDT 24	Mar 24 01:46:17 PM PDT 24	3947598825 ps
T46	/workspace/coverage/default/16.sram_ctrl_executable.299941704	Mar 24 01:39:46 PM PDT 24	Mar 24 01:44:02 PM PDT 24	10477130067 ps
T17	/workspace/coverage/default/29.sram_ctrl_max_throughput.2599026895	Mar 24 01:43:33 PM PDT 24	Mar 24 01:43:53 PM PDT 24	1373057732 ps
T15	/workspace/coverage/default/10.sram_ctrl_regwen.3817695010	Mar 24 01:37:59 PM PDT 24	Mar 24 01:42:30 PM PDT 24	17480937364 ps
T26	/workspace/coverage/default/37.sram_ctrl_bijection.1132799050	Mar 24 01:45:48 PM PDT 24	Mar 24 02:15:16 PM PDT 24	26576054849 ps
T157	/workspace/coverage/default/21.sram_ctrl_max_throughput.2045062131	Mar 24 01:41:28 PM PDT 24	Mar 24 01:42:43 PM PDT 24	1609869184 ps
T16	/workspace/coverage/default/28.sram_ctrl_executable.2079312513	Mar 24 01:43:23 PM PDT 24	Mar 24 01:45:47 PM PDT 24	6771377992 ps
T158	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1197580783	Mar 24 01:41:27 PM PDT 24	Mar 24 01:42:32 PM PDT 24	5329467437 ps
T8	/workspace/coverage/default/36.sram_ctrl_stress_all.1176109861	Mar 24 01:45:49 PM PDT 24	Mar 24 02:53:19 PM PDT 24	156070048935 ps
T95	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3784588647	Mar 24 01:39:27 PM PDT 24	Mar 24 01:43:30 PM PDT 24	3818001316 ps
T75	/workspace/coverage/default/49.sram_ctrl_smoke.821314415	Mar 24 01:49:24 PM PDT 24	Mar 24 01:49:39 PM PDT 24	1094760145 ps
T153	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.635438977	Mar 24 01:42:53 PM PDT 24	Mar 24 01:43:17 PM PDT 24	744842012 ps
T159	/workspace/coverage/default/39.sram_ctrl_smoke.280656279	Mar 24 01:46:22 PM PDT 24	Mar 24 01:46:58 PM PDT 24	1032902227 ps
T30	/workspace/coverage/default/23.sram_ctrl_stress_all.1649687026	Mar 24 01:41:59 PM PDT 24	Mar 24 02:43:29 PM PDT 24	51643585906 ps
T143	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2894595208	Mar 24 01:46:58 PM PDT 24	Mar 24 01:47:27 PM PDT 24	961481452 ps
T156	/workspace/coverage/default/20.sram_ctrl_partial_access.3257011317	Mar 24 01:40:47 PM PDT 24	Mar 24 01:41:07 PM PDT 24	2751232829 ps
T9	/workspace/coverage/default/44.sram_ctrl_stress_all.99815014	Mar 24 01:48:04 PM PDT 24	Mar 24 02:59:45 PM PDT 24	43755535485 ps
T155	/workspace/coverage/default/28.sram_ctrl_smoke.1795496539	Mar 24 01:43:14 PM PDT 24	Mar 24 01:43:32 PM PDT 24	587090501 ps
T105	/workspace/coverage/default/0.sram_ctrl_bijection.1981541236	Mar 24 01:34:35 PM PDT 24	Mar 24 02:07:49 PM PDT 24	87239795953 ps
T96	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.525475168	Mar 24 01:41:31 PM PDT 24	Mar 24 01:45:50 PM PDT 24	14529549474 ps
T63	/workspace/coverage/default/33.sram_ctrl_regwen.2868568386	Mar 24 01:44:55 PM PDT 24	Mar 24 02:03:02 PM PDT 24	167810332200 ps
T148	/workspace/coverage/default/3.sram_ctrl_bijection.1500809069	Mar 24 01:35:27 PM PDT 24	Mar 24 01:54:19 PM PDT 24	69192036581 ps
T146	/workspace/coverage/default/42.sram_ctrl_multiple_keys.1575345662	Mar 24 01:47:13 PM PDT 24	Mar 24 01:58:24 PM PDT 24	4632341090 ps
T149	/workspace/coverage/default/30.sram_ctrl_multiple_keys.4205668233	Mar 24 01:43:43 PM PDT 24	Mar 24 02:04:37 PM PDT 24	39389793128 ps
T150	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4243067839	Mar 24 01:38:38 PM PDT 24	Mar 24 01:38:46 PM PDT 24	4525714352 ps
T160	/workspace/coverage/default/30.sram_ctrl_mem_walk.3403058795	Mar 24 01:43:54 PM PDT 24	Mar 24 01:49:01 PM PDT 24	82640279177 ps
T101	/workspace/coverage/default/13.sram_ctrl_smoke.3151717535	Mar 24 01:38:57 PM PDT 24	Mar 24 01:39:22 PM PDT 24	3613210350 ps
T23	/workspace/coverage/default/2.sram_ctrl_sec_cm.1725028059	Mar 24 01:35:24 PM PDT 24	Mar 24 01:35:26 PM PDT 24	151364259 ps
T38	/workspace/coverage/default/49.sram_ctrl_executable.2245081839	Mar 24 01:49:34 PM PDT 24	Mar 24 02:05:59 PM PDT 24	40723986505 ps
T39	/workspace/coverage/default/1.sram_ctrl_multiple_keys.78956594	Mar 24 01:34:48 PM PDT 24	Mar 24 01:44:30 PM PDT 24	16321437170 ps
T27	/workspace/coverage/default/12.sram_ctrl_lc_escalation.2386624079	Mar 24 01:38:37 PM PDT 24	Mar 24 01:40:18 PM PDT 24	60383092790 ps
T40	/workspace/coverage/default/31.sram_ctrl_stress_all.2225781965	Mar 24 01:44:20 PM PDT 24	Mar 24 03:04:41 PM PDT 24	739893135019 ps
T41	/workspace/coverage/default/21.sram_ctrl_partial_access.3128929795	Mar 24 01:41:28 PM PDT 24	Mar 24 01:41:58 PM PDT 24	9295212359 ps
T42	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3663571477	Mar 24 01:45:13 PM PDT 24	Mar 24 01:46:59 PM PDT 24	4594158273 ps
T43	/workspace/coverage/default/7.sram_ctrl_executable.2101596056	Mar 24 01:36:47 PM PDT 24	Mar 24 01:38:25 PM PDT 24	5662557060 ps
T44	/workspace/coverage/default/37.sram_ctrl_mem_walk.2026214769	Mar 24 01:45:59 PM PDT 24	Mar 24 01:50:04 PM PDT 24	4111553858 ps
T45	/workspace/coverage/default/17.sram_ctrl_executable.1585044239	Mar 24 01:40:05 PM PDT 24	Mar 24 01:46:19 PM PDT 24	28022062180 ps
T34	/workspace/coverage/default/4.sram_ctrl_ram_cfg.1077403323	Mar 24 01:35:58 PM PDT 24	Mar 24 01:36:02 PM PDT 24	364258271 ps
T161	/workspace/coverage/default/33.sram_ctrl_bijection.1871224764	Mar 24 01:44:44 PM PDT 24	Mar 24 02:16:37 PM PDT 24	345630639498 ps
T147	/workspace/coverage/default/9.sram_ctrl_partial_access.1558250170	Mar 24 01:37:23 PM PDT 24	Mar 24 01:37:54 PM PDT 24	12659220283 ps
T28	/workspace/coverage/default/22.sram_ctrl_stress_all.2681259736	Mar 24 01:41:37 PM PDT 24	Mar 24 02:52:19 PM PDT 24	52921998112 ps
T151	/workspace/coverage/default/25.sram_ctrl_max_throughput.3390149344	Mar 24 01:42:18 PM PDT 24	Mar 24 01:44:20 PM PDT 24	774025877 ps
T20	/workspace/coverage/default/19.sram_ctrl_alert_test.3432650651	Mar 24 01:40:44 PM PDT 24	Mar 24 01:40:45 PM PDT 24	40795843 ps
T162	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2216501384	Mar 24 01:36:48 PM PDT 24	Mar 24 01:37:27 PM PDT 24	833186956 ps
T144	/workspace/coverage/default/17.sram_ctrl_bijection.687772018	Mar 24 01:39:59 PM PDT 24	Mar 24 02:04:17 PM PDT 24	197502355099 ps
T163	/workspace/coverage/default/41.sram_ctrl_smoke.2253213566	Mar 24 01:46:49 PM PDT 24	Mar 24 01:48:24 PM PDT 24	1593494053 ps
T142	/workspace/coverage/default/24.sram_ctrl_executable.3297591958	Mar 24 01:42:07 PM PDT 24	Mar 24 02:03:59 PM PDT 24	10800623924 ps
T164	/workspace/coverage/default/11.sram_ctrl_multiple_keys.3186056131	Mar 24 01:38:12 PM PDT 24	Mar 24 01:39:14 PM PDT 24	1534366386 ps
T165	/workspace/coverage/default/26.sram_ctrl_max_throughput.864672408	Mar 24 01:42:37 PM PDT 24	Mar 24 01:43:37 PM PDT 24	4290378020 ps
T166	/workspace/coverage/default/27.sram_ctrl_smoke.2845765357	Mar 24 01:42:53 PM PDT 24	Mar 24 01:43:05 PM PDT 24	6300319901 ps
T35	/workspace/coverage/default/28.sram_ctrl_ram_cfg.110253264	Mar 24 01:43:22 PM PDT 24	Mar 24 01:43:25 PM PDT 24	359711190 ps
T167	/workspace/coverage/default/48.sram_ctrl_multiple_keys.3213836879	Mar 24 01:49:12 PM PDT 24	Mar 24 01:53:48 PM PDT 24	12218978090 ps
T18	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3365238920	Mar 24 01:39:25 PM PDT 24	Mar 24 01:52:01 PM PDT 24	23929915074 ps
T152	/workspace/coverage/default/16.sram_ctrl_bijection.611306885	Mar 24 01:39:40 PM PDT 24	Mar 24 02:00:02 PM PDT 24	80049279762 ps
T97	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3133316072	Mar 24 01:47:20 PM PDT 24	Mar 24 01:52:10 PM PDT 24	45469851697 ps
T168	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1215205372	Mar 24 01:48:37 PM PDT 24	Mar 24 01:49:26 PM PDT 24	797155850 ps
T169	/workspace/coverage/default/42.sram_ctrl_mem_walk.1652458673	Mar 24 01:47:30 PM PDT 24	Mar 24 01:51:59 PM PDT 24	57406577001 ps
T145	/workspace/coverage/default/2.sram_ctrl_lc_escalation.1114135568	Mar 24 01:35:11 PM PDT 24	Mar 24 01:35:51 PM PDT 24	14999776462 ps
T29	/workspace/coverage/default/0.sram_ctrl_lc_escalation.1867340608	Mar 24 01:34:38 PM PDT 24	Mar 24 01:35:45 PM PDT 24	12940724002 ps
T170	/workspace/coverage/default/28.sram_ctrl_max_throughput.3263405085	Mar 24 01:43:18 PM PDT 24	Mar 24 01:45:22 PM PDT 24	1512637599 ps
T31	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3097723273	Mar 24 01:48:05 PM PDT 24	Mar 24 01:48:40 PM PDT 24	4671556072 ps
T54	/workspace/coverage/default/32.sram_ctrl_lc_escalation.3650941221	Mar 24 01:44:30 PM PDT 24	Mar 24 01:45:18 PM PDT 24	7939245164 ps
T55	/workspace/coverage/default/47.sram_ctrl_executable.1434994154	Mar 24 01:48:59 PM PDT 24	Mar 24 02:05:48 PM PDT 24	18682029192 ps
T56	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.4066426680	Mar 24 01:49:29 PM PDT 24	Mar 24 01:53:32 PM PDT 24	21893778733 ps
T57	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1736642060	Mar 24 01:42:07 PM PDT 24	Mar 24 01:42:49 PM PDT 24	3049588356 ps
T58	/workspace/coverage/default/25.sram_ctrl_ram_cfg.3217499323	Mar 24 01:42:29 PM PDT 24	Mar 24 01:42:33 PM PDT 24	1770351953 ps
T59	/workspace/coverage/default/4.sram_ctrl_lc_escalation.1340146838	Mar 24 01:35:48 PM PDT 24	Mar 24 01:36:40 PM PDT 24	27449271734 ps
T60	/workspace/coverage/default/27.sram_ctrl_executable.1275909024	Mar 24 01:43:06 PM PDT 24	Mar 24 01:49:57 PM PDT 24	2916862321 ps
T61	/workspace/coverage/default/23.sram_ctrl_mem_walk.3770231796	Mar 24 01:41:58 PM PDT 24	Mar 24 01:46:29 PM PDT 24	49233638603 ps
T62	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3510045739	Mar 24 01:37:59 PM PDT 24	Mar 24 01:39:13 PM PDT 24	2754823258 ps
T171	/workspace/coverage/default/41.sram_ctrl_multiple_keys.2576501967	Mar 24 01:46:55 PM PDT 24	Mar 24 01:49:08 PM PDT 24	2096942817 ps
T120	/workspace/coverage/default/42.sram_ctrl_stress_all.3912273181	Mar 24 01:47:34 PM PDT 24	Mar 24 02:14:52 PM PDT 24	17073327277 ps
T172	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2551398102	Mar 24 01:49:13 PM PDT 24	Mar 24 01:49:37 PM PDT 24	725964189 ps
T32	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3065114566	Mar 24 01:44:59 PM PDT 24	Mar 24 01:45:21 PM PDT 24	1846862908 ps
T173	/workspace/coverage/default/6.sram_ctrl_regwen.649603579	Mar 24 01:36:29 PM PDT 24	Mar 24 01:37:53 PM PDT 24	755442668 ps
T119	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1135815720	Mar 24 01:42:36 PM PDT 24	Mar 24 01:42:53 PM PDT 24	16091189297 ps
T81	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1725878958	Mar 24 01:40:28 PM PDT 24	Mar 24 01:43:04 PM PDT 24	4439636116 ps
T174	/workspace/coverage/default/49.sram_ctrl_ram_cfg.2707486329	Mar 24 01:49:33 PM PDT 24	Mar 24 01:49:36 PM PDT 24	676853863 ps
T135	/workspace/coverage/default/13.sram_ctrl_regwen.465528954	Mar 24 01:39:10 PM PDT 24	Mar 24 01:59:39 PM PDT 24	5463802736 ps
T175	/workspace/coverage/default/20.sram_ctrl_lc_escalation.3018870692	Mar 24 01:40:54 PM PDT 24	Mar 24 01:42:01 PM PDT 24	12860023364 ps
T176	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2879187124	Mar 24 01:40:53 PM PDT 24	Mar 24 01:41:45 PM PDT 24	1460597317 ps
T82	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.754379646	Mar 24 01:48:17 PM PDT 24	Mar 24 02:04:33 PM PDT 24	156639509119 ps
T177	/workspace/coverage/default/2.sram_ctrl_partial_access.3799357032	Mar 24 01:35:07 PM PDT 24	Mar 24 01:35:29 PM PDT 24	1149021990 ps
T178	/workspace/coverage/default/1.sram_ctrl_max_throughput.1623979798	Mar 24 01:34:53 PM PDT 24	Mar 24 01:36:35 PM PDT 24	784604893 ps
T24	/workspace/coverage/default/3.sram_ctrl_sec_cm.227137765	Mar 24 01:35:39 PM PDT 24	Mar 24 01:35:41 PM PDT 24	123139883 ps
T25	/workspace/coverage/default/4.sram_ctrl_sec_cm.3799189401	Mar 24 01:36:06 PM PDT 24	Mar 24 01:36:08 PM PDT 24	119071905 ps
T179	/workspace/coverage/default/33.sram_ctrl_mem_walk.2089137869	Mar 24 01:44:55 PM PDT 24	Mar 24 01:47:02 PM PDT 24	4209142096 ps
T180	/workspace/coverage/default/44.sram_ctrl_ram_cfg.577190200	Mar 24 01:48:06 PM PDT 24	Mar 24 01:48:09 PM PDT 24	354697242 ps
T83	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3775297867	Mar 24 01:39:21 PM PDT 24	Mar 24 01:42:16 PM PDT 24	18163125240 ps
T181	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3257366601	Mar 24 01:43:16 PM PDT 24	Mar 24 01:44:51 PM PDT 24	779240521 ps
T182	/workspace/coverage/default/49.sram_ctrl_bijection.3282575811	Mar 24 01:49:25 PM PDT 24	Mar 24 02:19:55 PM PDT 24	307243645696 ps
T183	/workspace/coverage/default/30.sram_ctrl_regwen.3286175536	Mar 24 01:43:56 PM PDT 24	Mar 24 01:58:16 PM PDT 24	4439780583 ps
T184	/workspace/coverage/default/34.sram_ctrl_partial_access.104034187	Mar 24 01:44:59 PM PDT 24	Mar 24 01:45:08 PM PDT 24	1407937999 ps
T136	/workspace/coverage/default/8.sram_ctrl_regwen.1942893566	Mar 24 01:37:14 PM PDT 24	Mar 24 01:40:57 PM PDT 24	750758241 ps
T185	/workspace/coverage/default/6.sram_ctrl_smoke.255741106	Mar 24 01:36:26 PM PDT 24	Mar 24 01:36:40 PM PDT 24	1247433914 ps
T186	/workspace/coverage/default/26.sram_ctrl_mem_walk.2186345282	Mar 24 01:42:42 PM PDT 24	Mar 24 01:44:45 PM PDT 24	2059824488 ps
T187	/workspace/coverage/default/19.sram_ctrl_partial_access.2264963263	Mar 24 01:40:35 PM PDT 24	Mar 24 01:42:50 PM PDT 24	5681899078 ps
T188	/workspace/coverage/default/48.sram_ctrl_stress_all.3664854599	Mar 24 01:49:25 PM PDT 24	Mar 24 02:13:09 PM PDT 24	51789164879 ps
T189	/workspace/coverage/default/9.sram_ctrl_multiple_keys.376185125	Mar 24 01:37:17 PM PDT 24	Mar 24 01:56:15 PM PDT 24	238357521429 ps
T190	/workspace/coverage/default/20.sram_ctrl_ram_cfg.2533487311	Mar 24 01:41:27 PM PDT 24	Mar 24 01:41:30 PM PDT 24	1692009640 ps
T191	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2711715372	Mar 24 01:47:35 PM PDT 24	Mar 24 01:48:13 PM PDT 24	2693229848 ps
T192	/workspace/coverage/default/47.sram_ctrl_stress_all.2530760189	Mar 24 01:49:04 PM PDT 24	Mar 24 03:31:26 PM PDT 24	63734628533 ps
T137	/workspace/coverage/default/46.sram_ctrl_regwen.3673789243	Mar 24 01:48:41 PM PDT 24	Mar 24 01:54:14 PM PDT 24	26077716235 ps
T193	/workspace/coverage/default/48.sram_ctrl_partial_access.4276153979	Mar 24 01:49:09 PM PDT 24	Mar 24 01:50:58 PM PDT 24	2447071874 ps
T89	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.4190108747	Mar 24 01:48:04 PM PDT 24	Mar 24 01:50:39 PM PDT 24	62088754630 ps
T194	/workspace/coverage/default/29.sram_ctrl_regwen.3242261032	Mar 24 01:43:37 PM PDT 24	Mar 24 02:03:39 PM PDT 24	48401154722 ps
T90	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.448181255	Mar 24 01:46:36 PM PDT 24	Mar 24 01:48:50 PM PDT 24	1635149366 ps
T195	/workspace/coverage/default/40.sram_ctrl_regwen.2459477383	Mar 24 01:46:50 PM PDT 24	Mar 24 02:09:08 PM PDT 24	15854123783 ps
T22	/workspace/coverage/default/24.sram_ctrl_alert_test.128303439	Mar 24 01:42:18 PM PDT 24	Mar 24 01:42:19 PM PDT 24	12195847 ps
T98	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.4275948419	Mar 24 01:42:33 PM PDT 24	Mar 24 01:45:04 PM PDT 24	8500108776 ps
T196	/workspace/coverage/default/13.sram_ctrl_multiple_keys.991954786	Mar 24 01:39:02 PM PDT 24	Mar 24 01:45:18 PM PDT 24	4350100150 ps
T197	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3856258366	Mar 24 01:39:03 PM PDT 24	Mar 24 01:44:49 PM PDT 24	26251786349 ps
T198	/workspace/coverage/default/43.sram_ctrl_executable.3109386317	Mar 24 01:47:35 PM PDT 24	Mar 24 02:01:59 PM PDT 24	25378886811 ps
T199	/workspace/coverage/default/46.sram_ctrl_executable.216792585	Mar 24 01:48:41 PM PDT 24	Mar 24 01:50:03 PM PDT 24	5631382208 ps
T200	/workspace/coverage/default/37.sram_ctrl_multiple_keys.2251849666	Mar 24 01:45:45 PM PDT 24	Mar 24 01:54:47 PM PDT 24	4253653670 ps
T99	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2591683371	Mar 24 01:47:36 PM PDT 24	Mar 24 01:51:06 PM PDT 24	3886429932 ps
T201	/workspace/coverage/default/41.sram_ctrl_bijection.3249268886	Mar 24 01:46:55 PM PDT 24	Mar 24 02:23:07 PM PDT 24	36141848663 ps
T202	/workspace/coverage/default/14.sram_ctrl_multiple_keys.2556093790	Mar 24 01:39:15 PM PDT 24	Mar 24 02:04:40 PM PDT 24	57371524727 ps
T203	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1881052054	Mar 24 01:46:54 PM PDT 24	Mar 24 01:50:07 PM PDT 24	6631352672 ps
T204	/workspace/coverage/default/34.sram_ctrl_smoke.2967148266	Mar 24 01:44:59 PM PDT 24	Mar 24 01:46:55 PM PDT 24	2718978111 ps
T205	/workspace/coverage/default/20.sram_ctrl_regwen.3073800862	Mar 24 01:41:26 PM PDT 24	Mar 24 01:46:18 PM PDT 24	7392405277 ps
T206	/workspace/coverage/default/15.sram_ctrl_partial_access.1147098039	Mar 24 01:39:27 PM PDT 24	Mar 24 01:40:37 PM PDT 24	1458608860 ps
T207	/workspace/coverage/default/29.sram_ctrl_smoke.2811538074	Mar 24 01:43:27 PM PDT 24	Mar 24 01:43:41 PM PDT 24	1957973690 ps
T208	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3206070704	Mar 24 01:48:59 PM PDT 24	Mar 24 02:01:04 PM PDT 24	39441383197 ps
T209	/workspace/coverage/default/45.sram_ctrl_mem_walk.3689029025	Mar 24 01:48:17 PM PDT 24	Mar 24 01:52:20 PM PDT 24	4070179518 ps
T210	/workspace/coverage/default/45.sram_ctrl_partial_access.1422036760	Mar 24 01:48:10 PM PDT 24	Mar 24 01:48:30 PM PDT 24	1200848518 ps
T211	/workspace/coverage/default/0.sram_ctrl_executable.1497750705	Mar 24 01:34:39 PM PDT 24	Mar 24 01:59:49 PM PDT 24	39436156233 ps
T212	/workspace/coverage/default/38.sram_ctrl_stress_all.2955124727	Mar 24 01:46:21 PM PDT 24	Mar 24 03:24:14 PM PDT 24	177707211087 ps
T213	/workspace/coverage/default/1.sram_ctrl_regwen.2723579331	Mar 24 01:34:57 PM PDT 24	Mar 24 01:59:52 PM PDT 24	13524276579 ps
T214	/workspace/coverage/default/16.sram_ctrl_partial_access.988156319	Mar 24 01:39:47 PM PDT 24	Mar 24 01:39:57 PM PDT 24	740269951 ps
T215	/workspace/coverage/default/1.sram_ctrl_executable.2861119302	Mar 24 01:34:58 PM PDT 24	Mar 24 02:07:04 PM PDT 24	45556403589 ps
T216	/workspace/coverage/default/9.sram_ctrl_mem_walk.1115640075	Mar 24 01:37:38 PM PDT 24	Mar 24 01:40:21 PM PDT 24	9330496781 ps
T138	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2099872937	Mar 24 01:39:10 PM PDT 24	Mar 24 01:40:33 PM PDT 24	20098331019 ps
T217	/workspace/coverage/default/10.sram_ctrl_ram_cfg.530362941	Mar 24 01:38:00 PM PDT 24	Mar 24 01:38:04 PM PDT 24	3740076421 ps
T84	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2304385095	Mar 24 01:45:07 PM PDT 24	Mar 24 01:47:30 PM PDT 24	5697797922 ps
T154	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.682098740	Mar 24 01:43:36 PM PDT 24	Mar 24 02:08:24 PM PDT 24	17947244844 ps
T218	/workspace/coverage/default/45.sram_ctrl_ram_cfg.1737996224	Mar 24 01:48:18 PM PDT 24	Mar 24 01:48:22 PM PDT 24	691389223 ps
T219	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3919539197	Mar 24 01:35:33 PM PDT 24	Mar 24 01:40:00 PM PDT 24	22767336477 ps
T220	/workspace/coverage/default/45.sram_ctrl_executable.2142777981	Mar 24 01:48:18 PM PDT 24	Mar 24 01:58:41 PM PDT 24	33923330749 ps
T221	/workspace/coverage/default/21.sram_ctrl_bijection.226517686	Mar 24 01:41:25 PM PDT 24	Mar 24 02:03:06 PM PDT 24	987761137103 ps
T33	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3832401965	Mar 24 01:42:14 PM PDT 24	Mar 24 01:42:29 PM PDT 24	2213738554 ps
T111	/workspace/coverage/default/6.sram_ctrl_max_throughput.2568242323	Mar 24 01:36:24 PM PDT 24	Mar 24 01:38:22 PM PDT 24	1577346019 ps
T112	/workspace/coverage/default/5.sram_ctrl_regwen.1093569477	Mar 24 01:36:15 PM PDT 24	Mar 24 01:50:22 PM PDT 24	11348143233 ps
T113	/workspace/coverage/default/4.sram_ctrl_mem_walk.2401949714	Mar 24 01:36:00 PM PDT 24	Mar 24 01:41:21 PM PDT 24	22096271659 ps
T114	/workspace/coverage/default/44.sram_ctrl_mem_walk.2750231568	Mar 24 01:48:06 PM PDT 24	Mar 24 01:50:50 PM PDT 24	21130721093 ps
T115	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4245782731	Mar 24 01:44:49 PM PDT 24	Mar 24 01:50:58 PM PDT 24	7563262757 ps
T21	/workspace/coverage/default/49.sram_ctrl_alert_test.2688039278	Mar 24 01:49:39 PM PDT 24	Mar 24 01:49:39 PM PDT 24	19111560 ps
T116	/workspace/coverage/default/29.sram_ctrl_partial_access.3521023277	Mar 24 01:43:33 PM PDT 24	Mar 24 01:43:52 PM PDT 24	1258878243 ps
T117	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2454355398	Mar 24 01:43:45 PM PDT 24	Mar 24 01:49:18 PM PDT 24	21890166444 ps
T118	/workspace/coverage/default/14.sram_ctrl_executable.543388560	Mar 24 01:39:24 PM PDT 24	Mar 24 01:57:59 PM PDT 24	16639797119 ps
T222	/workspace/coverage/default/27.sram_ctrl_lc_escalation.4159401332	Mar 24 01:43:02 PM PDT 24	Mar 24 01:44:13 PM PDT 24	24557765985 ps
T223	/workspace/coverage/default/8.sram_ctrl_mem_walk.4212937204	Mar 24 01:37:15 PM PDT 24	Mar 24 01:42:20 PM PDT 24	57376464912 ps
T224	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2931573718	Mar 24 01:46:46 PM PDT 24	Mar 24 01:51:35 PM PDT 24	24693439013 ps
T225	/workspace/coverage/default/12.sram_ctrl_stress_all.895576434	Mar 24 01:38:59 PM PDT 24	Mar 24 02:15:16 PM PDT 24	51913059024 ps
T226	/workspace/coverage/default/26.sram_ctrl_regwen.1840965786	Mar 24 01:42:37 PM PDT 24	Mar 24 02:05:36 PM PDT 24	15186872218 ps
T227	/workspace/coverage/default/7.sram_ctrl_bijection.2850906138	Mar 24 01:36:43 PM PDT 24	Mar 24 02:02:35 PM PDT 24	260809997917 ps
T228	/workspace/coverage/default/3.sram_ctrl_ram_cfg.1027332931	Mar 24 01:35:37 PM PDT 24	Mar 24 01:35:42 PM PDT 24	2786602335 ps
T229	/workspace/coverage/default/41.sram_ctrl_mem_walk.1286998041	Mar 24 01:47:09 PM PDT 24	Mar 24 01:52:12 PM PDT 24	20660259523 ps
T230	/workspace/coverage/default/24.sram_ctrl_partial_access.3097079114	Mar 24 01:42:08 PM PDT 24	Mar 24 01:42:28 PM PDT 24	2267684988 ps
T231	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1585525857	Mar 24 01:35:50 PM PDT 24	Mar 24 01:37:52 PM PDT 24	1429409120 ps
T232	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2133200822	Mar 24 01:49:18 PM PDT 24	Mar 24 01:51:26 PM PDT 24	6258234034 ps
T233	/workspace/coverage/default/31.sram_ctrl_mem_walk.398752076	Mar 24 01:44:19 PM PDT 24	Mar 24 01:48:55 PM PDT 24	29301133060 ps
T234	/workspace/coverage/default/43.sram_ctrl_partial_access.3696058141	Mar 24 01:47:33 PM PDT 24	Mar 24 01:47:43 PM PDT 24	2556535151 ps
T235	/workspace/coverage/default/28.sram_ctrl_lc_escalation.1256100657	Mar 24 01:43:16 PM PDT 24	Mar 24 01:44:13 PM PDT 24	18983144062 ps
T236	/workspace/coverage/default/23.sram_ctrl_partial_access.1299659910	Mar 24 01:41:46 PM PDT 24	Mar 24 01:41:54 PM PDT 24	710903043 ps
T139	/workspace/coverage/default/21.sram_ctrl_stress_all.330505023	Mar 24 01:41:33 PM PDT 24	Mar 24 02:46:53 PM PDT 24	65107545731 ps
T47	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3823660258	Mar 24 01:39:33 PM PDT 24	Mar 24 01:39:57 PM PDT 24	7280956975 ps
T237	/workspace/coverage/default/9.sram_ctrl_executable.1280195400	Mar 24 01:37:31 PM PDT 24	Mar 24 01:43:49 PM PDT 24	11483677938 ps
T238	/workspace/coverage/default/1.sram_ctrl_mem_walk.1218003475	Mar 24 01:35:02 PM PDT 24	Mar 24 01:39:49 PM PDT 24	28652718409 ps
T239	/workspace/coverage/default/39.sram_ctrl_alert_test.1788315375	Mar 24 01:46:40 PM PDT 24	Mar 24 01:46:40 PM PDT 24	13686302 ps
T240	/workspace/coverage/default/35.sram_ctrl_multiple_keys.2406294978	Mar 24 01:45:13 PM PDT 24	Mar 24 02:04:33 PM PDT 24	13186038507 ps
T241	/workspace/coverage/default/39.sram_ctrl_partial_access.3847222542	Mar 24 01:46:23 PM PDT 24	Mar 24 01:46:30 PM PDT 24	3048747117 ps
T242	/workspace/coverage/default/41.sram_ctrl_alert_test.3843840579	Mar 24 01:47:15 PM PDT 24	Mar 24 01:47:15 PM PDT 24	37524221 ps
T243	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1741721727	Mar 24 01:37:54 PM PDT 24	Mar 24 01:39:33 PM PDT 24	3074876446 ps
T244	/workspace/coverage/default/19.sram_ctrl_stress_all.2453516098	Mar 24 01:40:41 PM PDT 24	Mar 24 02:26:54 PM PDT 24	370282826353 ps
T140	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2338801997	Mar 24 01:47:35 PM PDT 24	Mar 24 01:54:30 PM PDT 24	99357387047 ps
T48	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.427293929	Mar 24 01:47:30 PM PDT 24	Mar 24 01:47:45 PM PDT 24	1785446405 ps
T245	/workspace/coverage/default/15.sram_ctrl_regwen.1671498721	Mar 24 01:39:32 PM PDT 24	Mar 24 01:46:19 PM PDT 24	1472045756 ps
T49	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3301161513	Mar 24 01:48:48 PM PDT 24	Mar 24 01:49:21 PM PDT 24	3997318386 ps
T246	/workspace/coverage/default/9.sram_ctrl_bijection.4110758742	Mar 24 01:37:22 PM PDT 24	Mar 24 02:07:15 PM PDT 24	81684506192 ps
T247	/workspace/coverage/default/18.sram_ctrl_regwen.3187770995	Mar 24 01:40:16 PM PDT 24	Mar 24 02:09:24 PM PDT 24	3521445313 ps
T248	/workspace/coverage/default/20.sram_ctrl_bijection.380410068	Mar 24 01:40:48 PM PDT 24	Mar 24 01:59:29 PM PDT 24	52996405820 ps
T249	/workspace/coverage/default/36.sram_ctrl_bijection.253964605	Mar 24 01:45:31 PM PDT 24	Mar 24 02:01:47 PM PDT 24	37349355178 ps
T250	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3585699807	Mar 24 01:37:13 PM PDT 24	Mar 24 01:52:18 PM PDT 24	11659131321 ps
T251	/workspace/coverage/default/41.sram_ctrl_max_throughput.1629604848	Mar 24 01:46:58 PM PDT 24	Mar 24 01:47:34 PM PDT 24	3960972151 ps
T252	/workspace/coverage/default/23.sram_ctrl_bijection.2892906431	Mar 24 01:41:46 PM PDT 24	Mar 24 02:14:50 PM PDT 24	179382041369 ps
T253	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1162538609	Mar 24 01:36:23 PM PDT 24	Mar 24 01:37:05 PM PDT 24	3075653929 ps
T254	/workspace/coverage/default/24.sram_ctrl_smoke.1240342324	Mar 24 01:42:05 PM PDT 24	Mar 24 01:42:12 PM PDT 24	1106687999 ps
T255	/workspace/coverage/default/31.sram_ctrl_max_throughput.2326001506	Mar 24 01:44:14 PM PDT 24	Mar 24 01:44:27 PM PDT 24	2876519903 ps
T256	/workspace/coverage/default/21.sram_ctrl_lc_escalation.79883792	Mar 24 01:41:27 PM PDT 24	Mar 24 01:42:19 PM PDT 24	8883161166 ps
T257	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3349675470	Mar 24 01:41:58 PM PDT 24	Mar 24 01:43:11 PM PDT 24	3643364912 ps
T258	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3170039654	Mar 24 01:34:47 PM PDT 24	Mar 24 01:39:50 PM PDT 24	4193002267 ps
T259	/workspace/coverage/default/32.sram_ctrl_stress_all.1415226197	Mar 24 01:44:36 PM PDT 24	Mar 24 02:25:36 PM PDT 24	289274425006 ps
T260	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1230205431	Mar 24 01:42:41 PM PDT 24	Mar 24 01:44:02 PM PDT 24	2348619754 ps
T261	/workspace/coverage/default/22.sram_ctrl_mem_walk.236923774	Mar 24 01:41:37 PM PDT 24	Mar 24 01:44:31 PM PDT 24	98583073361 ps
T262	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3441227957	Mar 24 01:36:19 PM PDT 24	Mar 24 01:38:51 PM PDT 24	4634152669 ps
T263	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3821905867	Mar 24 01:44:49 PM PDT 24	Mar 24 01:46:30 PM PDT 24	3166347643 ps
T50	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.160220934	Mar 24 01:44:00 PM PDT 24	Mar 24 01:44:37 PM PDT 24	1195893729 ps
T264	/workspace/coverage/default/49.sram_ctrl_stress_all.3736636528	Mar 24 01:49:38 PM PDT 24	Mar 24 03:11:30 PM PDT 24	805092077395 ps
T265	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1319945037	Mar 24 01:36:28 PM PDT 24	Mar 24 02:02:16 PM PDT 24	42015564155 ps
T266	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.4292306283	Mar 24 01:43:07 PM PDT 24	Mar 24 01:44:11 PM PDT 24	18902129050 ps
T267	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.822558445	Mar 24 01:42:30 PM PDT 24	Mar 24 01:44:57 PM PDT 24	2655010745 ps
T268	/workspace/coverage/default/33.sram_ctrl_alert_test.192271365	Mar 24 01:44:59 PM PDT 24	Mar 24 01:45:00 PM PDT 24	14915686 ps
T269	/workspace/coverage/default/8.sram_ctrl_executable.1169239797	Mar 24 01:37:14 PM PDT 24	Mar 24 01:48:13 PM PDT 24	8229808587 ps
T270	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1464632880	Mar 24 01:37:39 PM PDT 24	Mar 24 01:40:20 PM PDT 24	4657378174 ps
T271	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.127534821	Mar 24 01:40:05 PM PDT 24	Mar 24 01:40:50 PM PDT 24	1580654560 ps
T272	/workspace/coverage/default/1.sram_ctrl_ram_cfg.2644849957	Mar 24 01:35:04 PM PDT 24	Mar 24 01:35:07 PM PDT 24	359661067 ps
T273	/workspace/coverage/default/34.sram_ctrl_alert_test.134779091	Mar 24 01:45:13 PM PDT 24	Mar 24 01:45:14 PM PDT 24	43068334 ps
T274	/workspace/coverage/default/8.sram_ctrl_multiple_keys.373627187	Mar 24 01:37:03 PM PDT 24	Mar 24 02:00:19 PM PDT 24	98106568367 ps
T275	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2746331921	Mar 24 01:34:39 PM PDT 24	Mar 24 01:34:52 PM PDT 24	1397044088 ps
T276	/workspace/coverage/default/15.sram_ctrl_mem_walk.4251176745	Mar 24 01:39:33 PM PDT 24	Mar 24 01:41:40 PM PDT 24	4205134277 ps
T277	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2607550930	Mar 24 01:44:25 PM PDT 24	Mar 24 01:47:11 PM PDT 24	14354623398 ps
T278	/workspace/coverage/default/27.sram_ctrl_alert_test.1088234552	Mar 24 01:43:13 PM PDT 24	Mar 24 01:43:14 PM PDT 24	46247554 ps
T279	/workspace/coverage/default/8.sram_ctrl_stress_all.4160362805	Mar 24 01:37:12 PM PDT 24	Mar 24 03:57:33 PM PDT 24	515487755956 ps
T280	/workspace/coverage/default/48.sram_ctrl_alert_test.1990742104	Mar 24 01:49:24 PM PDT 24	Mar 24 01:49:25 PM PDT 24	24913460 ps
T281	/workspace/coverage/default/9.sram_ctrl_stress_all.3529051291	Mar 24 01:37:39 PM PDT 24	Mar 24 03:06:12 PM PDT 24	339004324524 ps
T282	/workspace/coverage/default/14.sram_ctrl_lc_escalation.2619099456	Mar 24 01:39:22 PM PDT 24	Mar 24 01:40:44 PM PDT 24	40612466761 ps
T51	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.444692930	Mar 24 01:48:19 PM PDT 24	Mar 24 01:48:44 PM PDT 24	1955987044 ps
T283	/workspace/coverage/default/25.sram_ctrl_multiple_keys.2794955300	Mar 24 01:42:18 PM PDT 24	Mar 24 02:04:24 PM PDT 24	18527865176 ps
T284	/workspace/coverage/default/40.sram_ctrl_lc_escalation.140759908	Mar 24 01:46:46 PM PDT 24	Mar 24 01:47:46 PM PDT 24	41014578456 ps
T285	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2429126114	Mar 24 01:45:47 PM PDT 24	Mar 24 01:51:55 PM PDT 24	65446452932 ps
T286	/workspace/coverage/default/31.sram_ctrl_lc_escalation.2805708931	Mar 24 01:44:14 PM PDT 24	Mar 24 01:45:26 PM PDT 24	68795536110 ps
T287	/workspace/coverage/default/36.sram_ctrl_executable.1470842739	Mar 24 01:45:45 PM PDT 24	Mar 24 01:46:41 PM PDT 24	1465169283 ps
T288	/workspace/coverage/default/15.sram_ctrl_ram_cfg.1172185352	Mar 24 01:39:31 PM PDT 24	Mar 24 01:39:35 PM PDT 24	1405360094 ps
T289	/workspace/coverage/default/22.sram_ctrl_max_throughput.2474782821	Mar 24 01:41:31 PM PDT 24	Mar 24 01:42:56 PM PDT 24	14818139379 ps
T290	/workspace/coverage/default/14.sram_ctrl_partial_access.1923081912	Mar 24 01:39:16 PM PDT 24	Mar 24 01:39:31 PM PDT 24	1699515939 ps
T52	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2792256897	Mar 24 01:35:00 PM PDT 24	Mar 24 01:35:20 PM PDT 24	1959670192 ps
T291	/workspace/coverage/default/11.sram_ctrl_mem_walk.582699734	Mar 24 01:38:25 PM PDT 24	Mar 24 01:40:51 PM PDT 24	6874612425 ps
T292	/workspace/coverage/default/24.sram_ctrl_stress_all.3866026273	Mar 24 01:42:19 PM PDT 24	Mar 24 03:46:57 PM PDT 24	231861661451 ps
T293	/workspace/coverage/default/5.sram_ctrl_stress_all.2146408273	Mar 24 01:36:18 PM PDT 24	Mar 24 02:11:27 PM PDT 24	73729615701 ps
T294	/workspace/coverage/default/15.sram_ctrl_smoke.1362218509	Mar 24 01:39:27 PM PDT 24	Mar 24 01:39:33 PM PDT 24	423194029 ps
T295	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1546377053	Mar 24 01:43:33 PM PDT 24	Mar 24 01:50:55 PM PDT 24	19407915091 ps
T141	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1658965181	Mar 24 01:45:05 PM PDT 24	Mar 24 01:50:25 PM PDT 24	14985026926 ps
T296	/workspace/coverage/default/44.sram_ctrl_lc_escalation.4097870617	Mar 24 01:47:59 PM PDT 24	Mar 24 01:48:33 PM PDT 24	5651915704 ps
T297	/workspace/coverage/default/21.sram_ctrl_multiple_keys.2798097046	Mar 24 01:41:25 PM PDT 24	Mar 24 02:05:58 PM PDT 24	29126063652 ps
T298	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.159153254	Mar 24 01:38:18 PM PDT 24	Mar 24 02:22:59 PM PDT 24	59501354686 ps
T299	/workspace/coverage/default/9.sram_ctrl_max_throughput.3106517821	Mar 24 01:37:22 PM PDT 24	Mar 24 01:39:29 PM PDT 24	7633550662 ps