Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	141750980	1			T1	4866		T2	2974		T3	6496
triple_byte_access	2708042	1			T1	217		T2	7047		T3	277
halfword_access	4155772	1			T1	307		T2	13258		T3	427
byte_access	5819765	1			T1	403		T2	24753		T3	600
zero_access	1767316	1			T1	101		T2	14539		T3	152

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77795200

1

T1

2899

T2

31019

T3

4028

auto[1]

78406675

1

T1

2995

T2

31552

T3

3924

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70437045	1			T1	2373		T2	258		T3	3299
auto[0]	triple_byte_access	1288995	1			T1	98		T2	1294		T3	137
auto[0]	halfword_access	2029257	1			T1	171		T2	4495		T3	211
auto[0]	byte_access	2982314	1			T1	202		T2	13265		T3	304
auto[0]	zero_access	1057589	1			T1	55		T2	11707		T3	77
auto[1]	word_access	71313935	1			T1	2493		T2	2716		T3	3197
auto[1]	triple_byte_access	1419047	1			T1	119		T2	5753		T3	140
auto[1]	halfword_access	2126515	1			T1	136		T2	8763		T3	216
auto[1]	byte_access	2837451	1			T1	201		T2	11488		T3	296
auto[1]	zero_access	709727	1			T1	46		T2	2832		T3	75