| T792 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3787835666 |
|
|
Mar 24 01:49:27 PM PDT 24 |
Mar 24 01:50:25 PM PDT 24 |
2958624127 ps |
| T793 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1663813552 |
|
|
Mar 24 01:40:41 PM PDT 24 |
Mar 24 01:40:50 PM PDT 24 |
254942331 ps |
| T794 |
/workspace/coverage/default/21.sram_ctrl_executable.1872605397 |
|
|
Mar 24 01:41:31 PM PDT 24 |
Mar 24 01:55:55 PM PDT 24 |
20152852143 ps |
| T795 |
/workspace/coverage/default/27.sram_ctrl_regwen.1782254834 |
|
|
Mar 24 01:43:08 PM PDT 24 |
Mar 24 01:56:45 PM PDT 24 |
3223509916 ps |
| T796 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3187303832 |
|
|
Mar 24 01:45:57 PM PDT 24 |
Mar 24 01:46:51 PM PDT 24 |
1969569695 ps |
| T797 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3177699369 |
|
|
Mar 24 01:43:11 PM PDT 24 |
Mar 24 01:48:32 PM PDT 24 |
4639598182 ps |
| T798 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.361596504 |
|
|
Mar 24 01:36:50 PM PDT 24 |
Mar 24 01:37:23 PM PDT 24 |
20389112558 ps |
| T799 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1717909386 |
|
|
Mar 24 01:37:18 PM PDT 24 |
Mar 24 01:37:18 PM PDT 24 |
16422906 ps |
| T800 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3385904382 |
|
|
Mar 24 01:45:47 PM PDT 24 |
Mar 24 01:46:36 PM PDT 24 |
772758832 ps |
| T801 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.79515333 |
|
|
Mar 24 01:46:10 PM PDT 24 |
Mar 24 01:48:17 PM PDT 24 |
234532878876 ps |
| T802 |
/workspace/coverage/default/3.sram_ctrl_smoke.3455826936 |
|
|
Mar 24 01:35:28 PM PDT 24 |
Mar 24 01:35:47 PM PDT 24 |
1118097448 ps |
| T803 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4214778982 |
|
|
Mar 24 01:47:18 PM PDT 24 |
Mar 24 01:47:29 PM PDT 24 |
2750950434 ps |
| T804 |
/workspace/coverage/default/34.sram_ctrl_executable.3564713194 |
|
|
Mar 24 01:45:06 PM PDT 24 |
Mar 24 02:06:45 PM PDT 24 |
37142842733 ps |
| T805 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3517900818 |
|
|
Mar 24 01:45:58 PM PDT 24 |
Mar 24 01:47:02 PM PDT 24 |
1036265509 ps |
| T806 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2333003947 |
|
|
Mar 24 01:38:18 PM PDT 24 |
Mar 24 01:42:53 PM PDT 24 |
73808853985 ps |
| T807 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1683584591 |
|
|
Mar 24 01:41:52 PM PDT 24 |
Mar 24 01:42:17 PM PDT 24 |
12388226436 ps |
| T808 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3980772000 |
|
|
Mar 24 01:46:03 PM PDT 24 |
Mar 24 01:50:59 PM PDT 24 |
4121720554 ps |
| T809 |
/workspace/coverage/default/15.sram_ctrl_alert_test.271254321 |
|
|
Mar 24 01:39:39 PM PDT 24 |
Mar 24 01:39:41 PM PDT 24 |
14753283 ps |
| T810 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.247048549 |
|
|
Mar 24 01:38:24 PM PDT 24 |
Mar 24 01:39:42 PM PDT 24 |
9400207939 ps |
| T811 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3371472171 |
|
|
Mar 24 01:39:47 PM PDT 24 |
Mar 24 01:39:54 PM PDT 24 |
1381819023 ps |
| T812 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3810362949 |
|
|
Mar 24 01:49:04 PM PDT 24 |
Mar 24 01:51:29 PM PDT 24 |
2718320442 ps |
| T813 |
/workspace/coverage/default/41.sram_ctrl_executable.3944593092 |
|
|
Mar 24 01:47:03 PM PDT 24 |
Mar 24 01:58:25 PM PDT 24 |
73219454494 ps |
| T814 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2666702385 |
|
|
Mar 24 01:39:04 PM PDT 24 |
Mar 24 01:42:24 PM PDT 24 |
6004934232 ps |
| T815 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.1096354393 |
|
|
Mar 24 01:45:22 PM PDT 24 |
Mar 24 01:50:28 PM PDT 24 |
21291421837 ps |
| T816 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3126889301 |
|
|
Mar 24 01:39:52 PM PDT 24 |
Mar 24 01:42:37 PM PDT 24 |
41402719406 ps |
| T817 |
/workspace/coverage/default/47.sram_ctrl_bijection.1931587727 |
|
|
Mar 24 01:48:49 PM PDT 24 |
Mar 24 02:11:05 PM PDT 24 |
19078436682 ps |
| T818 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2767966457 |
|
|
Mar 24 01:45:05 PM PDT 24 |
Mar 24 01:45:12 PM PDT 24 |
705188786 ps |
| T819 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.54877329 |
|
|
Mar 24 01:42:08 PM PDT 24 |
Mar 24 01:42:49 PM PDT 24 |
2902779264 ps |
| T820 |
/workspace/coverage/default/30.sram_ctrl_smoke.4292221890 |
|
|
Mar 24 01:43:44 PM PDT 24 |
Mar 24 01:45:29 PM PDT 24 |
456686349 ps |
| T821 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2997605885 |
|
|
Mar 24 01:42:19 PM PDT 24 |
Mar 24 01:44:17 PM PDT 24 |
1571368310 ps |
| T822 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.660250549 |
|
|
Mar 24 01:41:24 PM PDT 24 |
Mar 24 01:47:43 PM PDT 24 |
7014507416 ps |
| T823 |
/workspace/coverage/default/47.sram_ctrl_smoke.1816334020 |
|
|
Mar 24 01:48:54 PM PDT 24 |
Mar 24 01:48:58 PM PDT 24 |
513966808 ps |
| T824 |
/workspace/coverage/default/37.sram_ctrl_executable.783910176 |
|
|
Mar 24 01:45:52 PM PDT 24 |
Mar 24 02:06:08 PM PDT 24 |
9051016160 ps |
| T825 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1561296504 |
|
|
Mar 24 01:46:55 PM PDT 24 |
Mar 24 01:49:10 PM PDT 24 |
1033692192 ps |
| T826 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3697451496 |
|
|
Mar 24 01:40:56 PM PDT 24 |
Mar 24 01:41:11 PM PDT 24 |
1118401471 ps |
| T827 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.788996669 |
|
|
Mar 24 01:41:30 PM PDT 24 |
Mar 24 01:41:42 PM PDT 24 |
280855580 ps |
| T828 |
/workspace/coverage/default/16.sram_ctrl_alert_test.682174578 |
|
|
Mar 24 01:39:52 PM PDT 24 |
Mar 24 01:39:52 PM PDT 24 |
37884383 ps |
| T829 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2354393793 |
|
|
Mar 24 01:49:20 PM PDT 24 |
Mar 24 01:49:43 PM PDT 24 |
2352112757 ps |
| T830 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.496494473 |
|
|
Mar 24 01:45:04 PM PDT 24 |
Mar 24 01:48:17 PM PDT 24 |
5309237067 ps |
| T831 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3915753684 |
|
|
Mar 24 01:37:33 PM PDT 24 |
Mar 24 01:50:10 PM PDT 24 |
46866888947 ps |
| T832 |
/workspace/coverage/default/2.sram_ctrl_smoke.3341679572 |
|
|
Mar 24 01:35:10 PM PDT 24 |
Mar 24 01:35:31 PM PDT 24 |
2944647790 ps |
| T833 |
/workspace/coverage/default/5.sram_ctrl_partial_access.770770675 |
|
|
Mar 24 01:36:03 PM PDT 24 |
Mar 24 01:36:11 PM PDT 24 |
920430879 ps |
| T834 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3197799631 |
|
|
Mar 24 01:47:05 PM PDT 24 |
Mar 24 02:11:42 PM PDT 24 |
59197491663 ps |
| T835 |
/workspace/coverage/default/10.sram_ctrl_executable.11963330 |
|
|
Mar 24 01:37:54 PM PDT 24 |
Mar 24 01:39:11 PM PDT 24 |
15398723941 ps |
| T836 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1132154006 |
|
|
Mar 24 01:45:28 PM PDT 24 |
Mar 24 01:45:47 PM PDT 24 |
572876029 ps |
| T837 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.504699308 |
|
|
Mar 24 01:48:44 PM PDT 24 |
Mar 24 01:51:10 PM PDT 24 |
10180348154 ps |
| T838 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.481151829 |
|
|
Mar 24 01:41:31 PM PDT 24 |
Mar 24 02:03:01 PM PDT 24 |
105350179315 ps |
| T839 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1081709825 |
|
|
Mar 24 01:39:16 PM PDT 24 |
Mar 24 01:39:32 PM PDT 24 |
1468735393 ps |
| T840 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3463640677 |
|
|
Mar 24 01:49:33 PM PDT 24 |
Mar 24 02:22:41 PM PDT 24 |
84397878790 ps |
| T841 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1581184392 |
|
|
Mar 24 01:36:59 PM PDT 24 |
Mar 24 01:37:00 PM PDT 24 |
15946168 ps |
| T842 |
/workspace/coverage/default/47.sram_ctrl_regwen.998483254 |
|
|
Mar 24 01:49:00 PM PDT 24 |
Mar 24 02:10:05 PM PDT 24 |
31338479317 ps |
| T843 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2294781092 |
|
|
Mar 24 01:37:13 PM PDT 24 |
Mar 24 01:37:17 PM PDT 24 |
1357222521 ps |
| T844 |
/workspace/coverage/default/34.sram_ctrl_regwen.2398776844 |
|
|
Mar 24 01:45:07 PM PDT 24 |
Mar 24 01:54:51 PM PDT 24 |
75296034811 ps |
| T845 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4266172243 |
|
|
Mar 24 01:35:58 PM PDT 24 |
Mar 24 01:40:23 PM PDT 24 |
10804170305 ps |
| T846 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2947442335 |
|
|
Mar 24 01:43:34 PM PDT 24 |
Mar 24 01:45:43 PM PDT 24 |
812132814 ps |
| T847 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1142612233 |
|
|
Mar 24 01:49:29 PM PDT 24 |
Mar 24 01:49:51 PM PDT 24 |
8171879829 ps |
| T848 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.636686606 |
|
|
Mar 24 01:49:33 PM PDT 24 |
Mar 24 01:54:46 PM PDT 24 |
86092442199 ps |
| T849 |
/workspace/coverage/default/42.sram_ctrl_alert_test.4066261688 |
|
|
Mar 24 01:47:30 PM PDT 24 |
Mar 24 01:47:31 PM PDT 24 |
13902126 ps |
| T850 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3544753816 |
|
|
Mar 24 01:35:06 PM PDT 24 |
Mar 24 01:48:43 PM PDT 24 |
30442093801 ps |
| T851 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1710195348 |
|
|
Mar 24 01:40:34 PM PDT 24 |
Mar 24 01:49:13 PM PDT 24 |
47797199662 ps |
| T852 |
/workspace/coverage/default/36.sram_ctrl_smoke.3252136560 |
|
|
Mar 24 01:45:31 PM PDT 24 |
Mar 24 01:45:38 PM PDT 24 |
1940079953 ps |
| T853 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4260493383 |
|
|
Mar 24 01:36:48 PM PDT 24 |
Mar 24 01:41:35 PM PDT 24 |
13709863200 ps |
| T854 |
/workspace/coverage/default/46.sram_ctrl_smoke.1896100912 |
|
|
Mar 24 01:48:19 PM PDT 24 |
Mar 24 01:48:33 PM PDT 24 |
825257921 ps |
| T855 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2488707869 |
|
|
Mar 24 01:44:22 PM PDT 24 |
Mar 24 01:45:05 PM PDT 24 |
1484769035 ps |
| T856 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3598623987 |
|
|
Mar 24 01:37:29 PM PDT 24 |
Mar 24 01:38:47 PM PDT 24 |
17580001558 ps |
| T857 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3715975743 |
|
|
Mar 24 01:40:04 PM PDT 24 |
Mar 24 01:55:35 PM PDT 24 |
12504191733 ps |
| T858 |
/workspace/coverage/default/6.sram_ctrl_executable.2564733567 |
|
|
Mar 24 01:36:28 PM PDT 24 |
Mar 24 01:47:43 PM PDT 24 |
9616508568 ps |
| T859 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.303208354 |
|
|
Mar 24 01:48:31 PM PDT 24 |
Mar 24 01:50:23 PM PDT 24 |
773563384 ps |
| T860 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1277438212 |
|
|
Mar 24 01:45:08 PM PDT 24 |
Mar 24 01:45:11 PM PDT 24 |
350871628 ps |
| T861 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2259264918 |
|
|
Mar 24 01:39:40 PM PDT 24 |
Mar 24 01:44:45 PM PDT 24 |
5352650067 ps |
| T862 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2932790982 |
|
|
Mar 24 01:46:51 PM PDT 24 |
Mar 24 01:47:05 PM PDT 24 |
1915414633 ps |
| T863 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.702636179 |
|
|
Mar 24 01:45:17 PM PDT 24 |
Mar 24 01:46:42 PM PDT 24 |
784021654 ps |
| T864 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1624398675 |
|
|
Mar 24 01:38:32 PM PDT 24 |
Mar 24 01:50:13 PM PDT 24 |
58167547810 ps |
| T865 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.2127522806 |
|
|
Mar 24 01:38:37 PM PDT 24 |
Mar 24 01:40:24 PM PDT 24 |
3897819994 ps |
| T866 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1790874406 |
|
|
Mar 24 01:43:17 PM PDT 24 |
Mar 24 01:47:54 PM PDT 24 |
86826002557 ps |
| T867 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1217357987 |
|
|
Mar 24 01:43:49 PM PDT 24 |
Mar 24 01:48:09 PM PDT 24 |
3383205974 ps |
| T868 |
/workspace/coverage/default/38.sram_ctrl_executable.2706424549 |
|
|
Mar 24 01:46:15 PM PDT 24 |
Mar 24 01:51:35 PM PDT 24 |
10542980404 ps |
| T869 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.170945864 |
|
|
Mar 24 01:45:33 PM PDT 24 |
Mar 24 01:53:05 PM PDT 24 |
72832162298 ps |
| T870 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2956325557 |
|
|
Mar 24 01:43:22 PM PDT 24 |
Mar 24 01:43:59 PM PDT 24 |
788369943 ps |
| T871 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.1064705817 |
|
|
Mar 24 01:36:15 PM PDT 24 |
Mar 24 01:39:03 PM PDT 24 |
10884986576 ps |
| T872 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3237147057 |
|
|
Mar 24 01:48:58 PM PDT 24 |
Mar 24 01:49:02 PM PDT 24 |
349935016 ps |
| T873 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1102493402 |
|
|
Mar 24 01:46:44 PM PDT 24 |
Mar 24 01:47:00 PM PDT 24 |
4583535894 ps |
| T874 |
/workspace/coverage/default/27.sram_ctrl_partial_access.4018180285 |
|
|
Mar 24 01:42:52 PM PDT 24 |
Mar 24 01:43:07 PM PDT 24 |
3289357950 ps |
| T875 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3814370989 |
|
|
Mar 24 01:44:07 PM PDT 24 |
Mar 24 02:25:42 PM PDT 24 |
42060596230 ps |
| T876 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3792843367 |
|
|
Mar 24 01:37:46 PM PDT 24 |
Mar 24 01:41:02 PM PDT 24 |
20915717764 ps |
| T877 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.96219896 |
|
|
Mar 24 01:45:31 PM PDT 24 |
Mar 24 02:04:38 PM PDT 24 |
94250575963 ps |
| T878 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.2656589692 |
|
|
Mar 24 01:43:23 PM PDT 24 |
Mar 24 01:48:36 PM PDT 24 |
18302224192 ps |
| T879 |
/workspace/coverage/default/32.sram_ctrl_regwen.2976778102 |
|
|
Mar 24 01:44:34 PM PDT 24 |
Mar 24 02:05:18 PM PDT 24 |
12234421729 ps |
| T880 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3451814009 |
|
|
Mar 24 01:40:29 PM PDT 24 |
Mar 24 01:40:30 PM PDT 24 |
13399474 ps |
| T881 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2538590198 |
|
|
Mar 24 01:45:13 PM PDT 24 |
Mar 24 03:08:01 PM PDT 24 |
92841326729 ps |
| T882 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.20094040 |
|
|
Mar 24 01:35:33 PM PDT 24 |
Mar 24 01:37:07 PM PDT 24 |
4095964694 ps |
| T883 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1775540678 |
|
|
Mar 24 01:34:49 PM PDT 24 |
Mar 24 01:39:17 PM PDT 24 |
4488895753 ps |
| T884 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.4264422072 |
|
|
Mar 24 01:39:23 PM PDT 24 |
Mar 24 01:39:50 PM PDT 24 |
928905228 ps |
| T885 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2534010083 |
|
|
Mar 24 01:41:26 PM PDT 24 |
Mar 24 01:42:02 PM PDT 24 |
915875092 ps |
| T886 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1325824383 |
|
|
Mar 24 01:42:53 PM PDT 24 |
Mar 24 01:46:13 PM PDT 24 |
4876140524 ps |
| T887 |
/workspace/coverage/default/12.sram_ctrl_regwen.1910929716 |
|
|
Mar 24 01:38:43 PM PDT 24 |
Mar 24 01:50:55 PM PDT 24 |
4338014974 ps |
| T888 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2863218211 |
|
|
Mar 24 01:37:13 PM PDT 24 |
Mar 24 01:43:23 PM PDT 24 |
16171218721 ps |
| T889 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1524754169 |
|
|
Mar 24 01:47:45 PM PDT 24 |
Mar 24 01:50:22 PM PDT 24 |
10641570067 ps |
| T890 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1918144593 |
|
|
Mar 24 01:46:45 PM PDT 24 |
Mar 24 01:51:42 PM PDT 24 |
11450821581 ps |
| T891 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3271484955 |
|
|
Mar 24 01:46:21 PM PDT 24 |
Mar 24 01:48:59 PM PDT 24 |
34296229952 ps |
| T892 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2601865459 |
|
|
Mar 24 01:37:01 PM PDT 24 |
Mar 24 01:39:12 PM PDT 24 |
2081546137 ps |
| T893 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1444200010 |
|
|
Mar 24 01:40:15 PM PDT 24 |
Mar 24 02:16:02 PM PDT 24 |
38055229546 ps |
| T894 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2411880835 |
|
|
Mar 24 01:39:52 PM PDT 24 |
Mar 24 01:42:18 PM PDT 24 |
20761129474 ps |
| T895 |
/workspace/coverage/default/10.sram_ctrl_smoke.429438851 |
|
|
Mar 24 01:37:45 PM PDT 24 |
Mar 24 01:37:54 PM PDT 24 |
1650988497 ps |
| T896 |
/workspace/coverage/default/43.sram_ctrl_alert_test.420240289 |
|
|
Mar 24 01:47:50 PM PDT 24 |
Mar 24 01:47:50 PM PDT 24 |
38131558 ps |
| T897 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.15063643 |
|
|
Mar 24 01:44:49 PM PDT 24 |
Mar 24 01:45:14 PM PDT 24 |
3428435870 ps |
| T898 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.295975566 |
|
|
Mar 24 01:44:59 PM PDT 24 |
Mar 24 01:51:02 PM PDT 24 |
14000137957 ps |
| T899 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.27639351 |
|
|
Mar 24 01:39:52 PM PDT 24 |
Mar 24 01:40:03 PM PDT 24 |
1417645385 ps |
| T900 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1982642838 |
|
|
Mar 24 01:49:19 PM PDT 24 |
Mar 24 01:49:22 PM PDT 24 |
1411221108 ps |
| T901 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3569352530 |
|
|
Mar 24 01:38:32 PM PDT 24 |
Mar 24 01:38:33 PM PDT 24 |
80193211 ps |
| T902 |
/workspace/coverage/default/12.sram_ctrl_executable.3580460178 |
|
|
Mar 24 01:38:43 PM PDT 24 |
Mar 24 01:45:49 PM PDT 24 |
18239512406 ps |
| T903 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2290953669 |
|
|
Mar 24 01:39:41 PM PDT 24 |
Mar 24 02:06:33 PM PDT 24 |
25090051513 ps |
| T904 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.3030151539 |
|
|
Mar 24 01:41:45 PM PDT 24 |
Mar 24 02:00:58 PM PDT 24 |
76182835073 ps |
| T905 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1551194517 |
|
|
Mar 24 01:40:12 PM PDT 24 |
Mar 24 02:31:27 PM PDT 24 |
80818008006 ps |
| T906 |
/workspace/coverage/default/28.sram_ctrl_regwen.728174070 |
|
|
Mar 24 01:43:22 PM PDT 24 |
Mar 24 02:04:43 PM PDT 24 |
26924579319 ps |
| T907 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3019686404 |
|
|
Mar 24 01:36:09 PM PDT 24 |
Mar 24 01:38:45 PM PDT 24 |
824004176 ps |
| T908 |
/workspace/coverage/default/19.sram_ctrl_bijection.963012693 |
|
|
Mar 24 01:40:36 PM PDT 24 |
Mar 24 02:16:31 PM PDT 24 |
304836416028 ps |
| T909 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.555352854 |
|
|
Mar 24 01:37:54 PM PDT 24 |
Mar 24 01:38:34 PM PDT 24 |
23907819191 ps |
| T910 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1610147328 |
|
|
Mar 24 01:39:53 PM PDT 24 |
Mar 24 01:39:56 PM PDT 24 |
360060600 ps |
| T911 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2402473009 |
|
|
Mar 24 01:49:28 PM PDT 24 |
Mar 24 01:49:55 PM PDT 24 |
755068817 ps |
| T912 |
/workspace/coverage/default/46.sram_ctrl_bijection.3863970440 |
|
|
Mar 24 01:48:22 PM PDT 24 |
Mar 24 02:02:02 PM PDT 24 |
148250685035 ps |
| T913 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3451707013 |
|
|
Mar 24 01:48:00 PM PDT 24 |
Mar 24 01:57:08 PM PDT 24 |
14627791433 ps |
| T914 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1161326402 |
|
|
Mar 24 01:36:25 PM PDT 24 |
Mar 24 01:38:23 PM PDT 24 |
3476823155 ps |
| T915 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2915496775 |
|
|
Mar 24 01:35:59 PM PDT 24 |
Mar 24 02:43:31 PM PDT 24 |
342409266003 ps |
| T916 |
/workspace/coverage/default/2.sram_ctrl_executable.1339914492 |
|
|
Mar 24 01:35:11 PM PDT 24 |
Mar 24 01:52:55 PM PDT 24 |
19786452452 ps |
| T917 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2466034023 |
|
|
Mar 24 01:45:54 PM PDT 24 |
Mar 24 01:46:44 PM PDT 24 |
3115452656 ps |
| T918 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2846079687 |
|
|
Mar 24 01:38:31 PM PDT 24 |
Mar 24 01:41:41 PM PDT 24 |
9071447361 ps |
| T919 |
/workspace/coverage/default/32.sram_ctrl_partial_access.4199454308 |
|
|
Mar 24 01:44:25 PM PDT 24 |
Mar 24 01:44:45 PM PDT 24 |
1259071375 ps |
| T920 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1995401220 |
|
|
Mar 24 01:39:59 PM PDT 24 |
Mar 24 01:49:51 PM PDT 24 |
90312994159 ps |
| T921 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.268212763 |
|
|
Mar 24 01:37:00 PM PDT 24 |
Mar 24 01:38:10 PM PDT 24 |
1969322561 ps |
| T922 |
/workspace/coverage/default/3.sram_ctrl_partial_access.182896430 |
|
|
Mar 24 01:35:34 PM PDT 24 |
Mar 24 01:35:55 PM PDT 24 |
3136152699 ps |
| T923 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2969161753 |
|
|
Mar 24 01:38:44 PM PDT 24 |
Mar 24 01:44:25 PM PDT 24 |
7033282917 ps |
| T924 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.546418070 |
|
|
Mar 24 01:39:46 PM PDT 24 |
Mar 24 01:41:16 PM PDT 24 |
48340581140 ps |
| T925 |
/workspace/coverage/default/25.sram_ctrl_executable.500321576 |
|
|
Mar 24 01:42:24 PM PDT 24 |
Mar 24 01:50:22 PM PDT 24 |
64186507173 ps |
| T926 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3307506522 |
|
|
Mar 24 01:41:25 PM PDT 24 |
Mar 24 01:41:26 PM PDT 24 |
20569768 ps |
| T927 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3649053131 |
|
|
Mar 24 01:40:04 PM PDT 24 |
Mar 24 01:41:20 PM PDT 24 |
46324455616 ps |
| T928 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.557773862 |
|
|
Mar 24 01:42:07 PM PDT 24 |
Mar 24 01:48:37 PM PDT 24 |
319557965809 ps |
| T929 |
/workspace/coverage/default/6.sram_ctrl_alert_test.649848602 |
|
|
Mar 24 01:36:39 PM PDT 24 |
Mar 24 01:36:40 PM PDT 24 |
34313954 ps |
| T930 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.3091759475 |
|
|
Mar 24 01:41:31 PM PDT 24 |
Mar 24 01:41:52 PM PDT 24 |
4837682416 ps |
| T931 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3725331165 |
|
|
Mar 24 01:49:15 PM PDT 24 |
Mar 24 01:51:17 PM PDT 24 |
3004291647 ps |
| T932 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2366719423 |
|
|
Mar 24 01:45:53 PM PDT 24 |
Mar 24 01:46:14 PM PDT 24 |
8470188866 ps |
| T933 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2826923766 |
|
|
Mar 24 01:36:04 PM PDT 24 |
Mar 24 01:40:58 PM PDT 24 |
36529164368 ps |
| T934 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.4287511957 |
|
|
Mar 24 01:43:48 PM PDT 24 |
Mar 24 01:44:37 PM PDT 24 |
757519188 ps |
| T935 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1813578679 |
|
|
Mar 24 01:40:34 PM PDT 24 |
Mar 24 01:42:45 PM PDT 24 |
772415565 ps |
| T936 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2600788484 |
|
|
Mar 24 01:40:12 PM PDT 24 |
Mar 24 01:46:09 PM PDT 24 |
23954099467 ps |
| T937 |
/workspace/coverage/default/32.sram_ctrl_executable.2307199104 |
|
|
Mar 24 01:44:34 PM PDT 24 |
Mar 24 01:55:59 PM PDT 24 |
18028931756 ps |
| T938 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.210402344 |
|
|
Mar 24 01:48:32 PM PDT 24 |
Mar 24 01:55:15 PM PDT 24 |
101645222100 ps |
| T939 |
/workspace/coverage/default/9.sram_ctrl_regwen.3983269049 |
|
|
Mar 24 01:37:39 PM PDT 24 |
Mar 24 01:47:43 PM PDT 24 |
10916433500 ps |
| T940 |
/workspace/coverage/default/30.sram_ctrl_stress_all.1788990510 |
|
|
Mar 24 01:44:00 PM PDT 24 |
Mar 24 02:53:10 PM PDT 24 |
121409992536 ps |
| T941 |
/workspace/coverage/default/35.sram_ctrl_alert_test.647257162 |
|
|
Mar 24 01:45:33 PM PDT 24 |
Mar 24 01:45:33 PM PDT 24 |
12371707 ps |
| T942 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.1272777052 |
|
|
Mar 24 01:40:12 PM PDT 24 |
Mar 24 01:42:34 PM PDT 24 |
4355156690 ps |
| T943 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3993187784 |
|
|
Mar 24 01:42:19 PM PDT 24 |
Mar 24 01:45:19 PM PDT 24 |
3339597028 ps |
| T944 |
/workspace/coverage/default/35.sram_ctrl_smoke.3167663200 |
|
|
Mar 24 01:45:11 PM PDT 24 |
Mar 24 01:45:21 PM PDT 24 |
2523751579 ps |
| T91 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1256521652 |
|
|
Mar 24 12:34:29 PM PDT 24 |
Mar 24 12:34:30 PM PDT 24 |
22683816 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2675012650 |
|
|
Mar 24 12:34:25 PM PDT 24 |
Mar 24 12:34:29 PM PDT 24 |
1445240694 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.731635755 |
|
|
Mar 24 12:34:52 PM PDT 24 |
Mar 24 12:34:53 PM PDT 24 |
47039364 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1979779284 |
|
|
Mar 24 12:34:39 PM PDT 24 |
Mar 24 12:34:40 PM PDT 24 |
45208468 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3081597344 |
|
|
Mar 24 12:34:33 PM PDT 24 |
Mar 24 12:34:35 PM PDT 24 |
19780303 ps |
| T134 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1209480762 |
|
|
Mar 24 12:34:17 PM PDT 24 |
Mar 24 12:34:19 PM PDT 24 |
82828844 ps |
| T65 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4000341290 |
|
|
Mar 24 12:34:30 PM PDT 24 |
Mar 24 12:35:27 PM PDT 24 |
7053491584 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1096557692 |
|
|
Mar 24 12:34:25 PM PDT 24 |
Mar 24 12:34:28 PM PDT 24 |
18620448 ps |
| T67 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.816459117 |
|
|
Mar 24 12:34:22 PM PDT 24 |
Mar 24 12:34:23 PM PDT 24 |
16223945 ps |
| T946 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.13287308 |
|
|
Mar 24 12:34:32 PM PDT 24 |
Mar 24 12:34:34 PM PDT 24 |
100855779 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.870426012 |
|
|
Mar 24 12:34:33 PM PDT 24 |
Mar 24 12:34:38 PM PDT 24 |
2024849405 ps |
| T68 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.752389959 |
|
|
Mar 24 12:34:45 PM PDT 24 |
Mar 24 12:35:33 PM PDT 24 |
7397487424 ps |
| T69 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1643900895 |
|
|
Mar 24 12:34:21 PM PDT 24 |
Mar 24 12:35:07 PM PDT 24 |
32055131542 ps |
| T948 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1554554288 |
|
|
Mar 24 12:34:46 PM PDT 24 |
Mar 24 12:34:50 PM PDT 24 |
364821554 ps |
| T102 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3444545168 |
|
|
Mar 24 12:34:18 PM PDT 24 |
Mar 24 12:34:20 PM PDT 24 |
1161077658 ps |
| T70 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.716386364 |
|
|
Mar 24 12:34:23 PM PDT 24 |
Mar 24 12:34:24 PM PDT 24 |
12554971 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3222807759 |
|
|
Mar 24 12:34:36 PM PDT 24 |
Mar 24 12:34:39 PM PDT 24 |
99288369 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2611809820 |
|
|
Mar 24 12:34:12 PM PDT 24 |
Mar 24 12:34:17 PM PDT 24 |
2188138683 ps |
| T951 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.36899086 |
|
|
Mar 24 12:34:27 PM PDT 24 |
Mar 24 12:34:30 PM PDT 24 |
63817273 ps |
| T71 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1086491275 |
|
|
Mar 24 12:34:42 PM PDT 24 |
Mar 24 12:35:35 PM PDT 24 |
44079352403 ps |
| T103 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.547114898 |
|
|
Mar 24 12:34:39 PM PDT 24 |
Mar 24 12:34:41 PM PDT 24 |
133586496 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.249075653 |
|
|
Mar 24 12:34:10 PM PDT 24 |
Mar 24 12:34:15 PM PDT 24 |
294155325 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3012113983 |
|
|
Mar 24 12:34:29 PM PDT 24 |
Mar 24 12:34:33 PM PDT 24 |
39797237 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1572233899 |
|
|
Mar 24 12:34:18 PM PDT 24 |
Mar 24 12:34:19 PM PDT 24 |
62033493 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3840687433 |
|
|
Mar 24 12:34:47 PM PDT 24 |
Mar 24 12:34:49 PM PDT 24 |
20239486 ps |
| T72 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2080858474 |
|
|
Mar 24 12:34:18 PM PDT 24 |
Mar 24 12:35:05 PM PDT 24 |
58610896451 ps |
| T955 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.313560089 |
|
|
Mar 24 12:34:23 PM PDT 24 |
Mar 24 12:34:24 PM PDT 24 |
22166328 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.813120670 |
|
|
Mar 24 12:34:26 PM PDT 24 |
Mar 24 12:35:21 PM PDT 24 |
14107689286 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1659745349 |
|
|
Mar 24 12:34:22 PM PDT 24 |
Mar 24 12:34:24 PM PDT 24 |
860875421 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3703044506 |
|
|
Mar 24 12:35:34 PM PDT 24 |
Mar 24 12:35:35 PM PDT 24 |
96334571 ps |
| T73 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.828629123 |
|
|
Mar 24 12:34:11 PM PDT 24 |
Mar 24 12:34:12 PM PDT 24 |
122947943 ps |
| T74 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2695260767 |
|
|
Mar 24 12:34:34 PM PDT 24 |
Mar 24 12:35:01 PM PDT 24 |
7693825077 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1898786418 |
|
|
Mar 24 12:35:56 PM PDT 24 |
Mar 24 12:35:57 PM PDT 24 |
48136565 ps |
| T76 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.817989905 |
|
|
Mar 24 12:34:27 PM PDT 24 |
Mar 24 12:35:15 PM PDT 24 |
32342403093 ps |
| T77 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2196297678 |
|
|
Mar 24 12:34:28 PM PDT 24 |
Mar 24 12:34:56 PM PDT 24 |
3703699896 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3049073392 |
|
|
Mar 24 12:34:24 PM PDT 24 |
Mar 24 12:34:25 PM PDT 24 |
39458285 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2322173802 |
|
|
Mar 24 12:34:28 PM PDT 24 |
Mar 24 12:34:29 PM PDT 24 |
11714848 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2311316018 |
|
|
Mar 24 12:34:22 PM PDT 24 |
Mar 24 12:35:09 PM PDT 24 |
7410490604 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.92792321 |
|
|
Mar 24 12:34:28 PM PDT 24 |
Mar 24 12:34:56 PM PDT 24 |
73560641055 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3441638471 |
|
|
Mar 24 12:34:34 PM PDT 24 |
Mar 24 12:34:35 PM PDT 24 |
23833659 ps |
| T961 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3749008994 |
|
|
Mar 24 12:34:58 PM PDT 24 |
Mar 24 12:35:04 PM PDT 24 |
1423899966 ps |
| T962 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4211657387 |
|
|
Mar 24 12:35:39 PM PDT 24 |
Mar 24 12:35:42 PM PDT 24 |
279311326 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4026189929 |
|
|
Mar 24 12:34:18 PM PDT 24 |
Mar 24 12:34:19 PM PDT 24 |
34707802 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2567214180 |
|
|
Mar 24 12:34:41 PM PDT 24 |
Mar 24 12:34:46 PM PDT 24 |
136135185 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2357770764 |
|
|
Mar 24 12:34:25 PM PDT 24 |
Mar 24 12:34:29 PM PDT 24 |
33655801 ps |
| T966 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2224697384 |
|
|
Mar 24 12:34:39 PM PDT 24 |
Mar 24 12:34:45 PM PDT 24 |
12014662 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2622895804 |
|
|
Mar 24 12:34:16 PM PDT 24 |
Mar 24 12:34:17 PM PDT 24 |
142615819 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1185620051 |
|
|
Mar 24 12:34:24 PM PDT 24 |
Mar 24 12:34:25 PM PDT 24 |
21200334 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3039453746 |
|
|
Mar 24 12:34:26 PM PDT 24 |
Mar 24 12:34:29 PM PDT 24 |
700704062 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1543408853 |
|
|
Mar 24 12:34:28 PM PDT 24 |
Mar 24 12:34:28 PM PDT 24 |
33714438 ps |
| T971 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.820899110 |
|
|
Mar 24 12:34:45 PM PDT 24 |
Mar 24 12:34:48 PM PDT 24 |
1463918863 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.23770231 |
|
|
Mar 24 12:34:39 PM PDT 24 |
Mar 24 12:35:27 PM PDT 24 |
7334967239 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2818328765 |
|
|
Mar 24 12:34:20 PM PDT 24 |
Mar 24 12:34:21 PM PDT 24 |
18189453 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3157022494 |
|
|
Mar 24 12:34:18 PM PDT 24 |
Mar 24 12:34:19 PM PDT 24 |
75451928 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.286835216 |
|
|
Mar 24 12:34:35 PM PDT 24 |
Mar 24 12:34:39 PM PDT 24 |
141861353 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2933677065 |
|
|
Mar 24 12:34:23 PM PDT 24 |
Mar 24 12:34:25 PM PDT 24 |
649237936 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.289701602 |
|
|
Mar 24 12:34:22 PM PDT 24 |
Mar 24 12:34:25 PM PDT 24 |
361499402 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3102456676 |
|
|
Mar 24 12:34:24 PM PDT 24 |
Mar 24 12:34:25 PM PDT 24 |
26040068 ps |
| T978 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4135869815 |
|
|
Mar 24 12:34:27 PM PDT 24 |
Mar 24 12:34:30 PM PDT 24 |
716135406 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4100583232 |
|
|
Mar 24 12:34:15 PM PDT 24 |
Mar 24 12:35:04 PM PDT 24 |
29351756244 ps |
| T980 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.594352240 |
|
|
Mar 24 12:34:09 PM PDT 24 |
Mar 24 12:34:12 PM PDT 24 |
37024836 ps |
| T128 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2752048033 |
|
|
Mar 24 12:34:29 PM PDT 24 |
Mar 24 12:34:31 PM PDT 24 |
345282861 ps |
| T80 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2147393820 |
|
|
Mar 24 12:34:20 PM PDT 24 |
Mar 24 12:34:21 PM PDT 24 |
23814412 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.142488813 |
|
|
Mar 24 12:34:23 PM PDT 24 |
Mar 24 12:34:23 PM PDT 24 |
16504892 ps |
| T85 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1637514358 |
|
|
Mar 24 12:34:17 PM PDT 24 |
Mar 24 12:34:41 PM PDT 24 |
3930856225 ps |
| T982 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2451770716 |
|
|
Mar 24 12:34:29 PM PDT 24 |
Mar 24 12:34:30 PM PDT 24 |
16049028 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3990141493 |
|
|
Mar 24 12:34:21 PM PDT 24 |
Mar 24 12:34:25 PM PDT 24 |
1206248362 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.395213815 |
|
|
Mar 24 12:34:42 PM PDT 24 |
Mar 24 12:34:43 PM PDT 24 |
31582533 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2931165147 |
|
|
Mar 24 12:34:15 PM PDT 24 |
Mar 24 12:34:18 PM PDT 24 |
149408422 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2736384589 |
|
|
Mar 24 12:34:19 PM PDT 24 |
Mar 24 12:34:20 PM PDT 24 |
26302984 ps |
| T129 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3923890299 |
|
|
Mar 24 12:34:20 PM PDT 24 |
Mar 24 12:34:21 PM PDT 24 |
132707686 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2376209038 |
|
|
Mar 24 12:34:05 PM PDT 24 |
Mar 24 12:34:06 PM PDT 24 |
20530912 ps |
| T987 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1836672537 |
|
|
Mar 24 12:34:24 PM PDT 24 |
Mar 24 12:34:25 PM PDT 24 |
23949157 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.761881575 |
|
|
Mar 24 12:34:32 PM PDT 24 |
Mar 24 12:34:36 PM PDT 24 |
357596279 ps |
| T87 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2445121479 |
|
|
Mar 24 12:34:38 PM PDT 24 |
Mar 24 12:34:39 PM PDT 24 |
17308097 ps |
| T989 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1936911438 |
|
|
Mar 24 12:34:26 PM PDT 24 |
Mar 24 12:34:29 PM PDT 24 |
130967068 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3451155308 |
|
|
Mar 24 12:34:52 PM PDT 24 |
Mar 24 12:34:54 PM PDT 24 |
240561314 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1472423385 |
|
|
Mar 24 12:34:19 PM PDT 24 |
Mar 24 12:34:20 PM PDT 24 |
15343386 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.214609611 |
|
|
Mar 24 12:34:21 PM PDT 24 |
Mar 24 12:34:22 PM PDT 24 |
84127185 ps |
| T123 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1684567593 |
|
|
Mar 24 12:34:29 PM PDT 24 |
Mar 24 12:34:31 PM PDT 24 |
225845881 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2027876889 |
|
|
Mar 24 12:34:21 PM PDT 24 |
Mar 24 12:34:22 PM PDT 24 |
18175329 ps |
| T993 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.558669166 |
|
|
Mar 24 12:34:39 PM PDT 24 |
Mar 24 12:34:43 PM PDT 24 |
3822030155 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2165621852 |
|
|
Mar 24 12:34:07 PM PDT 24 |
Mar 24 12:34:11 PM PDT 24 |
351512487 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.359431503 |
|
|
Mar 24 12:34:33 PM PDT 24 |
Mar 24 12:34:34 PM PDT 24 |
186267156 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1100310274 |
|
|
Mar 24 12:34:46 PM PDT 24 |
Mar 24 12:34:47 PM PDT 24 |
48295037 ps |
| T997 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3642515254 |
|
|
Mar 24 12:34:17 PM PDT 24 |
Mar 24 12:35:06 PM PDT 24 |
7353087741 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.358147538 |
|
|
Mar 24 12:34:22 PM PDT 24 |
Mar 24 12:34:23 PM PDT 24 |
36791561 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2034562573 |
|
|
Mar 24 12:34:17 PM PDT 24 |
Mar 24 12:34:18 PM PDT 24 |
13794178 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3785791328 |
|
|
Mar 24 12:34:15 PM PDT 24 |
Mar 24 12:34:16 PM PDT 24 |
104918403 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2306709239 |
|
|
Mar 24 12:34:31 PM PDT 24 |
Mar 24 12:34:33 PM PDT 24 |
350059717 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.689279179 |
|
|
Mar 24 12:35:04 PM PDT 24 |
Mar 24 12:35:06 PM PDT 24 |
122642542 ps |
| T1002 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.46402510 |
|
|
Mar 24 12:34:20 PM PDT 24 |
Mar 24 12:35:15 PM PDT 24 |
22761422924 ps |
| T1003 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4115844999 |
|
|
Mar 24 12:34:47 PM PDT 24 |
Mar 24 12:34:51 PM PDT 24 |
2325213558 ps |
| T1004 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1931937816 |
|
|
Mar 24 12:34:30 PM PDT 24 |
Mar 24 12:34:31 PM PDT 24 |
46580270 ps |
| T1005 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2174753154 |
|
|
Mar 24 12:34:25 PM PDT 24 |
Mar 24 12:34:28 PM PDT 24 |
93077821 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4267587694 |
|
|
Mar 24 12:34:39 PM PDT 24 |
Mar 24 12:35:26 PM PDT 24 |
7363482896 ps |
| T1006 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.470561440 |
|
|
Mar 24 12:34:35 PM PDT 24 |
Mar 24 12:34:38 PM PDT 24 |
29149333 ps |