Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	322056152	1			T1	393212		T2	7568		T3	288358
instr_valid_dis	288634432	1			T1	393212		T2	7568		T3	288358
instr_en	25874086	1			T15	393006		T20	72446		T8	157012

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9262775	1			T15	95674		T17	57292		T20	94700
sram_ifetch_valid_disable	283641199	1			T1	393212		T2	7568		T3	288358
sram_ifetch_enable	29152178	1			T15	135166		T17	336994		T20	154396

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	322056152	1			T1	393212		T2	7568		T3	288358
hw_debug_en_valid_off	285546699	1			T1	393212		T2	7568		T3	288358
hw_debug_en_on	22434881	1			T15	99432		T17	160070		T20	44262

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	283641199	1			T1	393212		T2	7568		T3	288358
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	272314500	1			T1	393212		T2	7568		T3	288358
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8541140	1			T15	162166		T20	16000		T8	69788
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4094784	1			T17	32446		T20	50694		T26	144590
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1563852	1			T17	32446		T20	38254		T120	126998
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1848824	1			T20	12440		T26	124818		T119	18152
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3303627	1			T15	20638		T17	24846		T26	58946
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1272056	1			T17	24846		T26	58946		T116	21354
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1622084	1			T15	20638		T119	89400		T123	51118
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7601078	1			T15	65936		T17	31884		T20	28252
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3055244	1			T17	31884		T20	21788		T8	131790
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3314762	1			T15	65936		T8	33598		T26	9214

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13037824	1			T15	135166		T8	67224		T26	163032
lc_exec_en	11530176	1			T15	12858		T17	103340		T20	16010
valid_exec_dis	284988251	1			T1	393212		T2	7568		T3	288358
invalid_exec_dis	38414953	1			T15	230840		T17	342723		T20	249096