| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.575093502 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3757424363 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3987456947 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1165742319 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2203589141 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.353766614 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1917419465 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3920944327 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2130753557 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2463570182 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3905824931 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3759975595 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.235508781 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.434752911 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1820296710 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2542390620 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3932343276 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2148692109 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1545632548 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.487938870 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2595702242 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3462677997 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2477851084 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2128136828 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2729954468 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1820260451 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2673166510 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1231900277 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4213898436 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3397171794 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1394085654 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3984314534 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3269305041 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.667062916 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2239550587 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2739882638 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2004938418 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1058453625 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.641222044 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.373970698 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3167042984 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2078298327 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3705410248 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1638362298 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2195053357 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.67102538 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.243467063 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3389699712 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1507815119 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2416518942 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2626245727 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1878573212 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3576748145 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2052580600 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4075697317 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3446344411 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.785848303 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3600300360 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2683710201 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2532208573 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3040805205 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2353570642 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1665450909 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1081297687 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2634019470 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.287069830 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2915147785 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2361379030 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2866660133 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2836321339 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2748295261 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3272940018 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2129022109 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2770367371 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1174300668 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.26292524 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2317271900 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3473400527 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.33641946 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3663922691 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3268239029 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3008004942 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3210157048 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3188558071 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2786904262 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.808753082 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3770936580 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3405088933 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2573573973 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1935011030 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2609420773 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.554406329 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3186451700 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3830022473 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2848615611 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3487259503 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1696888879 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.460249669 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2500170362 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1610194104 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.151817021 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1426789510 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.686569078 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.995453686 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1330756101 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3712152247 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.354048295 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1371182560 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2442447339 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.541644535 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.292048425 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1683510090 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2918103501 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.709782750 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.599287832 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3842971070 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3837465895 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1256607033 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3626112060 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.741430499 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1554345182 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2759085304 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.725993306 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2328346054 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2371351146 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.642663099 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3445823929 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2437064584 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4126038772 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4231301753 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.302879548 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.370731949 |
| /workspace/coverage/default/0.sram_ctrl_bijection.2686983592 |
| /workspace/coverage/default/0.sram_ctrl_executable.1216963499 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.2952140227 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.2343430508 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.480115070 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.3948163818 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.2827606998 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.283459271 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.521099412 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1505238838 |
| /workspace/coverage/default/0.sram_ctrl_regwen.3559457259 |
| /workspace/coverage/default/0.sram_ctrl_smoke.1192426804 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.3852258309 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.873947795 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2906063188 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2446755152 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3808461586 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3365007768 |
| /workspace/coverage/default/1.sram_ctrl_executable.1628411481 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.2262841203 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1268610243 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1252361015 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.3552416024 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2205591006 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1295110112 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2745312294 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.768042054 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3741019737 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.3923066928 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3829124558 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1996926446 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4285697519 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3432249438 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.4155224101 |
| /workspace/coverage/default/10.sram_ctrl_bijection.183572061 |
| /workspace/coverage/default/10.sram_ctrl_executable.313738223 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.1469563175 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.1452255280 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.602588106 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.874393586 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1743101897 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2601818978 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3670197962 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.2355698471 |
| /workspace/coverage/default/10.sram_ctrl_regwen.4164643298 |
| /workspace/coverage/default/10.sram_ctrl_smoke.3166239988 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4256378287 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3032665145 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3460977716 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3705801494 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.913275794 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1378080301 |
| /workspace/coverage/default/11.sram_ctrl_executable.2195707033 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.2473389640 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2012997114 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2456779669 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.929780526 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2375419065 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1108690084 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3522358987 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2672247485 |
| /workspace/coverage/default/11.sram_ctrl_smoke.2334688793 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3292131545 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.668879638 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3709768682 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2698402718 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3781259767 |
| /workspace/coverage/default/12.sram_ctrl_bijection.3951810527 |
| /workspace/coverage/default/12.sram_ctrl_executable.3977134910 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.1282562025 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.1463413566 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1259081627 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.770434049 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3595477902 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.563471472 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1426509997 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.1028332712 |
| /workspace/coverage/default/12.sram_ctrl_regwen.270328272 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1060453705 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.4091828983 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3085248299 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1103806599 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.633388861 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.212508111 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.4211581177 |
| /workspace/coverage/default/13.sram_ctrl_bijection.3187836040 |
| /workspace/coverage/default/13.sram_ctrl_executable.1553994624 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.2957186642 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.537227597 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.4222186444 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.400058086 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.886356479 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.239324372 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3489965780 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.2728973841 |
| /workspace/coverage/default/13.sram_ctrl_regwen.1112169448 |
| /workspace/coverage/default/13.sram_ctrl_smoke.3294320603 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.2858481012 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.740717888 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2271088406 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3816412597 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3254218423 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.3327257750 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2247701034 |
| /workspace/coverage/default/14.sram_ctrl_executable.196562652 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.357321403 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.4181640759 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2168334115 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3401193681 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.4075078566 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.1369825228 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2828202965 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.2991385628 |
| /workspace/coverage/default/14.sram_ctrl_regwen.3362950192 |
| /workspace/coverage/default/14.sram_ctrl_smoke.3784619463 |
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| /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2068757072 |
| /workspace/coverage/default/42.sram_ctrl_ram_cfg.589352011 |
| /workspace/coverage/default/42.sram_ctrl_regwen.3328739784 |
| /workspace/coverage/default/42.sram_ctrl_smoke.4280832640 |
| /workspace/coverage/default/42.sram_ctrl_stress_all.2131324618 |
| /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3342460568 |
| /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2187768477 |
| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3869817338 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3345257343 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.4286442155 |
| /workspace/coverage/default/43.sram_ctrl_bijection.1747521614 |
| /workspace/coverage/default/43.sram_ctrl_executable.4171658301 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.1285891723 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3180148585 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.1791969371 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.2516002010 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.423131033 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1297810202 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.2697990287 |
| /workspace/coverage/default/43.sram_ctrl_regwen.2461226412 |
| /workspace/coverage/default/43.sram_ctrl_smoke.1312100738 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.4118183999 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2016074873 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.306897513 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.245053006 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1541768249 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.2107362492 |
| /workspace/coverage/default/44.sram_ctrl_bijection.2218906283 |
| /workspace/coverage/default/44.sram_ctrl_executable.91757231 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3992450728 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.316321683 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.696675000 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.3805902848 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1951308202 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.1582933232 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3807268172 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.3940347547 |
| /workspace/coverage/default/44.sram_ctrl_regwen.538651242 |
| /workspace/coverage/default/44.sram_ctrl_smoke.3961715869 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.2242428077 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1661006008 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1913159428 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3000894329 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1241611835 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1788666084 |
| /workspace/coverage/default/45.sram_ctrl_bijection.2088423379 |
| /workspace/coverage/default/45.sram_ctrl_executable.835582004 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.4272692799 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2308370463 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2963253292 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.3058257063 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.2643334975 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.3517705009 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.4098259375 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2789688873 |
| /workspace/coverage/default/45.sram_ctrl_regwen.4289609138 |
| /workspace/coverage/default/45.sram_ctrl_smoke.3575067120 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.3832577221 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1121044345 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1707844215 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.669382873 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3327565066 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.1869993348 |
| /workspace/coverage/default/46.sram_ctrl_bijection.2448583425 |
| /workspace/coverage/default/46.sram_ctrl_executable.2667715691 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.2417983241 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.1232972866 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.528366999 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.876027482 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.3241224198 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.579529921 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4169441364 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.422641767 |
| /workspace/coverage/default/46.sram_ctrl_regwen.1956366075 |
| /workspace/coverage/default/46.sram_ctrl_smoke.2659930487 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.1403801692 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3018777096 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3352791500 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2193881798 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3899160095 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.2779075468 |
| /workspace/coverage/default/47.sram_ctrl_bijection.2894234311 |
| /workspace/coverage/default/47.sram_ctrl_executable.3482215304 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.3646600830 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.2406439399 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3442212093 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.392851196 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.2257115933 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.642977765 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3141346446 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.171038852 |
| /workspace/coverage/default/47.sram_ctrl_regwen.138383724 |
| /workspace/coverage/default/47.sram_ctrl_smoke.3313525577 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.650744238 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2587237554 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2053848977 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2635543679 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.3829623876 |
| /workspace/coverage/default/48.sram_ctrl_bijection.1205848011 |
| /workspace/coverage/default/48.sram_ctrl_executable.2694385005 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.1742104956 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.3999309714 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2557921877 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.648388865 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2721646240 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.1637117422 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3899035055 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2932323773 |
| /workspace/coverage/default/48.sram_ctrl_regwen.2177663266 |
| /workspace/coverage/default/48.sram_ctrl_smoke.304964316 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.683020881 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.564844101 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.49986253 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3011903917 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2542878224 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.4187707819 |
| /workspace/coverage/default/49.sram_ctrl_bijection.2685593079 |
| /workspace/coverage/default/49.sram_ctrl_executable.337912612 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3715179050 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.291480602 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1312639049 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.2541194267 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.1723114075 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2489580856 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.376016605 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.857128855 |
| /workspace/coverage/default/49.sram_ctrl_regwen.4079984081 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1781101232 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.870193732 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2803411538 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.4199151598 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.674255143 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3910497740 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.1039740490 |
| /workspace/coverage/default/5.sram_ctrl_bijection.3910649446 |
| /workspace/coverage/default/5.sram_ctrl_executable.1110859949 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3812015029 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2892560483 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3703583850 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.321181119 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2261946062 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2348191514 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4254448146 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.2120542149 |
| /workspace/coverage/default/5.sram_ctrl_regwen.582995629 |
| /workspace/coverage/default/5.sram_ctrl_smoke.1678338466 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.2962571401 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2903587347 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2126759784 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.399578203 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.2018580106 |
| /workspace/coverage/default/6.sram_ctrl_bijection.3906486938 |
| /workspace/coverage/default/6.sram_ctrl_executable.2860657124 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2842919258 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.3512941837 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.657237276 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.4232606258 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.2057806192 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.3241514786 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.942457949 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.3628559467 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3388455286 |
| /workspace/coverage/default/6.sram_ctrl_smoke.3684589710 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.221276595 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2159792510 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2247000679 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1680502594 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2441820519 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.4184834318 |
| /workspace/coverage/default/7.sram_ctrl_bijection.114974880 |
| /workspace/coverage/default/7.sram_ctrl_executable.3680896432 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.3623307628 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.1084064829 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.184770705 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.1355832911 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.252945399 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.623896435 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.806534391 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.312383334 |
| /workspace/coverage/default/7.sram_ctrl_regwen.1653822618 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1732289039 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.807749384 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3662808176 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1125906408 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3136768936 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.850567569 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1796885623 |
| /workspace/coverage/default/8.sram_ctrl_executable.448322358 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.1554183278 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.1281220216 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.874433401 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1217434314 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2674273998 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3384724985 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1901911320 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2646911173 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1021079088 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2489024894 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.3927429615 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3585475857 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2352394738 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3454740064 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3775451170 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.2314207257 |
| /workspace/coverage/default/9.sram_ctrl_bijection.1440509078 |
| /workspace/coverage/default/9.sram_ctrl_executable.3845420593 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.1488971659 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.368537862 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1875561979 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3306274289 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3862573114 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.1835948365 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1169319931 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.258110213 |
| /workspace/coverage/default/9.sram_ctrl_regwen.1696985511 |
| /workspace/coverage/default/9.sram_ctrl_smoke.346979006 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3939407499 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1099788237 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2544569559 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2052341050 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.876027482 |
|
|
Mar 26 01:07:54 PM PDT 24 |
Mar 26 01:11:56 PM PDT 24 |
3942771496 ps |
| T2 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.4215121981 |
|
|
Mar 26 01:07:17 PM PDT 24 |
Mar 26 01:08:45 PM PDT 24 |
92417140516 ps |
| T3 |
/workspace/coverage/default/16.sram_ctrl_bijection.266956739 |
|
|
Mar 26 01:01:14 PM PDT 24 |
Mar 26 01:42:17 PM PDT 24 |
192031277490 ps |
| T4 |
/workspace/coverage/default/23.sram_ctrl_smoke.2559360223 |
|
|
Mar 26 01:02:43 PM PDT 24 |
Mar 26 01:02:54 PM PDT 24 |
8009606564 ps |
| T5 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.633388861 |
|
|
Mar 26 01:00:18 PM PDT 24 |
Mar 26 01:00:31 PM PDT 24 |
2658309469 ps |
| T12 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3829623876 |
|
|
Mar 26 01:08:35 PM PDT 24 |
Mar 26 01:08:36 PM PDT 24 |
15133379 ps |
| T6 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1136982319 |
|
|
Mar 26 01:01:57 PM PDT 24 |
Mar 26 01:04:25 PM PDT 24 |
19904340557 ps |
| T13 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3306274289 |
|
|
Mar 26 12:59:42 PM PDT 24 |
Mar 26 01:01:45 PM PDT 24 |
1980301437 ps |
| T7 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3546556259 |
|
|
Mar 26 01:06:48 PM PDT 24 |
Mar 26 01:24:04 PM PDT 24 |
76953237110 ps |
| T14 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2236834277 |
|
|
Mar 26 12:58:35 PM PDT 24 |
Mar 26 12:58:36 PM PDT 24 |
34730917 ps |
| T16 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3079111945 |
|
|
Mar 26 01:06:50 PM PDT 24 |
Mar 26 01:09:34 PM PDT 24 |
111904701151 ps |
| T15 |
/workspace/coverage/default/42.sram_ctrl_regwen.3328739784 |
|
|
Mar 26 01:07:05 PM PDT 24 |
Mar 26 01:22:23 PM PDT 24 |
21189789914 ps |
| T17 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1108047816 |
|
|
Mar 26 01:08:20 PM PDT 24 |
Mar 26 02:16:15 PM PDT 24 |
664599281330 ps |
| T18 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1913159428 |
|
|
Mar 26 01:07:29 PM PDT 24 |
Mar 26 01:10:28 PM PDT 24 |
6218549283 ps |
| T19 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2212300846 |
|
|
Mar 26 12:59:04 PM PDT 24 |
Mar 26 12:59:37 PM PDT 24 |
1192500977 ps |
| T20 |
/workspace/coverage/default/8.sram_ctrl_executable.448322358 |
|
|
Mar 26 12:59:35 PM PDT 24 |
Mar 26 01:18:10 PM PDT 24 |
67386057276 ps |
| T10 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2696871889 |
|
|
Mar 26 12:58:48 PM PDT 24 |
Mar 26 12:58:51 PM PDT 24 |
568574246 ps |
| T35 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3457978256 |
|
|
Mar 26 01:01:15 PM PDT 24 |
Mar 26 01:01:21 PM PDT 24 |
1283596208 ps |
| T36 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1686523394 |
|
|
Mar 26 12:58:37 PM PDT 24 |
Mar 26 12:58:49 PM PDT 24 |
3160435781 ps |
| T11 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.830097667 |
|
|
Mar 26 12:58:25 PM PDT 24 |
Mar 26 12:58:28 PM PDT 24 |
950588687 ps |
| T37 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3867925998 |
|
|
Mar 26 12:58:51 PM PDT 24 |
Mar 26 01:00:25 PM PDT 24 |
792428589 ps |
| T38 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.691568405 |
|
|
Mar 26 01:03:20 PM PDT 24 |
Mar 26 01:04:43 PM PDT 24 |
4956040213 ps |
| T8 |
/workspace/coverage/default/48.sram_ctrl_stress_all.683020881 |
|
|
Mar 26 01:08:32 PM PDT 24 |
Mar 26 03:02:03 PM PDT 24 |
1124793584769 ps |
| T9 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.3051424961 |
|
|
Mar 26 01:03:51 PM PDT 24 |
Mar 26 01:04:21 PM PDT 24 |
48191951769 ps |
| T28 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.564844101 |
|
|
Mar 26 01:08:33 PM PDT 24 |
Mar 26 01:09:52 PM PDT 24 |
3710167136 ps |
| T24 |
/workspace/coverage/default/32.sram_ctrl_alert_test.884882267 |
|
|
Mar 26 01:04:34 PM PDT 24 |
Mar 26 01:04:35 PM PDT 24 |
48446688 ps |
| T130 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2114414571 |
|
|
Mar 26 01:01:44 PM PDT 24 |
Mar 26 01:01:45 PM PDT 24 |
31366248 ps |
| T60 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1535454777 |
|
|
Mar 26 01:02:12 PM PDT 24 |
Mar 26 01:19:50 PM PDT 24 |
30260104612 ps |
| T125 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1812409368 |
|
|
Mar 26 01:02:58 PM PDT 24 |
Mar 26 01:14:41 PM PDT 24 |
9535734167 ps |
| T39 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.444493848 |
|
|
Mar 26 12:58:37 PM PDT 24 |
Mar 26 01:03:19 PM PDT 24 |
21004226917 ps |
| T131 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.321181119 |
|
|
Mar 26 12:58:58 PM PDT 24 |
Mar 26 01:01:42 PM PDT 24 |
14364192468 ps |
| T48 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.361011773 |
|
|
Mar 26 01:05:35 PM PDT 24 |
Mar 26 01:05:50 PM PDT 24 |
2421278176 ps |
| T27 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3976956114 |
|
|
Mar 26 01:07:03 PM PDT 24 |
Mar 26 01:08:15 PM PDT 24 |
30240881027 ps |
| T40 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3276938704 |
|
|
Mar 26 01:01:18 PM PDT 24 |
Mar 26 01:03:57 PM PDT 24 |
5989858006 ps |
| T21 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2419419679 |
|
|
Mar 26 01:02:24 PM PDT 24 |
Mar 26 01:10:14 PM PDT 24 |
34349713032 ps |
| T128 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.85086519 |
|
|
Mar 26 01:06:19 PM PDT 24 |
Mar 26 01:06:48 PM PDT 24 |
760180812 ps |
| T85 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.5188584 |
|
|
Mar 26 01:01:01 PM PDT 24 |
Mar 26 01:05:54 PM PDT 24 |
34028470209 ps |
| T49 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.321304392 |
|
|
Mar 26 01:03:11 PM PDT 24 |
Mar 26 01:04:06 PM PDT 24 |
19470416428 ps |
| T132 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2135123448 |
|
|
Mar 26 01:01:57 PM PDT 24 |
Mar 26 01:02:56 PM PDT 24 |
730841737 ps |
| T133 |
/workspace/coverage/default/12.sram_ctrl_smoke.1060453705 |
|
|
Mar 26 01:00:18 PM PDT 24 |
Mar 26 01:00:29 PM PDT 24 |
782636622 ps |
| T99 |
/workspace/coverage/default/1.sram_ctrl_regwen.2882673979 |
|
|
Mar 26 12:58:25 PM PDT 24 |
Mar 26 01:04:00 PM PDT 24 |
7313629932 ps |
| T134 |
/workspace/coverage/default/23.sram_ctrl_partial_access.680976335 |
|
|
Mar 26 01:02:42 PM PDT 24 |
Mar 26 01:02:53 PM PDT 24 |
704947586 ps |
| T30 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3844807796 |
|
|
Mar 26 12:58:24 PM PDT 24 |
Mar 26 12:58:28 PM PDT 24 |
2592834172 ps |
| T86 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1191200864 |
|
|
Mar 26 01:05:22 PM PDT 24 |
Mar 26 01:10:40 PM PDT 24 |
14455040388 ps |
| T87 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3670197962 |
|
|
Mar 26 12:59:55 PM PDT 24 |
Mar 26 01:04:02 PM PDT 24 |
39293287268 ps |
| T129 |
/workspace/coverage/default/34.sram_ctrl_smoke.3892696367 |
|
|
Mar 26 01:04:52 PM PDT 24 |
Mar 26 01:05:02 PM PDT 24 |
936944765 ps |
| T135 |
/workspace/coverage/default/38.sram_ctrl_alert_test.2005835150 |
|
|
Mar 26 01:06:04 PM PDT 24 |
Mar 26 01:06:05 PM PDT 24 |
17942957 ps |
| T126 |
/workspace/coverage/default/48.sram_ctrl_bijection.1205848011 |
|
|
Mar 26 01:08:19 PM PDT 24 |
Mar 26 01:22:16 PM PDT 24 |
127755881585 ps |
| T136 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2617673161 |
|
|
Mar 26 01:02:54 PM PDT 24 |
Mar 26 01:08:28 PM PDT 24 |
137590554464 ps |
| T88 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2081583671 |
|
|
Mar 26 01:03:52 PM PDT 24 |
Mar 26 01:09:41 PM PDT 24 |
32648160613 ps |
| T137 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2369440526 |
|
|
Mar 26 01:01:30 PM PDT 24 |
Mar 26 01:02:19 PM PDT 24 |
757566403 ps |
| T138 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3805902848 |
|
|
Mar 26 01:07:45 PM PDT 24 |
Mar 26 01:12:11 PM PDT 24 |
13939112641 ps |
| T22 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.912490196 |
|
|
Mar 26 12:58:11 PM PDT 24 |
Mar 26 01:14:04 PM PDT 24 |
27720345247 ps |
| T127 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1509537197 |
|
|
Mar 26 01:02:26 PM PDT 24 |
Mar 26 01:02:40 PM PDT 24 |
1400177245 ps |
| T139 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2354411879 |
|
|
Mar 26 01:01:30 PM PDT 24 |
Mar 26 01:18:05 PM PDT 24 |
64719518267 ps |
| T140 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.669382873 |
|
|
Mar 26 01:07:43 PM PDT 24 |
Mar 26 01:08:00 PM PDT 24 |
2932502252 ps |
| T26 |
/workspace/coverage/default/10.sram_ctrl_stress_all.212305129 |
|
|
Mar 26 01:00:06 PM PDT 24 |
Mar 26 02:00:28 PM PDT 24 |
271352412892 ps |
| T141 |
/workspace/coverage/default/19.sram_ctrl_smoke.485467589 |
|
|
Mar 26 01:01:48 PM PDT 24 |
Mar 26 01:04:23 PM PDT 24 |
2092931590 ps |
| T89 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3530805679 |
|
|
Mar 26 01:01:58 PM PDT 24 |
Mar 26 01:03:49 PM PDT 24 |
22945255960 ps |
| T142 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.4174124298 |
|
|
Mar 26 01:04:11 PM PDT 24 |
Mar 26 01:05:16 PM PDT 24 |
737260094 ps |
| T31 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2356785371 |
|
|
Mar 26 01:06:03 PM PDT 24 |
Mar 26 01:06:07 PM PDT 24 |
362576528 ps |
| T119 |
/workspace/coverage/default/45.sram_ctrl_regwen.4289609138 |
|
|
Mar 26 01:07:42 PM PDT 24 |
Mar 26 01:18:57 PM PDT 24 |
46835266663 ps |
| T32 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.4045028995 |
|
|
Mar 26 01:04:13 PM PDT 24 |
Mar 26 01:04:17 PM PDT 24 |
1344101938 ps |
| T90 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.743494303 |
|
|
Mar 26 01:06:05 PM PDT 24 |
Mar 26 01:14:04 PM PDT 24 |
64757165243 ps |
| T143 |
/workspace/coverage/default/38.sram_ctrl_bijection.501629609 |
|
|
Mar 26 01:05:54 PM PDT 24 |
Mar 26 01:26:29 PM PDT 24 |
79206170579 ps |
| T144 |
/workspace/coverage/default/30.sram_ctrl_bijection.2447784784 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:12:09 PM PDT 24 |
7182918626 ps |
| T120 |
/workspace/coverage/default/12.sram_ctrl_regwen.270328272 |
|
|
Mar 26 01:00:29 PM PDT 24 |
Mar 26 01:20:23 PM PDT 24 |
80032627550 ps |
| T29 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1661006008 |
|
|
Mar 26 01:07:42 PM PDT 24 |
Mar 26 01:11:17 PM PDT 24 |
8325794023 ps |
| T93 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1835948365 |
|
|
Mar 26 12:59:42 PM PDT 24 |
Mar 26 12:59:55 PM PDT 24 |
1298886496 ps |
| T41 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4278419566 |
|
|
Mar 26 01:01:46 PM PDT 24 |
Mar 26 01:02:05 PM PDT 24 |
1351338691 ps |
| T23 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.139307833 |
|
|
Mar 26 01:03:52 PM PDT 24 |
Mar 26 01:18:29 PM PDT 24 |
13655650666 ps |
| T94 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1791969371 |
|
|
Mar 26 01:07:18 PM PDT 24 |
Mar 26 01:12:33 PM PDT 24 |
21521123280 ps |
| T91 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.668879638 |
|
|
Mar 26 01:00:05 PM PDT 24 |
Mar 26 01:02:56 PM PDT 24 |
17423082356 ps |
| T95 |
/workspace/coverage/default/46.sram_ctrl_executable.2667715691 |
|
|
Mar 26 01:07:54 PM PDT 24 |
Mar 26 01:08:10 PM PDT 24 |
538352887 ps |
| T42 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.650744238 |
|
|
Mar 26 01:08:21 PM PDT 24 |
Mar 26 01:11:06 PM PDT 24 |
4948427589 ps |
| T96 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2534796662 |
|
|
Mar 26 01:02:10 PM PDT 24 |
Mar 26 01:02:42 PM PDT 24 |
2826743229 ps |
| T97 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2241037658 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:06:02 PM PDT 24 |
3817898364 ps |
| T145 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.4231666375 |
|
|
Mar 26 01:02:30 PM PDT 24 |
Mar 26 01:05:00 PM PDT 24 |
22257787930 ps |
| T115 |
/workspace/coverage/default/37.sram_ctrl_regwen.2001962352 |
|
|
Mar 26 01:05:55 PM PDT 24 |
Mar 26 01:10:40 PM PDT 24 |
21122119376 ps |
| T146 |
/workspace/coverage/default/41.sram_ctrl_bijection.2039303824 |
|
|
Mar 26 01:06:50 PM PDT 24 |
Mar 26 01:52:10 PM PDT 24 |
165814405745 ps |
| T147 |
/workspace/coverage/default/36.sram_ctrl_bijection.1889459561 |
|
|
Mar 26 01:05:21 PM PDT 24 |
Mar 26 01:22:03 PM PDT 24 |
14760082527 ps |
| T148 |
/workspace/coverage/default/35.sram_ctrl_smoke.2984704241 |
|
|
Mar 26 01:05:08 PM PDT 24 |
Mar 26 01:05:23 PM PDT 24 |
8709247769 ps |
| T92 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2247000679 |
|
|
Mar 26 12:59:14 PM PDT 24 |
Mar 26 01:04:29 PM PDT 24 |
11436739218 ps |
| T149 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3753983200 |
|
|
Mar 26 01:06:33 PM PDT 24 |
Mar 26 01:07:07 PM PDT 24 |
7102565236 ps |
| T150 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2403510268 |
|
|
Mar 26 01:02:24 PM PDT 24 |
Mar 26 01:04:45 PM PDT 24 |
9919664437 ps |
| T151 |
/workspace/coverage/default/45.sram_ctrl_bijection.2088423379 |
|
|
Mar 26 01:07:28 PM PDT 24 |
Mar 26 01:33:36 PM PDT 24 |
22631506030 ps |
| T152 |
/workspace/coverage/default/43.sram_ctrl_partial_access.423131033 |
|
|
Mar 26 01:07:18 PM PDT 24 |
Mar 26 01:07:42 PM PDT 24 |
5247385287 ps |
| T153 |
/workspace/coverage/default/15.sram_ctrl_bijection.1828651858 |
|
|
Mar 26 01:01:16 PM PDT 24 |
Mar 26 01:15:47 PM PDT 24 |
75833053793 ps |
| T154 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3058257063 |
|
|
Mar 26 01:07:43 PM PDT 24 |
Mar 26 01:12:28 PM PDT 24 |
13758539888 ps |
| T68 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3883305283 |
|
|
Mar 26 01:06:49 PM PDT 24 |
Mar 26 01:28:46 PM PDT 24 |
32754304306 ps |
| T155 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1877512587 |
|
|
Mar 26 01:04:13 PM PDT 24 |
Mar 26 01:04:14 PM PDT 24 |
39090492 ps |
| T156 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1713986028 |
|
|
Mar 26 01:04:24 PM PDT 24 |
Mar 26 01:09:22 PM PDT 24 |
27220489852 ps |
| T157 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.4089571493 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:04:16 PM PDT 24 |
1406759033 ps |
| T158 |
/workspace/coverage/default/4.sram_ctrl_bijection.533118601 |
|
|
Mar 26 12:58:47 PM PDT 24 |
Mar 26 01:22:53 PM PDT 24 |
85279293321 ps |
| T69 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2456779669 |
|
|
Mar 26 01:00:17 PM PDT 24 |
Mar 26 01:02:34 PM PDT 24 |
3205793966 ps |
| T159 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4276089262 |
|
|
Mar 26 01:06:18 PM PDT 24 |
Mar 26 01:11:55 PM PDT 24 |
19976799976 ps |
| T160 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2068757072 |
|
|
Mar 26 01:07:05 PM PDT 24 |
Mar 26 01:14:27 PM PDT 24 |
45253215996 ps |
| T116 |
/workspace/coverage/default/48.sram_ctrl_regwen.2177663266 |
|
|
Mar 26 01:08:32 PM PDT 24 |
Mar 26 01:17:39 PM PDT 24 |
9869881422 ps |
| T161 |
/workspace/coverage/default/39.sram_ctrl_bijection.3814487380 |
|
|
Mar 26 01:06:03 PM PDT 24 |
Mar 26 01:38:04 PM PDT 24 |
29262607205 ps |
| T70 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2895090931 |
|
|
Mar 26 01:02:10 PM PDT 24 |
Mar 26 01:18:41 PM PDT 24 |
14084942587 ps |
| T162 |
/workspace/coverage/default/28.sram_ctrl_executable.2157855624 |
|
|
Mar 26 01:03:51 PM PDT 24 |
Mar 26 01:11:17 PM PDT 24 |
7902910358 ps |
| T163 |
/workspace/coverage/default/31.sram_ctrl_smoke.3207680728 |
|
|
Mar 26 01:04:21 PM PDT 24 |
Mar 26 01:04:30 PM PDT 24 |
2877218889 ps |
| T164 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.934193408 |
|
|
Mar 26 01:02:13 PM PDT 24 |
Mar 26 01:03:01 PM PDT 24 |
14532158562 ps |
| T71 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1803176496 |
|
|
Mar 26 01:06:04 PM PDT 24 |
Mar 26 01:08:56 PM PDT 24 |
2476324861 ps |
| T165 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.456176764 |
|
|
Mar 26 01:04:38 PM PDT 24 |
Mar 26 01:07:08 PM PDT 24 |
7654537871 ps |
| T166 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3494963128 |
|
|
Mar 26 12:58:50 PM PDT 24 |
Mar 26 01:05:31 PM PDT 24 |
18785697016 ps |
| T167 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4073343889 |
|
|
Mar 26 01:03:05 PM PDT 24 |
Mar 26 01:05:51 PM PDT 24 |
812935715 ps |
| T168 |
/workspace/coverage/default/49.sram_ctrl_regwen.4079984081 |
|
|
Mar 26 01:08:46 PM PDT 24 |
Mar 26 01:18:32 PM PDT 24 |
3136402344 ps |
| T169 |
/workspace/coverage/default/27.sram_ctrl_partial_access.3823638840 |
|
|
Mar 26 01:03:19 PM PDT 24 |
Mar 26 01:04:12 PM PDT 24 |
1146851152 ps |
| T123 |
/workspace/coverage/default/45.sram_ctrl_executable.835582004 |
|
|
Mar 26 01:07:42 PM PDT 24 |
Mar 26 01:37:17 PM PDT 24 |
18401375536 ps |
| T170 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2339093123 |
|
|
Mar 26 01:02:26 PM PDT 24 |
Mar 26 01:02:29 PM PDT 24 |
1252511101 ps |
| T124 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3927429615 |
|
|
Mar 26 12:59:31 PM PDT 24 |
Mar 26 02:03:47 PM PDT 24 |
319586235996 ps |
| T171 |
/workspace/coverage/default/6.sram_ctrl_stress_all.221276595 |
|
|
Mar 26 12:59:10 PM PDT 24 |
Mar 26 01:17:03 PM PDT 24 |
31752486018 ps |
| T172 |
/workspace/coverage/default/35.sram_ctrl_executable.4134028425 |
|
|
Mar 26 01:05:21 PM PDT 24 |
Mar 26 01:24:34 PM PDT 24 |
16689823871 ps |
| T173 |
/workspace/coverage/default/3.sram_ctrl_executable.3981962458 |
|
|
Mar 26 12:58:49 PM PDT 24 |
Mar 26 01:22:56 PM PDT 24 |
45578361607 ps |
| T174 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.2554519081 |
|
|
Mar 26 12:58:37 PM PDT 24 |
Mar 26 12:58:41 PM PDT 24 |
1863369896 ps |
| T118 |
/workspace/coverage/default/39.sram_ctrl_executable.835298539 |
|
|
Mar 26 01:06:20 PM PDT 24 |
Mar 26 01:25:34 PM PDT 24 |
290428122190 ps |
| T175 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2052341050 |
|
|
Mar 26 12:59:43 PM PDT 24 |
Mar 26 12:59:50 PM PDT 24 |
676548923 ps |
| T176 |
/workspace/coverage/default/20.sram_ctrl_smoke.119554919 |
|
|
Mar 26 01:01:58 PM PDT 24 |
Mar 26 01:02:24 PM PDT 24 |
10773538819 ps |
| T177 |
/workspace/coverage/default/23.sram_ctrl_regwen.1116296585 |
|
|
Mar 26 01:02:42 PM PDT 24 |
Mar 26 01:05:11 PM PDT 24 |
5744622682 ps |
| T117 |
/workspace/coverage/default/12.sram_ctrl_executable.3977134910 |
|
|
Mar 26 01:00:29 PM PDT 24 |
Mar 26 01:06:07 PM PDT 24 |
11308141302 ps |
| T178 |
/workspace/coverage/default/31.sram_ctrl_regwen.1224918072 |
|
|
Mar 26 01:04:22 PM PDT 24 |
Mar 26 01:29:13 PM PDT 24 |
110871758071 ps |
| T179 |
/workspace/coverage/default/26.sram_ctrl_regwen.257121704 |
|
|
Mar 26 01:03:05 PM PDT 24 |
Mar 26 01:24:05 PM PDT 24 |
22176715740 ps |
| T180 |
/workspace/coverage/default/28.sram_ctrl_smoke.1140232490 |
|
|
Mar 26 01:03:33 PM PDT 24 |
Mar 26 01:05:42 PM PDT 24 |
782698821 ps |
| T181 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2577325919 |
|
|
Mar 26 01:02:10 PM PDT 24 |
Mar 26 01:04:55 PM PDT 24 |
11414654521 ps |
| T78 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1015573483 |
|
|
Mar 26 01:02:11 PM PDT 24 |
Mar 26 01:03:18 PM PDT 24 |
3494465243 ps |
| T79 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.2492555872 |
|
|
Mar 26 01:02:24 PM PDT 24 |
Mar 26 01:04:32 PM PDT 24 |
1600989384 ps |
| T182 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2789688873 |
|
|
Mar 26 01:07:43 PM PDT 24 |
Mar 26 01:07:46 PM PDT 24 |
352959932 ps |
| T183 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3454740064 |
|
|
Mar 26 12:59:35 PM PDT 24 |
Mar 26 01:01:46 PM PDT 24 |
780839937 ps |
| T80 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2542878224 |
|
|
Mar 26 01:08:52 PM PDT 24 |
Mar 26 01:23:40 PM PDT 24 |
14950431074 ps |
| T184 |
/workspace/coverage/default/12.sram_ctrl_bijection.3951810527 |
|
|
Mar 26 01:00:21 PM PDT 24 |
Mar 26 01:32:30 PM PDT 24 |
518329869321 ps |
| T185 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2587237554 |
|
|
Mar 26 01:08:07 PM PDT 24 |
Mar 26 01:11:23 PM PDT 24 |
47299131803 ps |
| T186 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3775451170 |
|
|
Mar 26 12:59:46 PM PDT 24 |
Mar 26 01:23:23 PM PDT 24 |
17436261864 ps |
| T187 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3535373255 |
|
|
Mar 26 01:05:48 PM PDT 24 |
Mar 26 01:07:50 PM PDT 24 |
3239361939 ps |
| T188 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.975410170 |
|
|
Mar 26 01:03:13 PM PDT 24 |
Mar 26 01:16:08 PM PDT 24 |
13149309419 ps |
| T189 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3403734005 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:21:22 PM PDT 24 |
19383901742 ps |
| T190 |
/workspace/coverage/default/7.sram_ctrl_bijection.114974880 |
|
|
Mar 26 12:59:22 PM PDT 24 |
Mar 26 01:29:27 PM PDT 24 |
25246681251 ps |
| T191 |
/workspace/coverage/default/8.sram_ctrl_smoke.2489024894 |
|
|
Mar 26 12:59:22 PM PDT 24 |
Mar 26 01:01:06 PM PDT 24 |
3143144034 ps |
| T192 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.392851196 |
|
|
Mar 26 01:08:07 PM PDT 24 |
Mar 26 01:10:25 PM PDT 24 |
27529525550 ps |
| T193 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3523121106 |
|
|
Mar 26 01:03:07 PM PDT 24 |
Mar 26 01:03:55 PM PDT 24 |
758299735 ps |
| T194 |
/workspace/coverage/default/46.sram_ctrl_bijection.2448583425 |
|
|
Mar 26 01:07:56 PM PDT 24 |
Mar 26 01:18:18 PM PDT 24 |
116120147772 ps |
| T195 |
/workspace/coverage/default/42.sram_ctrl_partial_access.1997214545 |
|
|
Mar 26 01:07:06 PM PDT 24 |
Mar 26 01:07:21 PM PDT 24 |
1093109701 ps |
| T121 |
/workspace/coverage/default/7.sram_ctrl_stress_all.807749384 |
|
|
Mar 26 12:59:20 PM PDT 24 |
Mar 26 03:01:24 PM PDT 24 |
1025303803696 ps |
| T196 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.624609914 |
|
|
Mar 26 01:04:22 PM PDT 24 |
Mar 26 01:23:27 PM PDT 24 |
39127852813 ps |
| T197 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1995048990 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:08:44 PM PDT 24 |
4955338486 ps |
| T198 |
/workspace/coverage/default/28.sram_ctrl_stress_all.426456212 |
|
|
Mar 26 01:03:51 PM PDT 24 |
Mar 26 02:40:38 PM PDT 24 |
475571376592 ps |
| T199 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3807268172 |
|
|
Mar 26 01:07:28 PM PDT 24 |
Mar 26 01:12:52 PM PDT 24 |
12042703208 ps |
| T200 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.212508111 |
|
|
Mar 26 01:00:43 PM PDT 24 |
Mar 26 01:18:23 PM PDT 24 |
14876332678 ps |
| T43 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3635020378 |
|
|
Mar 26 01:06:05 PM PDT 24 |
Mar 26 01:06:39 PM PDT 24 |
1193797167 ps |
| T201 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.306897513 |
|
|
Mar 26 01:07:20 PM PDT 24 |
Mar 26 01:11:29 PM PDT 24 |
14814280886 ps |
| T202 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1815121469 |
|
|
Mar 26 01:01:14 PM PDT 24 |
Mar 26 01:13:10 PM PDT 24 |
15128127753 ps |
| T203 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3473660831 |
|
|
Mar 26 01:05:54 PM PDT 24 |
Mar 26 01:08:23 PM PDT 24 |
10134137553 ps |
| T44 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1227613122 |
|
|
Mar 26 01:04:11 PM PDT 24 |
Mar 26 01:04:24 PM PDT 24 |
1746921337 ps |
| T122 |
/workspace/coverage/default/11.sram_ctrl_regwen.2748424700 |
|
|
Mar 26 01:00:18 PM PDT 24 |
Mar 26 01:31:19 PM PDT 24 |
4893021216 ps |
| T204 |
/workspace/coverage/default/47.sram_ctrl_bijection.2894234311 |
|
|
Mar 26 01:08:06 PM PDT 24 |
Mar 26 01:25:09 PM PDT 24 |
64860573919 ps |
| T205 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3030496664 |
|
|
Mar 26 01:07:18 PM PDT 24 |
Mar 26 01:09:57 PM PDT 24 |
19905184622 ps |
| T206 |
/workspace/coverage/default/14.sram_ctrl_bijection.2247701034 |
|
|
Mar 26 01:01:01 PM PDT 24 |
Mar 26 01:36:01 PM PDT 24 |
469438476632 ps |
| T207 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.310633981 |
|
|
Mar 26 01:01:15 PM PDT 24 |
Mar 26 01:06:46 PM PDT 24 |
12477003960 ps |
| T208 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.3735743242 |
|
|
Mar 26 12:58:48 PM PDT 24 |
Mar 26 12:58:51 PM PDT 24 |
343141805 ps |
| T209 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2164472583 |
|
|
Mar 26 01:06:18 PM PDT 24 |
Mar 26 01:09:39 PM PDT 24 |
4181242119 ps |
| T210 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3623307628 |
|
|
Mar 26 12:59:21 PM PDT 24 |
Mar 26 01:00:14 PM PDT 24 |
9275221071 ps |
| T211 |
/workspace/coverage/default/22.sram_ctrl_alert_test.3386478428 |
|
|
Mar 26 01:02:24 PM PDT 24 |
Mar 26 01:02:25 PM PDT 24 |
51077726 ps |
| T212 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1707844215 |
|
|
Mar 26 01:07:29 PM PDT 24 |
Mar 26 01:09:27 PM PDT 24 |
17770146779 ps |
| T213 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3054915167 |
|
|
Mar 26 01:02:42 PM PDT 24 |
Mar 26 01:02:45 PM PDT 24 |
692481616 ps |
| T214 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3327565066 |
|
|
Mar 26 01:07:55 PM PDT 24 |
Mar 26 01:13:54 PM PDT 24 |
4976456062 ps |
| T215 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.657237276 |
|
|
Mar 26 12:59:09 PM PDT 24 |
Mar 26 01:00:34 PM PDT 24 |
2419162359 ps |
| T216 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.694378650 |
|
|
Mar 26 01:05:09 PM PDT 24 |
Mar 26 01:11:21 PM PDT 24 |
15477783653 ps |
| T217 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2448768369 |
|
|
Mar 26 01:05:21 PM PDT 24 |
Mar 26 01:05:22 PM PDT 24 |
39346033 ps |
| T218 |
/workspace/coverage/default/43.sram_ctrl_regwen.2461226412 |
|
|
Mar 26 01:07:18 PM PDT 24 |
Mar 26 01:39:41 PM PDT 24 |
24628588165 ps |
| T219 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1944031535 |
|
|
Mar 26 01:05:08 PM PDT 24 |
Mar 26 01:05:09 PM PDT 24 |
14999786 ps |
| T220 |
/workspace/coverage/default/31.sram_ctrl_executable.505505765 |
|
|
Mar 26 01:04:21 PM PDT 24 |
Mar 26 01:26:01 PM PDT 24 |
23636077330 ps |
| T221 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.874433401 |
|
|
Mar 26 12:59:32 PM PDT 24 |
Mar 26 01:00:44 PM PDT 24 |
3487776198 ps |
| T45 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.740717888 |
|
|
Mar 26 01:00:41 PM PDT 24 |
Mar 26 01:01:22 PM PDT 24 |
8575307086 ps |
| T222 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1484138540 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:24:51 PM PDT 24 |
18564945608 ps |
| T223 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2147919517 |
|
|
Mar 26 01:01:45 PM PDT 24 |
Mar 26 01:01:59 PM PDT 24 |
761734325 ps |
| T224 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3722431462 |
|
|
Mar 26 01:06:18 PM PDT 24 |
Mar 26 01:06:40 PM PDT 24 |
9151320983 ps |
| T225 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1315869293 |
|
|
Mar 26 01:04:36 PM PDT 24 |
Mar 26 01:22:56 PM PDT 24 |
6102570467 ps |
| T226 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.942457949 |
|
|
Mar 26 12:59:10 PM PDT 24 |
Mar 26 01:08:08 PM PDT 24 |
22864752110 ps |
| T227 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2774860300 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:05:19 PM PDT 24 |
11799214240 ps |
| T228 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.4019542788 |
|
|
Mar 26 01:03:18 PM PDT 24 |
Mar 26 01:28:56 PM PDT 24 |
17864704259 ps |
| T229 |
/workspace/coverage/default/34.sram_ctrl_bijection.860463633 |
|
|
Mar 26 01:04:56 PM PDT 24 |
Mar 26 01:20:53 PM PDT 24 |
370345352152 ps |
| T230 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3832577221 |
|
|
Mar 26 01:07:55 PM PDT 24 |
Mar 26 02:25:04 PM PDT 24 |
186587684542 ps |
| T231 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1180651931 |
|
|
Mar 26 01:05:08 PM PDT 24 |
Mar 26 01:56:17 PM PDT 24 |
100268207695 ps |
| T232 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3792554350 |
|
|
Mar 26 01:02:11 PM PDT 24 |
Mar 26 01:03:17 PM PDT 24 |
4759247062 ps |
| T233 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1578148027 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:06:09 PM PDT 24 |
4018403453 ps |
| T234 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3910497740 |
|
|
Mar 26 12:59:01 PM PDT 24 |
Mar 26 01:18:29 PM PDT 24 |
58279221839 ps |
| T235 |
/workspace/coverage/default/40.sram_ctrl_smoke.17255274 |
|
|
Mar 26 01:06:18 PM PDT 24 |
Mar 26 01:06:40 PM PDT 24 |
5507235675 ps |
| T236 |
/workspace/coverage/default/47.sram_ctrl_alert_test.2779075468 |
|
|
Mar 26 01:08:21 PM PDT 24 |
Mar 26 01:08:24 PM PDT 24 |
16232913 ps |
| T237 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1589017424 |
|
|
Mar 26 01:03:54 PM PDT 24 |
Mar 26 01:31:51 PM PDT 24 |
17576850317 ps |
| T238 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.1576106736 |
|
|
Mar 26 01:06:34 PM PDT 24 |
Mar 26 01:09:12 PM PDT 24 |
57506631476 ps |
| T239 |
/workspace/coverage/default/30.sram_ctrl_executable.1472247413 |
|
|
Mar 26 01:04:14 PM PDT 24 |
Mar 26 01:13:27 PM PDT 24 |
5114249407 ps |
| T240 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.670749959 |
|
|
Mar 26 01:04:37 PM PDT 24 |
Mar 26 01:07:07 PM PDT 24 |
4989488552 ps |
| T241 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2653330613 |
|
|
Mar 26 01:03:13 PM PDT 24 |
Mar 26 01:04:12 PM PDT 24 |
3663344814 ps |
| T242 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1386304505 |
|
|
Mar 26 01:06:18 PM PDT 24 |
Mar 26 01:07:23 PM PDT 24 |
5593304111 ps |
| T243 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1250311827 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:06:45 PM PDT 24 |
10334994417 ps |
| T244 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1088041529 |
|
|
Mar 26 01:02:57 PM PDT 24 |
Mar 26 01:03:00 PM PDT 24 |
1365340884 ps |
| T245 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.502950309 |
|
|
Mar 26 01:07:04 PM PDT 24 |
Mar 26 01:15:50 PM PDT 24 |
127752276768 ps |
| T246 |
/workspace/coverage/default/6.sram_ctrl_bijection.3906486938 |
|
|
Mar 26 12:58:59 PM PDT 24 |
Mar 26 01:09:24 PM PDT 24 |
29017926193 ps |
| T247 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.181363131 |
|
|
Mar 26 01:04:12 PM PDT 24 |
Mar 26 01:04:54 PM PDT 24 |
2906573761 ps |
| T248 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3999259259 |
|
|
Mar 26 01:02:30 PM PDT 24 |
Mar 26 01:03:12 PM PDT 24 |
6484004495 ps |
| T249 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1796885623 |
|
|
Mar 26 12:59:32 PM PDT 24 |
Mar 26 12:59:33 PM PDT 24 |
52660950 ps |
| T250 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2952140227 |
|
|
Mar 26 12:58:12 PM PDT 24 |
Mar 26 12:58:41 PM PDT 24 |
4590792521 ps |
| T251 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.100301641 |
|
|
Mar 26 01:06:20 PM PDT 24 |
Mar 26 01:17:29 PM PDT 24 |
6861115731 ps |
| T252 |
/workspace/coverage/default/24.sram_ctrl_executable.2667639774 |
|
|
Mar 26 01:02:56 PM PDT 24 |
Mar 26 01:20:17 PM PDT 24 |
16708665662 ps |
| T253 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1690687084 |
|
|
Mar 26 01:05:08 PM PDT 24 |
Mar 26 01:05:47 PM PDT 24 |
3010694010 ps |
| T254 |
/workspace/coverage/default/19.sram_ctrl_stress_all.561839958 |
|
|
Mar 26 01:01:57 PM PDT 24 |
Mar 26 02:02:59 PM PDT 24 |
254309068499 ps |
| T255 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2738577818 |
|
|
Mar 26 01:03:18 PM PDT 24 |
Mar 26 01:09:39 PM PDT 24 |
70817460103 ps |
| T256 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1282562025 |
|
|
Mar 26 01:00:18 PM PDT 24 |
Mar 26 01:01:39 PM PDT 24 |
56581289320 ps |
| T257 |
/workspace/coverage/default/38.sram_ctrl_smoke.3090515542 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:06:11 PM PDT 24 |
4434977580 ps |
| T46 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1099788237 |
|
|
Mar 26 12:59:58 PM PDT 24 |
Mar 26 01:00:09 PM PDT 24 |
514153202 ps |
| T258 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3703583850 |
|
|
Mar 26 12:58:59 PM PDT 24 |
Mar 26 01:00:09 PM PDT 24 |
9373277954 ps |
| T47 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3453969836 |
|
|
Mar 26 01:06:19 PM PDT 24 |
Mar 26 01:06:30 PM PDT 24 |
717389551 ps |
| T259 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2317214661 |
|
|
Mar 26 12:58:49 PM PDT 24 |
Mar 26 01:14:01 PM PDT 24 |
10884529409 ps |
| T260 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1403801692 |
|
|
Mar 26 01:07:55 PM PDT 24 |
Mar 26 02:16:54 PM PDT 24 |
106037093739 ps |
| T261 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.3284747948 |
|
|
Mar 26 01:06:06 PM PDT 24 |
Mar 26 01:06:24 PM PDT 24 |
2927587537 ps |
| T262 |
/workspace/coverage/default/15.sram_ctrl_smoke.1380528786 |
|
|
Mar 26 01:01:13 PM PDT 24 |
Mar 26 01:01:31 PM PDT 24 |
5063612057 ps |
| T263 |
/workspace/coverage/default/3.sram_ctrl_stress_all.883800979 |
|
|
Mar 26 12:58:50 PM PDT 24 |
Mar 26 02:07:57 PM PDT 24 |
1417521265850 ps |
| T264 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3141346446 |
|
|
Mar 26 01:08:05 PM PDT 24 |
Mar 26 01:11:37 PM PDT 24 |
15456071843 ps |
| T103 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2548805076 |
|
|
Mar 26 01:01:29 PM PDT 24 |
Mar 26 01:01:38 PM PDT 24 |
918678307 ps |
| T265 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2541194267 |
|
|
Mar 26 01:08:45 PM PDT 24 |
Mar 26 01:10:41 PM PDT 24 |
2637696738 ps |
| T266 |
/workspace/coverage/default/15.sram_ctrl_executable.4290964472 |
|
|
Mar 26 01:01:16 PM PDT 24 |
Mar 26 01:15:23 PM PDT 24 |
30038992914 ps |
| T267 |
/workspace/coverage/default/30.sram_ctrl_partial_access.593631287 |
|
|
Mar 26 01:04:14 PM PDT 24 |
Mar 26 01:06:12 PM PDT 24 |
1277988105 ps |
| T268 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3352791500 |
|
|
Mar 26 01:07:55 PM PDT 24 |
Mar 26 01:13:39 PM PDT 24 |
4459495474 ps |
| T269 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.713501231 |
|
|
Mar 26 01:01:59 PM PDT 24 |
Mar 26 01:11:55 PM PDT 24 |
7224514744 ps |
| T270 |
/workspace/coverage/default/9.sram_ctrl_smoke.346979006 |
|
|
Mar 26 12:59:30 PM PDT 24 |
Mar 26 01:01:06 PM PDT 24 |
4906324608 ps |
| T271 |
/workspace/coverage/default/36.sram_ctrl_partial_access.3234383008 |
|
|
Mar 26 01:05:21 PM PDT 24 |
Mar 26 01:06:05 PM PDT 24 |
459651355 ps |
| T272 |
/workspace/coverage/default/17.sram_ctrl_regwen.866076493 |
|
|
Mar 26 01:01:28 PM PDT 24 |
Mar 26 01:09:19 PM PDT 24 |
5628243977 ps |
| T273 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.603074073 |
|
|
Mar 26 01:04:37 PM PDT 24 |
Mar 26 01:05:50 PM PDT 24 |
4905284465 ps |
| T274 |
/workspace/coverage/default/9.sram_ctrl_alert_test.2314207257 |
|
|
Mar 26 12:59:54 PM PDT 24 |
Mar 26 12:59:55 PM PDT 24 |
13032109 ps |
| T275 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.633336999 |
|
|
Mar 26 01:01:48 PM PDT 24 |
Mar 26 01:03:13 PM PDT 24 |
44773849624 ps |
| T276 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3275975264 |
|
|
Mar 26 12:58:38 PM PDT 24 |
Mar 26 12:59:31 PM PDT 24 |
1272157150 ps |
| T277 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2596669530 |
|
|
Mar 26 01:03:06 PM PDT 24 |
Mar 26 01:03:07 PM PDT 24 |
39489952 ps |
| T278 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.895113781 |
|
|
Mar 26 01:03:07 PM PDT 24 |
Mar 26 01:06:40 PM PDT 24 |
13230540980 ps |
| T279 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1087091599 |
|
|
Mar 26 01:02:41 PM PDT 24 |
Mar 26 01:06:50 PM PDT 24 |
3985388675 ps |
| T280 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2426545326 |
|
|
Mar 26 01:04:33 PM PDT 24 |
Mar 26 02:08:00 PM PDT 24 |
448065488416 ps |
| T281 |
/workspace/coverage/default/35.sram_ctrl_stress_all.2951127913 |
|
|
Mar 26 01:05:20 PM PDT 24 |
Mar 26 02:05:42 PM PDT 24 |
606124142488 ps |
| T282 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.3821099675 |
|
|
Mar 26 01:05:55 PM PDT 24 |
Mar 26 01:05:59 PM PDT 24 |
394050711 ps |
| T283 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1426509997 |
|
|
Mar 26 01:00:18 PM PDT 24 |
Mar 26 01:06:32 PM PDT 24 |
6730853445 ps |
| T284 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2646911173 |
|
|
Mar 26 12:59:32 PM PDT 24 |
Mar 26 12:59:36 PM PDT 24 |
695187605 ps |
| T285 |
/workspace/coverage/default/13.sram_ctrl_regwen.1112169448 |
|
|
Mar 26 01:00:43 PM PDT 24 |
Mar 26 01:05:33 PM PDT 24 |
37277512595 ps |
| T286 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.2406439399 |
|
|
Mar 26 01:08:07 PM PDT 24 |
Mar 26 01:08:26 PM PDT 24 |
1423143008 ps |
| T287 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.354365798 |
|
|
Mar 26 01:05:49 PM PDT 24 |
Mar 26 01:16:50 PM PDT 24 |
12863026088 ps |
| T288 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3853619191 |
|
|
Mar 26 01:02:30 PM PDT 24 |
Mar 26 01:09:00 PM PDT 24 |
64347021835 ps |
| T289 |
/workspace/coverage/default/22.sram_ctrl_regwen.3762948932 |
|
|
Mar 26 01:02:23 PM PDT 24 |
Mar 26 01:07:02 PM PDT 24 |
1602762623 ps |
| T290 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.1817215862 |
|
|
Mar 26 01:03:13 PM PDT 24 |
Mar 26 01:05:23 PM PDT 24 |
7172902173 ps |
| T291 |
/workspace/coverage/default/0.sram_ctrl_bijection.2686983592 |
|
|
Mar 26 12:58:15 PM PDT 24 |
Mar 26 01:44:57 PM PDT 24 |
175881297333 ps |
| T292 |
/workspace/coverage/default/7.sram_ctrl_alert_test.4184834318 |
|
|
Mar 26 12:59:21 PM PDT 24 |
Mar 26 12:59:23 PM PDT 24 |
23176416 ps |
| T293 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3899035055 |
|
|
Mar 26 01:08:22 PM PDT 24 |
Mar 26 01:14:52 PM PDT 24 |
6733406250 ps |
| T294 |
/workspace/coverage/default/19.sram_ctrl_executable.983789349 |
|
|
Mar 26 01:01:58 PM PDT 24 |
Mar 26 01:02:05 PM PDT 24 |
2031692706 ps |
| T295 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.482895158 |
|
|
Mar 26 01:02:00 PM PDT 24 |
Mar 26 01:02:03 PM PDT 24 |
1344657039 ps |