Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	133089642	1			T1	196606		T2	1145		T3	144179
triple_byte_access	2857120	1			T2	30		T4	49		T5	93
halfword_access	4380296	1			T2	44		T4	78		T5	118
byte_access	6123921	1			T2	41		T4	103		T5	174
zero_access	1847781	1			T2	4		T4	24		T5	51

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73912078

1

T1

65536

T2

598

T3

720896

auto[1]

74386682

1

T1

131070

T2

666

T3

720896

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	66178910	1			T1	65536		T2	541		T3	720896
auto[0]	triple_byte_access	1364292	1			T2	20		T4	30		T5	47
auto[0]	halfword_access	2138482	1			T2	18		T4	38		T5	52
auto[0]	byte_access	3131110	1			T2	17		T4	53		T5	88
auto[0]	zero_access	1099284	1			T2	2		T4	9		T5	24
auto[1]	word_access	66910732	1			T1	131070		T2	604		T3	720896
auto[1]	triple_byte_access	1492828	1			T2	10		T4	19		T5	46
auto[1]	halfword_access	2241814	1			T2	26		T4	40		T5	66
auto[1]	byte_access	2992811	1			T2	24		T4	50		T5	86
auto[1]	zero_access	748497	1			T2	2		T4	15		T5	27