Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	346187418	1			T1	135648		T2	506824		T5	6382
instr_valid_dis	303197099	1			T1	106300		T2	506824		T5	6382
instr_en	34573582	1			T1	47812		T6	59962		T14	15336

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14037814	1			T1	14360		T6	65036		T14	11100
sram_ifetch_valid_disable	306185373	1			T1	119486		T2	506824		T5	6382
sram_ifetch_enable	25964231	1			T1	147262		T6	168968		T14	101168

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	346187418	1			T1	135648		T2	506824		T5	6382
hw_debug_en_valid_off	304597713	1			T1	125228		T2	506824		T5	6382
hw_debug_en_on	24788999	1			T1	77250		T6	143896		T14	41934

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	306185373	1			T1	119486		T2	506824		T5	6382
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	285094557	1			T1	106300		T2	506824		T5	6382
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	17335459	1			T1	19256		T6	10438		T19	55020
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	7315214	1			T1	14360		T6	58444		T14	11100
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1936964	1			T6	32352		T8	50442		T29	9172
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4772172	1			T6	16746		T14	11100		T29	26282
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4900064	1			T6	6592		T19	3818		T8	172476
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2464350	1			T6	6592		T8	132226		T58	19088
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1695560	1			T123	45564		T124	16826		T36	24176
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11834086	1			T1	20000		T6	69716		T19	17168
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6585390	1			T6	41812		T8	43802		T29	14412
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3511470	1			T6	10438		T8	1184		T58	12042

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9908983	1			T1	28556		T6	32778		T14	4236
lc_exec_en	8054849	1			T1	57250		T6	67588		T14	41934
valid_exec_dis	296869043	1			T1	115561		T2	506824		T5	6382
invalid_exec_dis	40002045	1			T1	161622		T6	234004		T14	112268