| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3160922376 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1505743337 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2310578954 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4075971928 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.253605651 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1729587732 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1934285236 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3844520887 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3258716044 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.96513378 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2123245874 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2622294819 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2088214185 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3928960917 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2414723168 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.697901944 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3613151904 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3640848669 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3997125789 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2544175154 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.993859605 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3576710447 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3379722615 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1147318901 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3505670008 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1104036782 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3805831332 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.133655594 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.656884316 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3335124976 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4105268669 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3377909000 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4017948089 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.881640242 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1969814266 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1203406604 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3779147168 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3608671016 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2996411608 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.121304032 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3568087624 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1081056872 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.161291058 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.498445754 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3901956390 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4176896437 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1580973831 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1320691271 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1898237452 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2859885484 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2601442662 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1622762464 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3580502764 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4201247040 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4114801544 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2579469722 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3812345690 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1919299400 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2666534547 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2933246049 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1530851060 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3538876935 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.397176415 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.842955284 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3479742121 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3287383009 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1696837109 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2642137217 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.190536803 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1787586919 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2167490462 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4196801332 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3160454575 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.696536870 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2736216712 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.772439593 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1656135214 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.150837400 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1240118828 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3951253031 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2378355760 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3811392130 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1200489745 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1616952245 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1520630499 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3478862331 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1484097280 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1477232065 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2342973593 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2654564760 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3033618922 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.487953597 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2169466222 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.690563533 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.433468750 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3428725713 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3985382919 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2800905373 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.639759427 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2653040944 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3792976799 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1912116545 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3632328802 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2278435033 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2959407503 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4212528657 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2714693937 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4238363324 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1237788113 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3317866764 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3960989447 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3198487936 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3455312740 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.217087657 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3169187933 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.638875417 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2248950807 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.389254583 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2017208532 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1078067814 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.288340773 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2369531963 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3397309514 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.159407150 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1032384634 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2336836014 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2585828139 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4137425174 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2036397690 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2857179210 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1448324332 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3521180353 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.3479105714 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1194028562 |
| /workspace/coverage/default/0.sram_ctrl_executable.2486449702 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.502774257 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1217626714 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.355390178 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.1230783741 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3164165134 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.1551329964 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.388832181 |
| /workspace/coverage/default/0.sram_ctrl_regwen.549017558 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.2859708708 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2176611581 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2967841823 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4257247447 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.147311244 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3901566253 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1727594765 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.4042823189 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3518210477 |
| /workspace/coverage/default/1.sram_ctrl_executable.1436346950 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.852805370 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1929449653 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.334108676 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2106341624 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2017696581 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.515600151 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4221843672 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.3235073641 |
| /workspace/coverage/default/1.sram_ctrl_regwen.4069650498 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.2638996996 |
| /workspace/coverage/default/1.sram_ctrl_smoke.732818315 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.2001767205 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4035525023 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.225876317 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3757033588 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2781568460 |
| /workspace/coverage/default/10.sram_ctrl_bijection.463211104 |
| /workspace/coverage/default/10.sram_ctrl_executable.865685902 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.2570920708 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.760666340 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.787228080 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3998158534 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1024988236 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.1827644195 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4156614308 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3508821277 |
| /workspace/coverage/default/10.sram_ctrl_regwen.2901084990 |
| /workspace/coverage/default/10.sram_ctrl_smoke.912543881 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3364587880 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1868384138 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.4109821895 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.286713028 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3198040686 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.4293658853 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1335784239 |
| /workspace/coverage/default/11.sram_ctrl_executable.3767088947 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.32549298 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.3850912464 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.963746161 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.596664793 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.616778278 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1199954645 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3499765079 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2743390937 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2830472142 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1939535208 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.115124590 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1820820958 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2986159363 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.623724039 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1006787565 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.843496335 |
| /workspace/coverage/default/12.sram_ctrl_bijection.3300119562 |
| /workspace/coverage/default/12.sram_ctrl_executable.1271255708 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3736411438 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.1528466178 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3331284816 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.241249925 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.217096854 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.157790355 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.915088373 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.2181395068 |
| /workspace/coverage/default/12.sram_ctrl_regwen.3655304167 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1461782673 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.3228424090 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.641782657 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2730320379 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.48876308 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1459703735 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.711779295 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2912092913 |
| /workspace/coverage/default/13.sram_ctrl_executable.3944819923 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.894180839 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3144015720 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2801717590 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3063690968 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.3756270253 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.1989799626 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2612979336 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.465986777 |
| /workspace/coverage/default/13.sram_ctrl_regwen.3698917475 |
| /workspace/coverage/default/13.sram_ctrl_smoke.3261237573 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.725947078 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.469536539 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1779357915 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3115724986 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1598134457 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.995832863 |
| /workspace/coverage/default/14.sram_ctrl_bijection.3866204221 |
| /workspace/coverage/default/14.sram_ctrl_executable.1397689796 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1533085056 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2204143304 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.415130815 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.4197636821 |
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| /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3396392809 |
| /workspace/coverage/default/42.sram_ctrl_stress_pipeline.294296773 |
| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2798528235 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3415257548 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.2092367080 |
| /workspace/coverage/default/43.sram_ctrl_bijection.3599876368 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.571199204 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.2956403026 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3520004809 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.1549186601 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.3269565935 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.3036493088 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2085207341 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.4025806081 |
| /workspace/coverage/default/43.sram_ctrl_regwen.2130861213 |
| /workspace/coverage/default/43.sram_ctrl_smoke.3372189977 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.356688103 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3044118248 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.4192365308 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1205106540 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3082507483 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.785475302 |
| /workspace/coverage/default/44.sram_ctrl_bijection.1134380182 |
| /workspace/coverage/default/44.sram_ctrl_executable.1854420869 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.249877426 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.2411902689 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2586693620 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.1995485646 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1799484325 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2858667532 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2658293020 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.779288091 |
| /workspace/coverage/default/44.sram_ctrl_regwen.1486513903 |
| /workspace/coverage/default/44.sram_ctrl_smoke.3484237289 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.1112729341 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2938524386 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.348470836 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.165566685 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.166616438 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1728960983 |
| /workspace/coverage/default/45.sram_ctrl_bijection.386487 |
| /workspace/coverage/default/45.sram_ctrl_executable.250748162 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.1948439216 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.498670613 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.750211948 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.267110652 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.901350766 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.3644549236 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2414712730 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.1084961743 |
| /workspace/coverage/default/45.sram_ctrl_regwen.4078048540 |
| /workspace/coverage/default/45.sram_ctrl_smoke.476109403 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.2059234599 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1854105759 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3572682903 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4170369022 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2095481045 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.2003924302 |
| /workspace/coverage/default/46.sram_ctrl_bijection.2420963835 |
| /workspace/coverage/default/46.sram_ctrl_executable.2517333778 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.1770570495 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.2543395441 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1272997535 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.3354254727 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.330584879 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.2952311215 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2796207719 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.1608644791 |
| /workspace/coverage/default/46.sram_ctrl_regwen.3837201897 |
| /workspace/coverage/default/46.sram_ctrl_smoke.2949872129 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.1267692909 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2559310370 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.102083178 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1852501884 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.333906993 |
| /workspace/coverage/default/47.sram_ctrl_executable.3034780144 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.2233642094 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.1373621652 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.660887195 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.737583712 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.675523905 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2876796637 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1454638411 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3065330573 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3304503948 |
| /workspace/coverage/default/47.sram_ctrl_smoke.1098800517 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.4170312470 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1477715585 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3552449159 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2624812453 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1146745961 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1062858757 |
| /workspace/coverage/default/48.sram_ctrl_bijection.698380516 |
| /workspace/coverage/default/48.sram_ctrl_executable.2722206590 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.3316776186 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.3329536897 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2840763476 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.346971502 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2094836171 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.2193223377 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2630283353 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3086849513 |
| /workspace/coverage/default/48.sram_ctrl_regwen.3110638525 |
| /workspace/coverage/default/48.sram_ctrl_smoke.2974604683 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.136011447 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3744263016 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.4149719024 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2403205823 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.4268993644 |
| /workspace/coverage/default/49.sram_ctrl_bijection.4090174094 |
| /workspace/coverage/default/49.sram_ctrl_executable.14759446 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.913382368 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2897475167 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2756874729 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.367945833 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.2009824195 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.1510590812 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.484833526 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1871076731 |
| /workspace/coverage/default/49.sram_ctrl_regwen.610212444 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3326574345 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3892991942 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2882346052 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1052596602 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4142920652 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4198010771 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.4091845111 |
| /workspace/coverage/default/5.sram_ctrl_bijection.254489664 |
| /workspace/coverage/default/5.sram_ctrl_executable.895023798 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.1521558113 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.3344482512 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1801074018 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.1189804412 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.426405890 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1577100727 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2977520085 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.229916528 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3278452936 |
| /workspace/coverage/default/5.sram_ctrl_smoke.1986229006 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.585192905 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.884858825 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.21680935 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1500595699 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.635171463 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3276107034 |
| /workspace/coverage/default/6.sram_ctrl_bijection.459576005 |
| /workspace/coverage/default/6.sram_ctrl_executable.3047888253 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.3836611933 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.3170277779 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3600665014 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.1578088832 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3360512845 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.1332784429 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.665599096 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.3800175060 |
| /workspace/coverage/default/6.sram_ctrl_regwen.2500966253 |
| /workspace/coverage/default/6.sram_ctrl_smoke.2519940637 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.1879955331 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1196438787 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2791624314 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1513855989 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3671673029 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2417659111 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2754023153 |
| /workspace/coverage/default/7.sram_ctrl_executable.2402316209 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.589971215 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2096596614 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3224289670 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.2005345691 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1901105575 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.2123382938 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1714476626 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.381423482 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3706563254 |
| /workspace/coverage/default/7.sram_ctrl_smoke.4080714301 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2560005478 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.976289313 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1500070848 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2298766256 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3756333974 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3978823925 |
| /workspace/coverage/default/8.sram_ctrl_bijection.655858991 |
| /workspace/coverage/default/8.sram_ctrl_executable.3542869519 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.240464920 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.2000640204 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.250515509 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1991937764 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.3847343070 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3016450558 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.94997508 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3857522041 |
| /workspace/coverage/default/8.sram_ctrl_regwen.566388845 |
| /workspace/coverage/default/8.sram_ctrl_smoke.1205118930 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.1830068309 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2985179293 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3572823510 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.232278377 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1029207235 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1475480714 |
| /workspace/coverage/default/9.sram_ctrl_bijection.796510408 |
| /workspace/coverage/default/9.sram_ctrl_executable.1892358446 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.2591076803 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.3275611845 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.530090364 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3166936041 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.4062690553 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.832661516 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3238672143 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2369095286 |
| /workspace/coverage/default/9.sram_ctrl_regwen.4077925147 |
| /workspace/coverage/default/9.sram_ctrl_smoke.2166580773 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.667066424 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2748195246 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3372717904 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3515471594 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 03:25:00 PM PDT 24 |
340437401995 ps |
| T2 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3398435848 |
|
|
Mar 28 02:47:25 PM PDT 24 |
Mar 28 02:52:46 PM PDT 24 |
14460712118 ps |
| T3 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1542816968 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:49:44 PM PDT 24 |
4215249960 ps |
| T5 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3478245563 |
|
|
Mar 28 02:46:27 PM PDT 24 |
Mar 28 02:46:47 PM PDT 24 |
1346626114 ps |
| T9 |
/workspace/coverage/default/17.sram_ctrl_bijection.3214317134 |
|
|
Mar 28 02:46:09 PM PDT 24 |
Mar 28 03:30:56 PM PDT 24 |
460230085410 ps |
| T10 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.760666340 |
|
|
Mar 28 02:45:05 PM PDT 24 |
Mar 28 02:45:17 PM PDT 24 |
1374895538 ps |
| T11 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3170277779 |
|
|
Mar 28 02:44:31 PM PDT 24 |
Mar 28 02:45:37 PM PDT 24 |
4565734849 ps |
| T4 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1424774437 |
|
|
Mar 28 02:45:51 PM PDT 24 |
Mar 28 02:56:49 PM PDT 24 |
13143508104 ps |
| T12 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1528466178 |
|
|
Mar 28 02:45:27 PM PDT 24 |
Mar 28 02:45:57 PM PDT 24 |
710353348 ps |
| T13 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2204143304 |
|
|
Mar 28 02:45:48 PM PDT 24 |
Mar 28 02:46:03 PM PDT 24 |
2791986529 ps |
| T6 |
/workspace/coverage/default/3.sram_ctrl_executable.3611414196 |
|
|
Mar 28 02:43:57 PM PDT 24 |
Mar 28 03:11:53 PM PDT 24 |
24474120157 ps |
| T22 |
/workspace/coverage/default/2.sram_ctrl_alert_test.4021987713 |
|
|
Mar 28 02:43:58 PM PDT 24 |
Mar 28 02:43:59 PM PDT 24 |
44662865 ps |
| T14 |
/workspace/coverage/default/33.sram_ctrl_executable.4196842550 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:55:13 PM PDT 24 |
5138766425 ps |
| T15 |
/workspace/coverage/default/26.sram_ctrl_smoke.425114719 |
|
|
Mar 28 02:47:56 PM PDT 24 |
Mar 28 02:48:58 PM PDT 24 |
758933174 ps |
| T16 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2541307674 |
|
|
Mar 28 02:47:26 PM PDT 24 |
Mar 28 02:48:39 PM PDT 24 |
15763915514 ps |
| T32 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.949689251 |
|
|
Mar 28 02:49:07 PM PDT 24 |
Mar 28 02:49:10 PM PDT 24 |
348422301 ps |
| T17 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.426405890 |
|
|
Mar 28 02:44:17 PM PDT 24 |
Mar 28 03:03:43 PM PDT 24 |
9084238419 ps |
| T18 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.702078529 |
|
|
Mar 28 02:50:12 PM PDT 24 |
Mar 28 03:04:36 PM PDT 24 |
64829195406 ps |
| T19 |
/workspace/coverage/default/0.sram_ctrl_executable.2486449702 |
|
|
Mar 28 02:43:40 PM PDT 24 |
Mar 28 03:01:20 PM PDT 24 |
23084604593 ps |
| T70 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3860009120 |
|
|
Mar 28 02:46:08 PM PDT 24 |
Mar 28 02:51:30 PM PDT 24 |
17905066116 ps |
| T30 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1120461243 |
|
|
Mar 28 02:53:39 PM PDT 24 |
Mar 28 02:54:23 PM PDT 24 |
3088534444 ps |
| T28 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2882346052 |
|
|
Mar 28 02:53:56 PM PDT 24 |
Mar 28 02:54:25 PM PDT 24 |
1146712116 ps |
| T7 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.32549298 |
|
|
Mar 28 02:45:05 PM PDT 24 |
Mar 28 02:46:18 PM PDT 24 |
93071853397 ps |
| T23 |
/workspace/coverage/default/33.sram_ctrl_alert_test.564178023 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:49:42 PM PDT 24 |
42466567 ps |
| T53 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.986184005 |
|
|
Mar 28 02:46:27 PM PDT 24 |
Mar 28 02:47:32 PM PDT 24 |
992050739 ps |
| T8 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1448768495 |
|
|
Mar 28 02:50:30 PM PDT 24 |
Mar 28 03:40:16 PM PDT 24 |
58676635036 ps |
| T24 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2026692003 |
|
|
Mar 28 02:45:08 PM PDT 24 |
Mar 28 02:45:09 PM PDT 24 |
31638672 ps |
| T20 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.708142447 |
|
|
Mar 28 02:53:14 PM PDT 24 |
Mar 28 03:09:54 PM PDT 24 |
57226555123 ps |
| T54 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1934836246 |
|
|
Mar 28 02:49:08 PM PDT 24 |
Mar 28 02:51:33 PM PDT 24 |
18795399695 ps |
| T55 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.571199204 |
|
|
Mar 28 02:51:59 PM PDT 24 |
Mar 28 02:53:34 PM PDT 24 |
18488645083 ps |
| T33 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.229916528 |
|
|
Mar 28 02:44:14 PM PDT 24 |
Mar 28 02:44:17 PM PDT 24 |
346537555 ps |
| T56 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.293579630 |
|
|
Mar 28 02:47:27 PM PDT 24 |
Mar 28 02:48:42 PM PDT 24 |
13470080575 ps |
| T138 |
/workspace/coverage/default/30.sram_ctrl_partial_access.3468467809 |
|
|
Mar 28 02:48:38 PM PDT 24 |
Mar 28 02:49:47 PM PDT 24 |
855696472 ps |
| T57 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.868963355 |
|
|
Mar 28 02:50:36 PM PDT 24 |
Mar 28 02:51:25 PM PDT 24 |
7812249124 ps |
| T58 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2059234599 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 05:00:57 PM PDT 24 |
358839216919 ps |
| T95 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1437675427 |
|
|
Mar 28 02:47:09 PM PDT 24 |
Mar 28 02:50:36 PM PDT 24 |
42240984526 ps |
| T78 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.653882666 |
|
|
Mar 28 02:47:26 PM PDT 24 |
Mar 28 02:49:26 PM PDT 24 |
6718463965 ps |
| T96 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3214004880 |
|
|
Mar 28 02:46:15 PM PDT 24 |
Mar 28 02:48:12 PM PDT 24 |
10924366028 ps |
| T139 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.779288091 |
|
|
Mar 28 02:52:34 PM PDT 24 |
Mar 28 02:52:38 PM PDT 24 |
1467358874 ps |
| T140 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3756270253 |
|
|
Mar 28 02:45:26 PM PDT 24 |
Mar 28 02:57:02 PM PDT 24 |
63391258898 ps |
| T141 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1367561097 |
|
|
Mar 28 02:46:13 PM PDT 24 |
Mar 28 02:46:16 PM PDT 24 |
348298723 ps |
| T142 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3174324161 |
|
|
Mar 28 02:46:48 PM PDT 24 |
Mar 28 02:46:51 PM PDT 24 |
698286233 ps |
| T143 |
/workspace/coverage/default/4.sram_ctrl_partial_access.973656275 |
|
|
Mar 28 02:43:58 PM PDT 24 |
Mar 28 02:44:03 PM PDT 24 |
1654472935 ps |
| T97 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1730895191 |
|
|
Mar 28 02:51:12 PM PDT 24 |
Mar 28 02:57:56 PM PDT 24 |
7911339371 ps |
| T144 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3939148132 |
|
|
Mar 28 02:46:47 PM PDT 24 |
Mar 28 02:51:38 PM PDT 24 |
13876021899 ps |
| T98 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1131974543 |
|
|
Mar 28 02:48:39 PM PDT 24 |
Mar 28 02:52:40 PM PDT 24 |
7137213569 ps |
| T145 |
/workspace/coverage/default/39.sram_ctrl_smoke.139565518 |
|
|
Mar 28 02:50:50 PM PDT 24 |
Mar 28 02:51:40 PM PDT 24 |
1035842997 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3553734835 |
|
|
Mar 28 02:43:59 PM PDT 24 |
Mar 28 02:44:12 PM PDT 24 |
506256121 ps |
| T29 |
/workspace/coverage/default/22.sram_ctrl_stress_all.689967127 |
|
|
Mar 28 02:47:14 PM PDT 24 |
Mar 28 05:13:07 PM PDT 24 |
472423041682 ps |
| T123 |
/workspace/coverage/default/23.sram_ctrl_executable.2023292402 |
|
|
Mar 28 02:47:13 PM PDT 24 |
Mar 28 03:00:09 PM PDT 24 |
18683607506 ps |
| T137 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2417659111 |
|
|
Mar 28 02:44:30 PM PDT 24 |
Mar 28 02:44:32 PM PDT 24 |
20339330 ps |
| T45 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1830068309 |
|
|
Mar 28 02:44:50 PM PDT 24 |
Mar 28 04:18:47 PM PDT 24 |
186632829115 ps |
| T59 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2200110521 |
|
|
Mar 28 02:48:20 PM PDT 24 |
Mar 28 02:49:24 PM PDT 24 |
33461335330 ps |
| T136 |
/workspace/coverage/default/38.sram_ctrl_executable.126786876 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:54:18 PM PDT 24 |
3787344883 ps |
| T111 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.240464920 |
|
|
Mar 28 02:44:34 PM PDT 24 |
Mar 28 02:45:35 PM PDT 24 |
33544825980 ps |
| T21 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2969434851 |
|
|
Mar 28 02:47:11 PM PDT 24 |
Mar 28 03:04:50 PM PDT 24 |
11178105718 ps |
| T46 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1255889167 |
|
|
Mar 28 02:50:11 PM PDT 24 |
Mar 28 02:51:18 PM PDT 24 |
9947957155 ps |
| T146 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1728960983 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 02:52:57 PM PDT 24 |
32633645 ps |
| T147 |
/workspace/coverage/default/15.sram_ctrl_smoke.2371139901 |
|
|
Mar 28 02:45:50 PM PDT 24 |
Mar 28 02:46:06 PM PDT 24 |
1037821652 ps |
| T99 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2203551348 |
|
|
Mar 28 02:45:48 PM PDT 24 |
Mar 28 02:52:30 PM PDT 24 |
65251362795 ps |
| T148 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3329536897 |
|
|
Mar 28 02:53:36 PM PDT 24 |
Mar 28 02:55:47 PM PDT 24 |
4238962065 ps |
| T124 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1727418262 |
|
|
Mar 28 02:50:17 PM PDT 24 |
Mar 28 04:01:01 PM PDT 24 |
131143798873 ps |
| T149 |
/workspace/coverage/default/13.sram_ctrl_smoke.3261237573 |
|
|
Mar 28 02:45:25 PM PDT 24 |
Mar 28 02:45:57 PM PDT 24 |
972624772 ps |
| T100 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2597899738 |
|
|
Mar 28 02:44:03 PM PDT 24 |
Mar 28 02:49:07 PM PDT 24 |
241696282600 ps |
| T47 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.884858825 |
|
|
Mar 28 02:44:14 PM PDT 24 |
Mar 28 02:44:46 PM PDT 24 |
1186032743 ps |
| T150 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2947119947 |
|
|
Mar 28 02:48:21 PM PDT 24 |
Mar 28 02:48:26 PM PDT 24 |
702582909 ps |
| T79 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1083780412 |
|
|
Mar 28 02:44:02 PM PDT 24 |
Mar 28 02:46:16 PM PDT 24 |
6449126622 ps |
| T80 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1062560053 |
|
|
Mar 28 02:44:01 PM PDT 24 |
Mar 28 02:45:43 PM PDT 24 |
17381249489 ps |
| T151 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.4234450446 |
|
|
Mar 28 02:50:53 PM PDT 24 |
Mar 28 02:50:57 PM PDT 24 |
348038821 ps |
| T25 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1109821022 |
|
|
Mar 28 02:43:59 PM PDT 24 |
Mar 28 02:44:02 PM PDT 24 |
1328250175 ps |
| T36 |
/workspace/coverage/default/40.sram_ctrl_regwen.4095280755 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 03:08:14 PM PDT 24 |
5176268517 ps |
| T37 |
/workspace/coverage/default/47.sram_ctrl_stress_all.4170312470 |
|
|
Mar 28 02:53:15 PM PDT 24 |
Mar 28 04:08:33 PM PDT 24 |
157538782289 ps |
| T38 |
/workspace/coverage/default/33.sram_ctrl_bijection.983159881 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 03:28:13 PM PDT 24 |
195491142876 ps |
| T39 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.4282174903 |
|
|
Mar 28 02:50:30 PM PDT 24 |
Mar 28 02:50:35 PM PDT 24 |
489152076 ps |
| T40 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2009824195 |
|
|
Mar 28 02:53:39 PM PDT 24 |
Mar 28 03:04:10 PM PDT 24 |
7866954463 ps |
| T41 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3850912464 |
|
|
Mar 28 02:45:05 PM PDT 24 |
Mar 28 02:47:19 PM PDT 24 |
3048212921 ps |
| T42 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3096040951 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 02:52:15 PM PDT 24 |
1099389518 ps |
| T43 |
/workspace/coverage/default/20.sram_ctrl_bijection.2234770411 |
|
|
Mar 28 02:46:37 PM PDT 24 |
Mar 28 03:16:47 PM PDT 24 |
110490751092 ps |
| T44 |
/workspace/coverage/default/7.sram_ctrl_smoke.4080714301 |
|
|
Mar 28 02:44:29 PM PDT 24 |
Mar 28 02:44:53 PM PDT 24 |
3935514774 ps |
| T152 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2012469397 |
|
|
Mar 28 02:48:46 PM PDT 24 |
Mar 28 02:53:15 PM PDT 24 |
21754555742 ps |
| T153 |
/workspace/coverage/default/26.sram_ctrl_regwen.2826945332 |
|
|
Mar 28 02:47:54 PM PDT 24 |
Mar 28 03:04:23 PM PDT 24 |
4061164712 ps |
| T154 |
/workspace/coverage/default/5.sram_ctrl_regwen.3278452936 |
|
|
Mar 28 02:44:16 PM PDT 24 |
Mar 28 02:55:06 PM PDT 24 |
5870088510 ps |
| T155 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1852501884 |
|
|
Mar 28 02:52:58 PM PDT 24 |
Mar 28 02:54:12 PM PDT 24 |
3149651954 ps |
| T156 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.2218974784 |
|
|
Mar 28 02:43:58 PM PDT 24 |
Mar 28 02:48:30 PM PDT 24 |
9394293426 ps |
| T157 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2458871751 |
|
|
Mar 28 02:47:54 PM PDT 24 |
Mar 28 02:53:16 PM PDT 24 |
19632586163 ps |
| T158 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1402428557 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 02:52:25 PM PDT 24 |
1479146418 ps |
| T159 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3707803837 |
|
|
Mar 28 02:48:20 PM PDT 24 |
Mar 28 02:48:50 PM PDT 24 |
962391011 ps |
| T125 |
/workspace/coverage/default/19.sram_ctrl_executable.1091875825 |
|
|
Mar 28 02:46:28 PM PDT 24 |
Mar 28 03:05:47 PM PDT 24 |
21302329412 ps |
| T160 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1449258266 |
|
|
Mar 28 02:48:23 PM PDT 24 |
Mar 28 02:53:56 PM PDT 24 |
86074224947 ps |
| T81 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3607448514 |
|
|
Mar 28 02:44:00 PM PDT 24 |
Mar 28 02:53:36 PM PDT 24 |
11227584817 ps |
| T161 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2577836125 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 02:51:22 PM PDT 24 |
739118713 ps |
| T162 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2411902689 |
|
|
Mar 28 02:52:32 PM PDT 24 |
Mar 28 02:54:38 PM PDT 24 |
784908409 ps |
| T163 |
/workspace/coverage/default/24.sram_ctrl_bijection.3073377392 |
|
|
Mar 28 02:47:26 PM PDT 24 |
Mar 28 03:01:01 PM PDT 24 |
194005034365 ps |
| T126 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2967841823 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 03:56:18 PM PDT 24 |
75610561261 ps |
| T26 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2638996996 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:43:45 PM PDT 24 |
428673153 ps |
| T164 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3800175060 |
|
|
Mar 28 02:44:32 PM PDT 24 |
Mar 28 02:44:36 PM PDT 24 |
1342610583 ps |
| T165 |
/workspace/coverage/default/23.sram_ctrl_smoke.4280513976 |
|
|
Mar 28 02:47:10 PM PDT 24 |
Mar 28 02:49:25 PM PDT 24 |
497565310 ps |
| T166 |
/workspace/coverage/default/6.sram_ctrl_executable.3047888253 |
|
|
Mar 28 02:44:30 PM PDT 24 |
Mar 28 02:53:25 PM PDT 24 |
4919816905 ps |
| T90 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1459703735 |
|
|
Mar 28 02:45:48 PM PDT 24 |
Mar 28 03:02:23 PM PDT 24 |
50286871365 ps |
| T167 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3167937426 |
|
|
Mar 28 02:46:07 PM PDT 24 |
Mar 28 03:37:23 PM PDT 24 |
250237519657 ps |
| T131 |
/workspace/coverage/default/5.sram_ctrl_stress_all.585192905 |
|
|
Mar 28 02:44:14 PM PDT 24 |
Mar 28 04:15:37 PM PDT 24 |
156146115540 ps |
| T168 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.218255407 |
|
|
Mar 28 02:46:09 PM PDT 24 |
Mar 28 03:02:57 PM PDT 24 |
37911010933 ps |
| T127 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3688961303 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 02:53:44 PM PDT 24 |
5965015525 ps |
| T128 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2586693620 |
|
|
Mar 28 02:52:33 PM PDT 24 |
Mar 28 02:55:21 PM PDT 24 |
21630695218 ps |
| T169 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3754246151 |
|
|
Mar 28 02:50:30 PM PDT 24 |
Mar 28 02:50:33 PM PDT 24 |
556199005 ps |
| T170 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.394321069 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 02:49:23 PM PDT 24 |
3340531052 ps |
| T27 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3404527796 |
|
|
Mar 28 02:44:13 PM PDT 24 |
Mar 28 02:44:15 PM PDT 24 |
195892538 ps |
| T171 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1733277604 |
|
|
Mar 28 02:48:38 PM PDT 24 |
Mar 28 02:48:41 PM PDT 24 |
350889541 ps |
| T135 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2840763476 |
|
|
Mar 28 02:53:40 PM PDT 24 |
Mar 28 02:56:12 PM PDT 24 |
23310838884 ps |
| T172 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.787228080 |
|
|
Mar 28 02:45:10 PM PDT 24 |
Mar 28 02:47:46 PM PDT 24 |
10612201879 ps |
| T173 |
/workspace/coverage/default/4.sram_ctrl_bijection.3425906963 |
|
|
Mar 28 02:43:56 PM PDT 24 |
Mar 28 03:09:37 PM PDT 24 |
72821801801 ps |
| T48 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3512950343 |
|
|
Mar 28 02:50:30 PM PDT 24 |
Mar 28 02:50:49 PM PDT 24 |
2428298429 ps |
| T174 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2795213420 |
|
|
Mar 28 02:48:59 PM PDT 24 |
Mar 28 02:51:45 PM PDT 24 |
17686692557 ps |
| T175 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3572682903 |
|
|
Mar 28 02:52:33 PM PDT 24 |
Mar 28 02:57:48 PM PDT 24 |
5810030655 ps |
| T176 |
/workspace/coverage/default/10.sram_ctrl_smoke.912543881 |
|
|
Mar 28 02:44:50 PM PDT 24 |
Mar 28 02:46:40 PM PDT 24 |
873017376 ps |
| T177 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3130443995 |
|
|
Mar 28 02:48:57 PM PDT 24 |
Mar 28 02:53:42 PM PDT 24 |
6454468055 ps |
| T178 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1106598797 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:43:46 PM PDT 24 |
353024224 ps |
| T179 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.4268940262 |
|
|
Mar 28 02:47:10 PM PDT 24 |
Mar 28 02:52:31 PM PDT 24 |
48263316828 ps |
| T180 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4147854720 |
|
|
Mar 28 02:50:36 PM PDT 24 |
Mar 28 02:50:43 PM PDT 24 |
709266567 ps |
| T181 |
/workspace/coverage/default/41.sram_ctrl_executable.4093416441 |
|
|
Mar 28 02:51:34 PM PDT 24 |
Mar 28 03:11:02 PM PDT 24 |
10682528934 ps |
| T182 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3959884460 |
|
|
Mar 28 02:47:54 PM PDT 24 |
Mar 28 02:48:07 PM PDT 24 |
695247072 ps |
| T183 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2791624314 |
|
|
Mar 28 02:44:14 PM PDT 24 |
Mar 28 02:47:33 PM PDT 24 |
12528732584 ps |
| T184 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1230934278 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 02:58:09 PM PDT 24 |
19402291802 ps |
| T185 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3076043547 |
|
|
Mar 28 02:46:07 PM PDT 24 |
Mar 28 03:03:11 PM PDT 24 |
53871767442 ps |
| T186 |
/workspace/coverage/default/25.sram_ctrl_regwen.865890315 |
|
|
Mar 28 02:47:55 PM PDT 24 |
Mar 28 02:58:12 PM PDT 24 |
10107941810 ps |
| T187 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.147769737 |
|
|
Mar 28 02:48:20 PM PDT 24 |
Mar 28 02:51:07 PM PDT 24 |
12682793898 ps |
| T188 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2369154850 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 02:51:48 PM PDT 24 |
783241838 ps |
| T189 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3644549236 |
|
|
Mar 28 02:52:57 PM PDT 24 |
Mar 28 02:53:11 PM PDT 24 |
1866251469 ps |
| T190 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2193223377 |
|
|
Mar 28 02:53:39 PM PDT 24 |
Mar 28 02:56:20 PM PDT 24 |
4447334896 ps |
| T191 |
/workspace/coverage/default/27.sram_ctrl_regwen.515759416 |
|
|
Mar 28 02:48:23 PM PDT 24 |
Mar 28 03:08:47 PM PDT 24 |
8803166191 ps |
| T192 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4112260900 |
|
|
Mar 28 02:48:41 PM PDT 24 |
Mar 28 02:57:05 PM PDT 24 |
26393764835 ps |
| T193 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1235668779 |
|
|
Mar 28 02:50:32 PM PDT 24 |
Mar 28 02:52:56 PM PDT 24 |
27152085024 ps |
| T194 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3273984601 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:58:14 PM PDT 24 |
22127650145 ps |
| T195 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1577100727 |
|
|
Mar 28 02:44:17 PM PDT 24 |
Mar 28 02:47:05 PM PDT 24 |
4711815018 ps |
| T196 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3472847422 |
|
|
Mar 28 02:43:40 PM PDT 24 |
Mar 28 02:49:49 PM PDT 24 |
52640127231 ps |
| T197 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3345666571 |
|
|
Mar 28 02:45:48 PM PDT 24 |
Mar 28 02:46:26 PM PDT 24 |
6344281055 ps |
| T198 |
/workspace/coverage/default/46.sram_ctrl_partial_access.2952311215 |
|
|
Mar 28 02:52:57 PM PDT 24 |
Mar 28 02:55:09 PM PDT 24 |
1708769707 ps |
| T49 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2213752091 |
|
|
Mar 28 02:47:26 PM PDT 24 |
Mar 28 02:50:14 PM PDT 24 |
1623022664 ps |
| T199 |
/workspace/coverage/default/46.sram_ctrl_bijection.2420963835 |
|
|
Mar 28 02:52:58 PM PDT 24 |
Mar 28 03:29:23 PM PDT 24 |
200180529848 ps |
| T200 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.48876308 |
|
|
Mar 28 02:45:26 PM PDT 24 |
Mar 28 02:46:22 PM PDT 24 |
1702654330 ps |
| T201 |
/workspace/coverage/default/38.sram_ctrl_alert_test.729979876 |
|
|
Mar 28 02:50:53 PM PDT 24 |
Mar 28 02:50:54 PM PDT 24 |
75124887 ps |
| T202 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2001767205 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 03:28:02 PM PDT 24 |
63995950798 ps |
| T203 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1196684324 |
|
|
Mar 28 02:49:19 PM PDT 24 |
Mar 28 02:50:05 PM PDT 24 |
8092921353 ps |
| T204 |
/workspace/coverage/default/15.sram_ctrl_bijection.4153283032 |
|
|
Mar 28 02:45:50 PM PDT 24 |
Mar 28 03:13:33 PM PDT 24 |
24484114116 ps |
| T205 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2105708823 |
|
|
Mar 28 02:51:35 PM PDT 24 |
Mar 28 02:53:58 PM PDT 24 |
3316676902 ps |
| T206 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1515269927 |
|
|
Mar 28 02:43:59 PM PDT 24 |
Mar 28 02:46:25 PM PDT 24 |
19887148283 ps |
| T207 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3634561411 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:44:14 PM PDT 24 |
757344034 ps |
| T208 |
/workspace/coverage/default/2.sram_ctrl_smoke.2959937695 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:43:50 PM PDT 24 |
1418482402 ps |
| T209 |
/workspace/coverage/default/29.sram_ctrl_bijection.2166346422 |
|
|
Mar 28 02:48:39 PM PDT 24 |
Mar 28 03:02:33 PM PDT 24 |
12721062598 ps |
| T210 |
/workspace/coverage/default/1.sram_ctrl_executable.1436346950 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:59:03 PM PDT 24 |
33952168079 ps |
| T211 |
/workspace/coverage/default/6.sram_ctrl_regwen.2500966253 |
|
|
Mar 28 02:44:28 PM PDT 24 |
Mar 28 02:56:51 PM PDT 24 |
21271176234 ps |
| T212 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3256361230 |
|
|
Mar 28 02:45:52 PM PDT 24 |
Mar 28 02:46:16 PM PDT 24 |
3493174142 ps |
| T213 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3100225618 |
|
|
Mar 28 02:47:54 PM PDT 24 |
Mar 28 02:47:59 PM PDT 24 |
344707197 ps |
| T214 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3063690968 |
|
|
Mar 28 02:45:52 PM PDT 24 |
Mar 28 02:48:16 PM PDT 24 |
7173121261 ps |
| T215 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2658293020 |
|
|
Mar 28 02:52:33 PM PDT 24 |
Mar 28 02:56:33 PM PDT 24 |
10278944800 ps |
| T216 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2798528235 |
|
|
Mar 28 02:52:00 PM PDT 24 |
Mar 28 02:53:33 PM PDT 24 |
1511821425 ps |
| T217 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2467555331 |
|
|
Mar 28 02:48:21 PM PDT 24 |
Mar 28 02:53:14 PM PDT 24 |
47914175967 ps |
| T50 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2251802009 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:51:03 PM PDT 24 |
6081853921 ps |
| T218 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.497236747 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 02:54:29 PM PDT 24 |
87888978080 ps |
| T219 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.3857566981 |
|
|
Mar 28 02:47:14 PM PDT 24 |
Mar 28 03:05:12 PM PDT 24 |
22192448296 ps |
| T220 |
/workspace/coverage/default/35.sram_ctrl_bijection.2818629456 |
|
|
Mar 28 02:50:12 PM PDT 24 |
Mar 28 03:32:57 PM PDT 24 |
392073250661 ps |
| T221 |
/workspace/coverage/default/24.sram_ctrl_stress_all.2895293006 |
|
|
Mar 28 02:47:28 PM PDT 24 |
Mar 28 04:30:23 PM PDT 24 |
87512797772 ps |
| T222 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.952363314 |
|
|
Mar 28 02:45:52 PM PDT 24 |
Mar 28 02:52:27 PM PDT 24 |
7208105627 ps |
| T223 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1024988236 |
|
|
Mar 28 02:44:51 PM PDT 24 |
Mar 28 02:58:19 PM PDT 24 |
7692206022 ps |
| T224 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.355390178 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:45:03 PM PDT 24 |
9025726506 ps |
| T225 |
/workspace/coverage/default/16.sram_ctrl_alert_test.1399396226 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:46:12 PM PDT 24 |
30240371 ps |
| T226 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.901350766 |
|
|
Mar 28 02:52:33 PM PDT 24 |
Mar 28 03:11:33 PM PDT 24 |
26859812570 ps |
| T227 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1533085056 |
|
|
Mar 28 02:45:51 PM PDT 24 |
Mar 28 02:46:47 PM PDT 24 |
12100488766 ps |
| T228 |
/workspace/coverage/default/28.sram_ctrl_smoke.2098942587 |
|
|
Mar 28 02:48:21 PM PDT 24 |
Mar 28 02:48:42 PM PDT 24 |
1751693022 ps |
| T229 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.918935239 |
|
|
Mar 28 02:47:27 PM PDT 24 |
Mar 28 03:12:51 PM PDT 24 |
95940122143 ps |
| T230 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2410926219 |
|
|
Mar 28 02:46:26 PM PDT 24 |
Mar 28 02:46:26 PM PDT 24 |
14774777 ps |
| T130 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1052419823 |
|
|
Mar 28 02:43:58 PM PDT 24 |
Mar 28 03:12:57 PM PDT 24 |
25755933499 ps |
| T51 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4065198559 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:50:40 PM PDT 24 |
219391719 ps |
| T52 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1178749173 |
|
|
Mar 28 02:46:47 PM PDT 24 |
Mar 28 02:47:01 PM PDT 24 |
1528673468 ps |
| T231 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1305070345 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 02:53:45 PM PDT 24 |
13788580425 ps |
| T232 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1066460340 |
|
|
Mar 28 02:46:49 PM PDT 24 |
Mar 28 02:49:16 PM PDT 24 |
1311337176 ps |
| T233 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3866765804 |
|
|
Mar 28 02:47:14 PM PDT 24 |
Mar 28 02:48:06 PM PDT 24 |
1879104250 ps |
| T234 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.688170085 |
|
|
Mar 28 02:51:13 PM PDT 24 |
Mar 28 02:52:21 PM PDT 24 |
967477669 ps |
| T235 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3044118248 |
|
|
Mar 28 02:52:31 PM PDT 24 |
Mar 28 02:52:41 PM PDT 24 |
1118910256 ps |
| T236 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3754709172 |
|
|
Mar 28 02:50:10 PM PDT 24 |
Mar 28 02:51:03 PM PDT 24 |
30016203768 ps |
| T237 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1521558113 |
|
|
Mar 28 02:44:15 PM PDT 24 |
Mar 28 02:44:58 PM PDT 24 |
7755438068 ps |
| T132 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.905031833 |
|
|
Mar 28 02:47:13 PM PDT 24 |
Mar 28 03:16:35 PM PDT 24 |
53044251162 ps |
| T238 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3031613869 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 02:50:10 PM PDT 24 |
99921438 ps |
| T239 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.737583712 |
|
|
Mar 28 02:53:15 PM PDT 24 |
Mar 28 02:57:10 PM PDT 24 |
4110925360 ps |
| T240 |
/workspace/coverage/default/45.sram_ctrl_executable.250748162 |
|
|
Mar 28 02:53:00 PM PDT 24 |
Mar 28 03:05:09 PM PDT 24 |
26412551076 ps |
| T241 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2938524386 |
|
|
Mar 28 02:52:32 PM PDT 24 |
Mar 28 02:56:09 PM PDT 24 |
5087457251 ps |
| T105 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3982830186 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:46:40 PM PDT 24 |
3092542899 ps |
| T242 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.852805370 |
|
|
Mar 28 02:43:46 PM PDT 24 |
Mar 28 02:44:36 PM PDT 24 |
26746873726 ps |
| T243 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1403949810 |
|
|
Mar 28 02:45:52 PM PDT 24 |
Mar 28 02:50:47 PM PDT 24 |
55150128928 ps |
| T244 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2781568460 |
|
|
Mar 28 02:45:05 PM PDT 24 |
Mar 28 02:57:40 PM PDT 24 |
13961788426 ps |
| T245 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3243867076 |
|
|
Mar 28 02:45:48 PM PDT 24 |
Mar 28 02:47:29 PM PDT 24 |
1525594181 ps |
| T246 |
/workspace/coverage/default/13.sram_ctrl_alert_test.711779295 |
|
|
Mar 28 02:45:52 PM PDT 24 |
Mar 28 02:45:53 PM PDT 24 |
31232046 ps |
| T247 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.1233694271 |
|
|
Mar 28 02:46:14 PM PDT 24 |
Mar 28 02:48:53 PM PDT 24 |
17526991034 ps |
| T248 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.4119502294 |
|
|
Mar 28 02:45:47 PM PDT 24 |
Mar 28 02:45:58 PM PDT 24 |
464128735 ps |
| T249 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3703050637 |
|
|
Mar 28 02:50:31 PM PDT 24 |
Mar 28 02:54:19 PM PDT 24 |
11853942709 ps |
| T106 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3078084078 |
|
|
Mar 28 02:48:22 PM PDT 24 |
Mar 28 02:48:54 PM PDT 24 |
1102865821 ps |
| T250 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2908976295 |
|
|
Mar 28 02:51:58 PM PDT 24 |
Mar 28 02:52:02 PM PDT 24 |
1769586904 ps |
| T251 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3280622858 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 03:16:50 PM PDT 24 |
14568402062 ps |
| T107 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.714561080 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 02:50:35 PM PDT 24 |
804952100 ps |
| T252 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3736411438 |
|
|
Mar 28 02:45:24 PM PDT 24 |
Mar 28 02:46:45 PM PDT 24 |
145034676410 ps |
| T253 |
/workspace/coverage/default/41.sram_ctrl_regwen.989858242 |
|
|
Mar 28 02:51:33 PM PDT 24 |
Mar 28 02:57:06 PM PDT 24 |
2649498771 ps |
| T254 |
/workspace/coverage/default/12.sram_ctrl_alert_test.843496335 |
|
|
Mar 28 02:45:28 PM PDT 24 |
Mar 28 02:45:29 PM PDT 24 |
44580326 ps |
| T255 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2298766256 |
|
|
Mar 28 02:44:34 PM PDT 24 |
Mar 28 02:44:52 PM PDT 24 |
2824379071 ps |
| T256 |
/workspace/coverage/default/47.sram_ctrl_alert_test.333906993 |
|
|
Mar 28 02:53:21 PM PDT 24 |
Mar 28 02:53:22 PM PDT 24 |
27928700 ps |
| T257 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.46200016 |
|
|
Mar 28 02:50:51 PM PDT 24 |
Mar 28 03:00:20 PM PDT 24 |
21773484270 ps |
| T258 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3028970434 |
|
|
Mar 28 02:46:29 PM PDT 24 |
Mar 28 02:48:37 PM PDT 24 |
1979620609 ps |
| T259 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4142920652 |
|
|
Mar 28 02:53:36 PM PDT 24 |
Mar 28 02:53:44 PM PDT 24 |
681270687 ps |
| T260 |
/workspace/coverage/default/36.sram_ctrl_bijection.2601975658 |
|
|
Mar 28 02:50:12 PM PDT 24 |
Mar 28 03:27:10 PM PDT 24 |
43572603586 ps |
| T261 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2295532875 |
|
|
Mar 28 02:49:42 PM PDT 24 |
Mar 28 02:49:55 PM PDT 24 |
1915260982 ps |
| T262 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1727594765 |
|
|
Mar 28 02:43:41 PM PDT 24 |
Mar 28 02:48:34 PM PDT 24 |
10800983975 ps |
| T263 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2765307078 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 02:50:09 PM PDT 24 |
13481080 ps |
| T264 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.4044053626 |
|
|
Mar 28 02:46:50 PM PDT 24 |
Mar 28 02:46:58 PM PDT 24 |
691189377 ps |
| T265 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1267692909 |
|
|
Mar 28 02:52:56 PM PDT 24 |
Mar 28 04:27:12 PM PDT 24 |
518656099312 ps |
| T266 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.588317725 |
|
|
Mar 28 02:47:55 PM PDT 24 |
Mar 28 02:49:53 PM PDT 24 |
815033093 ps |
| T267 |
/workspace/coverage/default/44.sram_ctrl_bijection.1134380182 |
|
|
Mar 28 02:52:37 PM PDT 24 |
Mar 28 03:19:11 PM PDT 24 |
69104332058 ps |
| T268 |
/workspace/coverage/default/33.sram_ctrl_regwen.1680459406 |
|
|
Mar 28 02:49:41 PM PDT 24 |
Mar 28 02:56:37 PM PDT 24 |
13633545628 ps |
| T269 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1281684497 |
|
|
Mar 28 02:46:49 PM PDT 24 |
Mar 28 03:13:49 PM PDT 24 |
56790994531 ps |
| T270 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.4208332832 |
|
|
Mar 28 02:47:10 PM PDT 24 |
Mar 28 02:48:07 PM PDT 24 |
18696651172 ps |
| T271 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3479105714 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:43:44 PM PDT 24 |
13718981 ps |
| T272 |
/workspace/coverage/default/24.sram_ctrl_regwen.3559368875 |
|
|
Mar 28 02:47:28 PM PDT 24 |
Mar 28 03:04:41 PM PDT 24 |
18362221041 ps |
| T129 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.429427775 |
|
|
Mar 28 02:47:10 PM PDT 24 |
Mar 28 02:52:14 PM PDT 24 |
129781505873 ps |
| T273 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1205106540 |
|
|
Mar 28 02:51:58 PM PDT 24 |
Mar 28 02:54:01 PM PDT 24 |
3004290938 ps |
| T274 |
/workspace/coverage/default/31.sram_ctrl_bijection.298786928 |
|
|
Mar 28 02:48:58 PM PDT 24 |
Mar 28 03:25:49 PM PDT 24 |
62221260604 ps |
| T275 |
/workspace/coverage/default/49.sram_ctrl_executable.14759446 |
|
|
Mar 28 02:53:37 PM PDT 24 |
Mar 28 03:09:07 PM PDT 24 |
17374130997 ps |
| T276 |
/workspace/coverage/default/9.sram_ctrl_regwen.4077925147 |
|
|
Mar 28 02:44:49 PM PDT 24 |
Mar 28 03:10:14 PM PDT 24 |
61382620634 ps |
| T277 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.4174609958 |
|
|
Mar 28 02:50:13 PM PDT 24 |
Mar 28 02:52:44 PM PDT 24 |
2832477558 ps |
| T278 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.250515509 |
|
|
Mar 28 02:44:51 PM PDT 24 |
Mar 28 02:47:24 PM PDT 24 |
4706445186 ps |
| T279 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2998477519 |
|
|
Mar 28 02:50:35 PM PDT 24 |
Mar 28 02:56:47 PM PDT 24 |
95349930475 ps |
| T280 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4192365308 |
|
|
Mar 28 02:51:59 PM PDT 24 |
Mar 28 02:54:36 PM PDT 24 |
2569088321 ps |
| T281 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.38834591 |
|
|
Mar 28 02:50:49 PM PDT 24 |
Mar 28 03:04:40 PM PDT 24 |
10516585947 ps |
| T282 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3757033588 |
|
|
Mar 28 02:43:42 PM PDT 24 |
Mar 28 02:44:59 PM PDT 24 |
3048094135 ps |
| T283 |
/workspace/coverage/default/30.sram_ctrl_regwen.1599640978 |
|
|
Mar 28 02:48:46 PM PDT 24 |
Mar 28 03:03:54 PM PDT 24 |
2455558762 ps |
| T284 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.426977605 |
|
|
Mar 28 02:43:43 PM PDT 24 |
Mar 28 02:49:01 PM PDT 24 |
5017496756 ps |
| T285 |
/workspace/coverage/default/39.sram_ctrl_regwen.762606538 |
|
|
Mar 28 02:50:50 PM PDT 24 |
Mar 28 03:07:40 PM PDT 24 |
63865237996 ps |
| T286 |
/workspace/coverage/default/19.sram_ctrl_smoke.2611900814 |
|
|
Mar 28 02:46:27 PM PDT 24 |
Mar 28 02:46:45 PM PDT 24 |
899279294 ps |
| T287 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.748108329 |
|
|
Mar 28 02:48:20 PM PDT 24 |
Mar 28 02:49:25 PM PDT 24 |
1968905582 ps |
| T288 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1313149591 |
|
|
Mar 28 02:47:29 PM PDT 24 |
Mar 28 02:53:34 PM PDT 24 |
6122862157 ps |
| T289 |
/workspace/coverage/default/31.sram_ctrl_smoke.1633877932 |
|
|
Mar 28 02:48:58 PM PDT 24 |
Mar 28 02:49:28 PM PDT 24 |
1007650902 ps |
| T290 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2876796637 |
|
|
Mar 28 02:53:17 PM PDT 24 |
Mar 28 02:53:43 PM PDT 24 |
18157149917 ps |
| T291 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1354823233 |
|
|
Mar 28 02:47:29 PM PDT 24 |
Mar 28 02:47:35 PM PDT 24 |
6742507150 ps |
| T292 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.293002994 |
|
|
Mar 28 02:47:26 PM PDT 24 |
Mar 28 02:50:20 PM PDT 24 |
129249634780 ps |
| T293 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.623724039 |
|
|
Mar 28 02:45:08 PM PDT 24 |
Mar 28 02:45:51 PM PDT 24 |
3048609459 ps |
| T294 |
/workspace/coverage/default/18.sram_ctrl_bijection.4148735568 |
|
|
Mar 28 02:46:12 PM PDT 24 |
Mar 28 03:20:00 PM PDT 24 |
50907618111 ps |
| T295 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3005956990 |
|
|
Mar 28 02:46:37 PM PDT 24 |
Mar 28 02:46:38 PM PDT 24 |
14934949 ps |
| T296 |
/workspace/coverage/default/35.sram_ctrl_executable.4122863627 |
|
|
Mar 28 02:50:09 PM PDT 24 |
Mar 28 03:11:44 PM PDT 24 |
41721317745 ps |
| T297 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3857522041 |
|
|
Mar 28 02:44:36 PM PDT 24 |
Mar 28 02:44:40 PM PDT 24 |
362312507 ps |
| T298 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.4256927063 |
|
|
Mar 28 02:49:42 PM PDT 24 |
Mar 28 02:54:32 PM PDT 24 |
52974143747 ps |
| T299 |
/workspace/coverage/default/39.sram_ctrl_alert_test.707952433 |
|
|
Mar 28 02:51:16 PM PDT 24 |
Mar 28 02:51:17 PM PDT 24 |
42791838 ps |
| T300 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1644687837 |
|
|
Mar 28 02:46:11 PM PDT 24 |
Mar 28 02:46:14 PM PDT 24 |
367924058 ps |
| T301 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.469536539 |
|
|
Mar 28 02:45:52 PM PDT 24 |
Mar 28 02:46:16 PM PDT 24 |
937518297 ps |